CN100589328C - A kind of Reed-Solomon sign indicating number decoder - Google Patents
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Abstract
The present invention relates to a kind of Reed-Solomon sign indicating number decoder (12), comprise from being input to the syndrome computing module that output is electrically connected successively, MEA algoritic module (22), money search module (23), data buffering module (26) between good fortune Buddhist nun's algoritic module (24) and error correction output module (25) and input and the described error correction output module, described input is multibyte bus input, and described MEA algoritic module comprises that one or more reduce by half time-sharing multiplexs that are used for of iterations separately of merging that pass through that are connected in parallel between described syndrome computing module and the money search module handle 8 MEA algorithm submodules (41) that 16 bit data are separately imported.This decoder improves existing MEA algorithm and realizes its time-sharing multiplex, obtains the effect of saving resource, reducing design difficulty when calculating in the bus broadband greater than a byte further combined with parallel syndrome.
Description
Technical Field
The invention relates to digital optical fiber communication, in particular to a Reed-Solomon (RS) code decoder.
Background
Forward error correction techniques are widely used in current digital optical fiber communication systems. In fiber optic communication systems, FEC was first applied to submarine cable communication systems. G.975, promulgated by ITU-T in 1996, proposed the use of FEC as part of the standards for submarine cable communications, with the addition of FEC for the 10Gbit/s system as an option in a new draft that was passed in 4 months of 2000. FTTx technology is increasingly becoming a hotspot in communications networks, as bandwidth bottlenecks have shifted from the backbone network to the access portion. Among the technologies employed by FTTH, a Passive Optical Network (PON) technology is one of the most promising technologies. Currently, two of the most attractive technologies in PON technology are Ethernet Passive Optical Network (EPON) and Gigabit Passive Optical Network (GPON) with an operating rate of more than 1 Gbps. The EPON uses a widely adopted ethernet technology as a link layer protocol, and conforms to the development trend of service IP. GPON is a standard driven by an operator, has a higher rate, can effectively support Time Division Multiplexing (TDM) services and quality of service (QOS), has strong operation, administration and maintenance (OAM) functions, and has higher transmission efficiency. With the development of FTTx, GPON technology is gaining more and more attention. In the standard ITU-T G.984.3 of GPON, FEC techniques of RS (255, 239) coding are employed.
Forward error correction coding (FEC) is used in communication systems to transmit data in an encoded format, typically used in the transport layer. By introducing some redundancy in the encoding, the decoder is enabled to detect and correct the transmitted errors. If the BER of the decoder input data is 10-4Then the BER of the decoder output will be reduced to 10-15. By using FEC techniques, low error rate data transmission can be achieved, thereby avoiding the use of retransmission mechanisms.
Reed-solomon (RS) is a block code, as shown in fig. 1, which can realize low error rate transmission using an RS encoder 11 at the transmitting end and an RS decoder 12 at the receiving end, and uses a data block of a constant size and adds some redundancy bytes at the end, and the data block plus the redundancy bytes constitute a codeword. With these redundancy codes, the FEC decoder can detect, correct errors and recover the original data while processing the data stream. Reed-Solomon codes are specified in detail in ITU-T rec.j.8. The most commonly used RS code is RS (255, 239). The code word of this code is 255 bytes long and consists of 239 bytes of data plus 16 bytes of redundancy. RS (255, 239) is used in both ITU-T Recs G.975 and G.709. When FEC uses block coding, such as RS (255, 239), the original data is retained, i.e., the first 239 bytes of the codeword. Therefore, even if a case occurs in which the other end does not support FEC, omitting the check code can also process the original data.
The Decoder of RS codes generally consists of the following four parts (see documents H.Lee, A High-speed Low-Complexity Reed-Solomon Decoder for Optical Communications, [ J ] IEEETrans. Circuit Syst. -II: Express briefs, vol.52, No.8, pp461-465, Aug 2005): (1) the syndrome computation module (SC) (2) key equation solving module, typically employs a Modified Euclidean (MEA) algorithm that is conveniently implemented in hardware. (3) And the error position and error value solving module is used for solving the error position by adopting a Chien Search algorithm and solving the error value by adopting a Forney algorithm. (4) Data buffer, control and error correction output module. The algorithm is suitable for processing high-speed data (10/40Gbit/s and the like) in optical communication and is realized by using an Application Specific Integrated Circuit (ASIC) technology. However, when the technology is adopted in GPON, the following problems exist: 1) syndrome computation modules use a one-byte broadband data bus, while implementations in Field Programmable Gate Arrays (FPGAs) often use a wider bus to reduce the clock rate. E.g., 2.5Gbit/s, using a 32-bit bus with a clock frequency of 77.76 MHz. 2) The ME algorithm module for solving the key equation is the module occupying most logic resources, 4 parallel processing modules are adopted under the condition of 32-bit bus, and the resource consumption is large.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a Reed-Solomon code decoder, which can reduce the needed ME algorithm modules and further can reduce the hardware working clock frequency by using a wider bus.
The technical problem of the present invention is solved by providing a Reed-Solomon code decoder, which comprises an syndrome calculation module, an improved euclidean algorithm module, a chien search module, a forney algorithm module, an error correction output module and a data buffer module between an input end and the error correction output module, which are electrically connected in sequence from an input to an output, wherein the input is a multi-byte bus input, the improved euclidean algorithm module comprises one or more 8-bit improved euclidean algorithm submodules for time-division multiplexing processing respective 16-bit data inputs by combining and halving respective iteration times, which specifically means that the 8-bit improved euclidean algorithm submodule (41) performs iterative operation, if the last iterative operation is performed, the coefficient of the R (x) polynomial is more than or equal to the coefficient of the Q (x) polynomial, the iteration is directly operated on the basis of the last iteration result, namely the iteration operation and the last iteration operation are combined, so that the total iteration operation time delay is reduced by half; the output of the data input for time division multiplexing processing of the respective 16-bit data, specifically syndrome calculation, is time division multiplexed and sent to the 8-bit improved Euclidean algorithm submodule (41).
In accordance with the decoder provided by the present invention, said modified euclidean algorithm module further comprises one or more common 8-bit modified euclidean algorithm sub-modules connected in parallel between said syndrome calculation module and said chien search module for processing respective 8-bit data inputs, such as: and a decoder (II).
According to the present invention, there is provided a decoder including, but not limited to, the following three:
decoder (one), the said multi-byte is four bytes, the said improved Euclidean algorithm module is two parallel connected between the said syndrome computing module and searching module of the money and is used for the time-sharing multiplexing of processing the respective 16-bit data input of 8-bit improved Euclidean algorithm submodules of the number of iteration each time through combining and halving.
A decoder (two), the multi-byte is three bytes, the modified Euclidean algorithm module is two 8-bit modified Euclidean algorithm sub-modules which are connected in parallel between the syndrome calculation module and the Chien search module, wherein at least one of the modules is used for realizing time division multiplexing by combining and halving the iteration number, one module is used for processing 16-bit data input by realizing time division multiplexing, and the other module is used for processing the remaining 8-bit data input by realizing or not realizing time division multiplexing.
Decoder (three), the said multi-byte is two bytes, the said modified Euclidean algorithm module is a modified Euclidean algorithm submodule of 8 bits used for time-sharing multiplexing processing 16 bit data input of the number of times of half iteration through amalgamation.
According to the decoder provided by the invention, the 8-bit improved Euclidean algorithm submodule comprises a control unit, a polynomial calculation unit and a grade estimation unit, wherein: the control unit and the polynomial calculation unit and the level estimation unit are electrically connected in two directions. The 8-bit modified Euclidean algorithm sub-modules comprise a common 8-bit modified Euclidean algorithm sub-module and a time-division multiplexing 8-bit modified Euclidean algorithm sub-module, and the hardware units of the modules are the same, and only the algorithm (software) is different.
According to the decoder provided by the invention, the specific method for realizing time division multiplexing by combining and halving respective iteration times is as follows: the calculation period of each iteration calculation of the ME algorithm is 16, and in the worst case, 16 iterations are needed to complete the calculation, so the time delay for solving the key equation is 256 clock cycles. In the worst case, Ri(x) And Qi(x) The highest degree of the polynomial of (a) varies as follows:
it can be seen that the iterations of 2, 4, and 16 are only operations, and there is no process of swapping. (from the iterative formula, it can be seen that if deg (R)i-1(x))＜deg(Qi-1(x) Then R) isi(x) And Qi(x) Swapping is required and then the operation is performed. ) Therefore, the iterations of 2, 4, 15 can be directly operated on the basis of the results of the iterations of 1, 3, 5, 15, without resynchronization and exchange. After such processing, the maximum delay of the ME block is only 8 iterations. The highest degree of the polynomial in these 8 iterations varies in the worst case as follows:
the length of the storage space of the polynomial varies as follows:
with a shift register with output taps per stage, the number of stages used of the shift register is reduced by one per iteration, the fixed number of stages for one iteration is 11 stages, and thus the total delay is 119(16+16+15+14+13+12+11+11+ 11). Thus, within a code word period, the modulusThe block can perform two solution operations.
According to the decoder provided by the invention, the syndrome computing module is a syndrome computing module adopting a multi-byte parallel computing mode, and the multi-byte is consistent with the bus input; the calculation avoids bit width conversion, a plurality of calculation modules are not needed, the number of consumed logic units is reduced, and the processing time delay of data is reduced.
In accordance with the decoder provided by the present invention, the syndrome calculation module includes, but is not limited to, a 32-bit syndrome calculation module corresponding to decoder (one), 24-bit syndrome calculation module corresponding to decoder (two), or 16-bit syndrome calculation module corresponding to decoder (three).
According to the decoder provided by the invention, the chien search module, the forney algorithm module and the error correction output module are formed by connecting a plurality of 8-bit corresponding sub-modules which are consistent with a plurality of bytes and used for parallel processing in parallel, and can be matched with 4 of the decoder (I), 3 of the decoder (II) or 2 8-bit corresponding sub-modules of the decoder (III).
According to the decoder provided by the invention, the decoder is applied to a GPON network.
According to the decoder provided by the invention, the decoder is realized by a field programmable gate array or an application specific integrated circuit.
According to the decoder provided by the present invention, said one byte is 8 bits/bit.
According to the Reed-Solomon code decoder provided by the invention, the time-sharing multiplexing is realized by combining and reducing half of the iteration times and improving the existing improved Euclidean algorithm, and the parallel syndrome calculation is further adopted, so that the hardware resource is saved, the complexity is reduced, the hardware logic resource can be saved when the bus broadband is more than one byte, and the effects of saving the circuit resource and reducing the design difficulty are achieved.
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The invention is further described in detail below with reference to the figures and the specific embodiments.
Fig. 1 is a schematic diagram of an application of an RS decoder.
Fig. 2 is a schematic diagram of the circuit structure of the RS decoder.
FIG. 3 is a diagram of a conventional syndrome and MEA algorithm architecture.
FIG. 4 is a schematic diagram of the syndrome and MEA algorithm of the present invention.
Fig. 5 is a schematic diagram of the circuit structure of the RS decoder.
FIG. 6 is a diagram of an input/output interface of the RS decoder shown in FIG. 5
FIG. 7 is a diagram of the input/output interface of the 32-bit syndrome computing module of FIG. 5.
Fig. 8 is a graph of syndrome polynomial computation.
FIG. 9 is a circuit diagram of a 32-bit parallel syndrome computing module of FIG. 5.
FIG. 10 is a block diagram of the interface of the submodule of the MEA algorithm of FIG. 5.
FIG. 11 is a diagram of a submodule of the MEA algorithm of FIG. 5.
Fig. 12 is an interface diagram of the submodule of the chien search algorithm in fig. 5.
Fig. 13 is a schematic interface diagram of the forney algorithm submodule in fig. 5.
Detailed Description
First, the basic decoding algorithm of the present invention is explained:
for RS (255, 239) encoding, the generator polynomial is
Alpha is to generate GF (2)8) Primitive polynomial p (x) x of the field8+x4+x3+x2+1 root.
The syndrome is calculated as
ME algorithm for solving key equation
The key equation is as follows:
S(x)·σ(x)＝ω(x)mod x16
wherein,is a polynomial of the error location,
is a syndrome polynomial and ω (x) is an error calculation polynomial. With S (x) known, the ME algorithm is used to solve for ω (x) and σ (x). The algorithm is as follows:
initialization
R0(x)＝x2t；Q0(x)＝S(x)；L0(x)＝0；U0(x)＝1.
The iteration starts next:
Qi(x)＝σi-1Qi-1(x)+σi-1Ri-1(x)
Ui(x)＝σi-1Ui-1(x)+σi-1Li-1(x)
wherein, ai-1，bi-1Is Ri-1(x) And Qi-1(x) The coefficient of the highest degree. While
li-1＝deg(Ri-1(x))-deg(Qi-1(x))
deg () represents the degree of the polynomial.
After each iteration if deg (R)i(x) Or deg (Q)i(x) Less than 8), the algorithm iteration ends. Where ω (x) is equal to Ri(x)，σ(x)＝Li(x)。
The second step, illustrating the key of the invention:
MEA algorithm module
The ME algorithm for solving the key equation is improved on the basis of the conventional pipeline loop iteration algorithm, so that the module can be time-division multiplexed by two decoding processes, and the time-division multiplexing processing of the MEA algorithm is described by 4 paths of MEA calculation in the following: (data is input in the following manner, '0' indicating that the byte is padded with a 0 value, R254To R0Is a code word)
0 R251......R3 0 R251......R3......
R254 R250......R2 R254 R250......R2......
R253 R249......R1 R253 R249......R1......
R252 R248......R0 R252 R248......R0......
The calculation period of each iteration calculation of the ME algorithm is 16, and in the worst case, 16 iterations are needed to complete the calculation, so the time delay for solving the key equation is 256 clock cycles. In the worst case, Ri(x) And Qi(x) The highest degree of the polynomial of (a) varies as follows: 
it can be seen that the iterations of 2, 4, and 16 are only operations, and there is no process of swapping. (from the iterative formula, it can be seen that if deg (R)i-1(x))＜deg(Qi-1(x) Then R) isi(x) And Qi(x) Swapping is required and then the operation is performed. ) Therefore, the iterations of 2, 4, 15 can be directly operated on the basis of the results of the iterations of 1, 3, 5, 15, without resynchronization and exchange. After such processing, the maximum delay of the ME block is only 8 iterations. The highest degree of the polynomial in these 8 iterations varies in the worst case as follows:
the length of the storage space of the polynomial varies as follows:
with a shift register with output taps per stage, the number of stages used of the shift register is reduced by one per iteration, the fixed number of stages for one iteration is 11 stages, and thus the total delay is 119(16+16+15+14+13+12+11+11+ 11). Thus, in one codeword cycle, the module can perform two solving operations, such as 4 ME calculation modules in the conventional method and only 2 calculation modules in the improved algorithm in the case of 32-bit bus data input.
(II) adjoint module
The traditional syndrome calculation adopts a single byte/8 bit serial input calculation mode, when the input data rate is 2.5Gb/s, the processing clock frequency is 311MHz, and the hardware design is very difficult. If the data bus is widened and the processing clock frequency is reduced, for example, the data bus is converted into a 4 byte/32 bit bus, and the clock frequency is reduced to 77.76MHz, according to the conventional method, as shown in fig. 3, a bit width conversion circuit 31 for converting 32 bits of data into 8 bits needs to be added, and 4 8-bit syndrome calculation modules 32 are needed, and at the same time, 4 8-bit MEA algorithm modules 33 are also needed, that is: the syndrome calculation additionally requires more calculation modules, the number of consumed logic units is large, and meanwhile, the data processing delay is reduced.
In the syndrome calculation module, the syndrome calculation adopts a multi-byte parallel calculation mode to directly calculate in parallel to avoid bit width conversion, a bit width conversion circuit is not needed, and only one calculation module is needed.
Therefore, in conjunction with the keys (one) and (two) of the present invention, corresponding to the apparatus shown in fig. 3, the apparatus of the present invention, as shown in fig. 4, comprises a 32-bit syndrome calculation module 21 and two time-division-multiplexing-enabled MEA algorithm sub-modules 41 of the present invention.
Finally, the invention is explained in detail in connection with a four byte bus input RS decoder of the invention:
as shown in fig. 2, the RS decoder includes a 32-bit syndrome calculation module 21, an MEA algorithm module 22, a chien search module 23, a forney algorithm module 24, and an error correction output module 25 electrically connected in sequence from input to output, and a data buffer FIFO module 26 between an input terminal and the error correction output module 25;
the specific circuit structure of the RS decoder is shown in fig. 5, in which: the MEA algorithm module 22 is formed by connecting two 8-bit MEA algorithm submodules 41 which can be multiplexed in a time-sharing manner in parallel, the money search module 23 is formed by connecting four 8-bit money search submodules 231 in parallel, the Forney algorithm module 24 is formed by connecting four 8-bit Frey algorithm submodules 241 in parallel, and the error correction output module 25 is formed by connecting four 8-bit error correction output submodules 251 in parallel.
The input and output interface of the RS decoder is shown in fig. 6, in which:
an input interface:
clk: system clock
a _ rst: asynchronous reset signal
Code _ vld: data valid signal of the same width as valid data
Data _ start: start of data signal, occurring simultaneously with first valid data
Rn: the 32-bit data input, the first data of each codeword has the highest 8 bits as 0 (used as padding), and the last 16 bytes are error correction coded data.
An output interface:
right: pulse output signal indicating receipt of a correct code word
fail: a pulse output signal for outputting a code word having an error exceeding the error correction capability as it is
Dout _ vld: data output valid signal having the same width as valid output codeword
Dout _ start: data output start signal, which is simultaneously present with first valid output data
Dout: and outputting 32-bit data, wherein the first byte of each code word is not valid data, and only 239 bytes of valid data are output.
The input/output interface of the 32-bit syndrome calculation module 21 in the RS decoder is shown in fig. 7, wherein the 32-bit input interface Rn is the input interface of the decoder; 8-bit output R, S, L, U corresponding to R respectively0(x)、S0(x)、L0(x) And U0(x) It is the initial value required by the ME algorithm module. Since only the syndrome polynomial needs to be calculated, and the others are fixed value outputs, the main function of the module is syndrome calculation; the 32-bit syndrome calculation module circuit is shown in fig. 8, wherein the specific circuit structure of each calculation unit S0-S15 is shown in fig. 9, wherein the addition sign is an exclusive or operation, the multiplication sign is a finite field multiplication operation, a "select" signal is used for serially outputting 16 coefficients of the syndrome after the operation is completed, and a "select 2" signal is used for directly sending the calculation result to the register when the first input data of each codeword is input, so that the register clear operation of one clock cycle is avoided. Multiplication operation of finite fieldi"for each syndrome exponent" i "is a constant value, which can be simplified to a finite field of addition operations according to the operation rules.
The input and output interfaces of the MEA algorithm sub-module 41 in the RS decoder are shown in fig. 10, and the calculation results of the adjoint polynomials of the 32-bit adjoint syndrome calculation module are alternately sent to the two MEA algorithm sub-modules 41 to solve the key equation, wherein the input signals are from the output of the adjoint syndrome calculation module at the previous stage. In the output signal, X0., X8 is the coefficients of the calculated σ (X) polynomial, and W0., W7 is the coefficients of the calculated ω (X) polynomial. The other two output signals are data output indications to the subsequent stages. The circuit structure of the two MEA algorithm submodules 41 is shown in fig. 11, and the two MEA algorithm submodules are consistent with an 8-bit MEA algorithm module which cannot be time-division multiplexed in terms of hardware, and include a control unit 51, a polynomial calculation unit 52, and a level estimation unit 53.
The input and output interfaces of the chien search algorithm submodule 231 in the RS decoder are as shown in fig. 12, and the data output by each MEA algorithm submodule 41 is sent to two subsequent chien search algorithm submodules 231 and the forney algorithm submodule 241 in turn, wherein the input data is X0.., X8, and the signal "start" is used to indicate the start of the input data; the output data "Xout" represents σ (α)i) When it is equal to 0, it indicates that the corresponding position has an error. Output data "deriXout" representation
And calculating results, and providing a Forney algorithm module for use. The output data "err" indicates that the codeword contains a codeword that exceeds the error correction capability. The code word for which the error correction capability is exceeded is determined by: if the highest degree of the input sigma (x) polynomial is equal to the number of error positions, the codeword is in the error correction range, and if the highest degree of the input sigma (x) polynomial is not equal to the number of error positions, the codeword contains uncorrectable errors.
The input/output interface of the forney algorithm submodule 241 in the RS decoder is shown in fig. 13, wherein the input data is W0. The output data "error value" represents an error value.
Claims (10)
1. A Reed-Solomon code decoder, comprising a syndrome calculation module, a modified Euclidean algorithm module (22), a chien search module (23), a Forney algorithm module (24) and an error correction output module (25) which are electrically connected in sequence from input to output, and a data buffer module (26) between the input and the error correction output module, characterized in that the input is a multi-byte bus input, the modified Euclidean algorithm module (22) comprises one or more 8-bit modified Euclidean algorithm submodules (41) connected in parallel between the syndrome calculation module and the chien search module (23) for processing respective 16-bit data inputs by time division multiplexing by combining and halving respective iteration numbers, specifically the 8-bit modified Euclidean algorithm submodules (41) when performing iterative operation, if the coefficient of the R (x) polynomial is larger than or equal to the coefficient of the Q (x) polynomial after the last iteration operation, the iteration is directly operated on the basis of the last iteration result, namely the iteration operation and the last iteration operation are combined, so that the total iteration operation time delay is reduced by half; the output of the data input for time division multiplexing processing of the respective 16-bit data, specifically syndrome calculation, is time division multiplexed and sent to the 8-bit improved Euclidean algorithm submodule (41).
2. The decoder according to claim 1, wherein the plurality of bytes is four bytes and the modified euclidean algorithm module (22) is two 8-bit modified euclidean algorithm sub-modules (41) for time-multiplexed processing of respective 16-bit data inputs by combining to halve respective iterations between the syndrome calculation module and the chien search module in parallel.
3. The decoder of claim 1, wherein the plurality of bytes is three bytes and the modified euclidean algorithm module (22) is two 8-bit modified euclidean algorithm sub-modules connected in parallel between the syndrome calculation module and the chien search module, at least one (41) of which is configured to implement time-division multiplexing by combining halved iterations, one implementing time-division multiplexing for processing 16-bit data inputs and the other implementing (41) or not (33) time-division multiplexing for processing the remaining 8-bit data inputs.
4. The decoder of claim 1, wherein said plurality of bytes is two bytes and said modified euclidean algorithm module (22) is an 8-bit modified euclidean algorithm sub-module (41) for time division multiplexing processing of 16-bit data inputs by combining halved iterations.
5. The decoder according to any of claims 1-4, wherein the 8-bit modified Euclidean algorithm sub-module (41 or 33) comprises a control unit, a polynomial calculation unit and a level estimation unit, wherein: the control unit and the polynomial calculation unit and the level estimation unit are electrically connected in two directions.
6. The decoder of claim 1, wherein the syndrome computation module is a syndrome computation module that employs a multi-byte parallel computation, the multi-byte being consistent with the bus input.
7. Decoder according to claim 2, characterized in that the syndrome computation module can be a 16-bit, 24-bit or 32-bit syndrome computation module (21).
8. The decoder according to claim 1, wherein the chien search module (23), the forney algorithm module (24) and the error correction output module (25) are formed by parallel connection of a plurality of 8-bit corresponding sub-modules for parallel processing in accordance with a plurality of bytes.
9. The decoder according to claim 1, characterized in that the decoder (12) is applied in a GPON network.
10. The decoder according to claim 1, characterized in that the decoder (12) is implemented by a field programmable gate array or an application specific integrated circuit.
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| CN112436842B (en) * | 2021-01-27 | 2021-05-14 | 睿迪纳(南京)电子科技有限公司 | Method for realizing signal processing device based on fractional folding |
| CN114095039B (en) * | 2021-10-18 | 2023-11-28 | 深圳市紫光同创电子有限公司 | Accompanying calculation method and calculation circuit supporting codeword synchronization |
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