CN100587508C - 实现高速测试电路的扫描链和方法 - Google Patents
实现高速测试电路的扫描链和方法 Download PDFInfo
- Publication number
- CN100587508C CN100587508C CN200710103241A CN200710103241A CN100587508C CN 100587508 C CN100587508 C CN 100587508C CN 200710103241 A CN200710103241 A CN 200710103241A CN 200710103241 A CN200710103241 A CN 200710103241A CN 100587508 C CN100587508 C CN 100587508C
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- Prior art keywords
- scan
- test
- scan register
- register
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- 238000012360 testing method Methods 0.000 title claims abstract description 149
- 238000000034 method Methods 0.000 title claims abstract description 12
- 230000007704 transition Effects 0.000 claims abstract description 21
- 230000004044 response Effects 0.000 claims abstract description 20
- 230000003111 delayed effect Effects 0.000 claims abstract description 15
- 230000037361 pathway Effects 0.000 claims description 23
- 230000007306 turnover Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 230000008676 import Effects 0.000 description 3
- 230000005284 excitation Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318552—Clock circuits details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/427,659 US20080005634A1 (en) | 2006-06-29 | 2006-06-29 | Scan chain circuitry that enables scan testing at functional clock speed |
US11/427,659 | 2006-06-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101097245A CN101097245A (zh) | 2008-01-02 |
CN100587508C true CN100587508C (zh) | 2010-02-03 |
Family
ID=38878330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200710103241A Expired - Fee Related CN100587508C (zh) | 2006-06-29 | 2007-05-10 | 实现高速测试电路的扫描链和方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20080005634A1 (zh) |
CN (1) | CN100587508C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI684774B (zh) * | 2018-12-05 | 2020-02-11 | 瑞昱半導體股份有限公司 | 應用於多個掃描模式來進行測試的電路 |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4977045B2 (ja) * | 2008-01-16 | 2012-07-18 | 株式会社東芝 | 半導体集積回路及び半導体装置 |
US7885129B2 (en) * | 2008-05-28 | 2011-02-08 | Macronix International Co., Ltd | Memory chip and method for operating the same |
EP2331979B1 (en) | 2008-09-26 | 2012-07-04 | Nxp B.V. | Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device |
CN102054078B (zh) * | 2009-10-30 | 2014-11-26 | 新思科技(上海)有限公司 | 物理设计中基于双向优先选择的扫描链重构方法与装置 |
CN102004218B (zh) * | 2010-09-10 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | 芯片可接受度测试方法 |
CN102323538B (zh) * | 2011-07-08 | 2013-09-11 | 哈尔滨工业大学 | 基于改进测试向量集的部分扫描的扫描单元的设计方法 |
US8704529B2 (en) * | 2011-10-04 | 2014-04-22 | Nanya Technology Corporation | Circuit test interface and test method thereof |
US9354274B2 (en) | 2012-08-13 | 2016-05-31 | Nanya Technology Corporation | Circuit test system electric element memory control chip under different test modes |
JP6268461B2 (ja) * | 2013-03-28 | 2018-01-31 | セイコーエプソン株式会社 | 半導体装置、物理量センサー、電子機器及び移動体 |
CN105102996B (zh) * | 2013-04-12 | 2018-01-02 | 爱德万测试公司 | 输入和输出路径的扫描速度优化 |
US9383411B2 (en) * | 2013-06-26 | 2016-07-05 | International Business Machines Corporation | Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers |
US9239360B2 (en) * | 2014-01-28 | 2016-01-19 | Texas Instruments Incorporated | DFT approach to enable faster scan chain diagnosis |
FR3023620B1 (fr) * | 2014-07-09 | 2016-07-29 | Stmicroelectronics (Grenoble 2) Sas | Procede de gestion du fonctionnement d'un mode test d'un composant logique avec restauration de l'etat precedant le test |
CN109239586A (zh) * | 2018-08-17 | 2019-01-18 | 国营芜湖机械厂 | 一种lattice 1032 cpld的检测方法 |
CN109298322A (zh) * | 2018-09-27 | 2019-02-01 | 西安微电子技术研究所 | 一种动态变链长扫描结构及其方法和边界扫描单元 |
US11156664B2 (en) * | 2018-10-31 | 2021-10-26 | SK Hynix Inc. | Scan chain techniques and method of using scan chain structure |
CN113542045B (zh) * | 2020-04-21 | 2023-01-24 | 北京威努特技术有限公司 | 一种tcp端口状态确定方法及装置 |
WO2022087829A1 (zh) * | 2020-10-27 | 2022-05-05 | 京东方科技集团股份有限公司 | 数据处理电路、数据处理方法及电子设备 |
CN112098818B (zh) * | 2020-11-02 | 2021-02-02 | 创意电子(南京)有限公司 | 一种基于标准边界扫描电路的sip器件测试*** |
CN112684327B (zh) * | 2020-11-30 | 2023-09-05 | 海光信息技术股份有限公司 | 扫描链及其设计方法和基于扫描链的串行扫描复位方法 |
CN112713886B (zh) * | 2020-12-02 | 2023-09-15 | 海光信息技术股份有限公司 | 用于扫描寄存器复位的装置和方法 |
WO2023272439A1 (zh) * | 2021-06-28 | 2023-01-05 | 华为技术有限公司 | 芯片和芯片测试装置 |
CN113709390B (zh) * | 2021-08-25 | 2022-06-10 | 豪威芯仑传感器(上海)有限公司 | 一种扫描器电路及图像传感器 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0429728B1 (en) * | 1989-11-30 | 1994-06-15 | International Business Machines Corporation | Logic circuit |
US5668492A (en) * | 1994-08-24 | 1997-09-16 | International Business Machines Corporation | Integrated circuit clocking technique and circuit therefor |
CN1211323A (zh) * | 1996-02-06 | 1999-03-17 | 三星电子株式会社 | 利用联合测试行动组织标准的i/o状态翻转测试方法 |
CN1320214A (zh) * | 1998-09-28 | 2001-10-31 | 因芬尼昂技术股份公司 | 具有可去活的扫描电路的电路装置 |
US6427217B1 (en) * | 1999-04-15 | 2002-07-30 | Agilent Technologies, Inc. | System and method for scan assisted self-test of integrated circuits |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5355369A (en) * | 1991-04-26 | 1994-10-11 | At&T Bell Laboratories | High-speed integrated circuit testing with JTAG |
US5615217A (en) * | 1994-12-01 | 1997-03-25 | International Business Machines Corporation | Boundary-scan bypass circuit for integrated circuit electronic component and circuit boards incorporating such circuits and components |
US6055658A (en) * | 1995-10-02 | 2000-04-25 | International Business Machines Corporation | Apparatus and method for testing high speed components using low speed test apparatus |
CA2219847C (en) * | 1996-11-20 | 2000-10-03 | Logicvision, Inc. | Method and apparatus for scan testing digital circuits |
US6327684B1 (en) * | 1999-05-11 | 2001-12-04 | Logicvision, Inc. | Method of testing at-speed circuits having asynchronous clocks and controller for use therewith |
US6567943B1 (en) * | 2000-04-07 | 2003-05-20 | International Business Machines Corporation | D flip-flop structure with flush path for high-speed boundary scan applications |
US6578168B1 (en) * | 2000-04-25 | 2003-06-10 | Sun Microsystems, Inc. | Method for operating a boundary scan cell design for high performance I/O cells |
US6658632B1 (en) * | 2000-06-15 | 2003-12-02 | Sun Microsystems, Inc. | Boundary scan cell architecture with complete set of operational modes for high performance integrated circuits |
US6614263B2 (en) * | 2002-02-05 | 2003-09-02 | Logicvision, Inc. | Method and circuitry for controlling clocks of embedded blocks during logic bist test mode |
US6862705B1 (en) * | 2002-08-21 | 2005-03-01 | Applied Micro Circuits Corporation | System and method for testing high pin count electronic devices using a test board with test channels |
US7155651B2 (en) * | 2004-04-22 | 2006-12-26 | Logicvision, Inc. | Clock controller for at-speed testing of scan circuits |
US7322000B2 (en) * | 2005-04-29 | 2008-01-22 | Freescale Semiconductor, Inc. | Methods and apparatus for extending semiconductor chip testing with boundary scan registers |
US7487419B2 (en) * | 2005-06-15 | 2009-02-03 | Nilanjan Mukherjee | Reduced-pin-count-testing architectures for applying test patterns |
-
2006
- 2006-06-29 US US11/427,659 patent/US20080005634A1/en not_active Abandoned
-
2007
- 2007-05-10 CN CN200710103241A patent/CN100587508C/zh not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0429728B1 (en) * | 1989-11-30 | 1994-06-15 | International Business Machines Corporation | Logic circuit |
US5668492A (en) * | 1994-08-24 | 1997-09-16 | International Business Machines Corporation | Integrated circuit clocking technique and circuit therefor |
CN1211323A (zh) * | 1996-02-06 | 1999-03-17 | 三星电子株式会社 | 利用联合测试行动组织标准的i/o状态翻转测试方法 |
CN1320214A (zh) * | 1998-09-28 | 2001-10-31 | 因芬尼昂技术股份公司 | 具有可去活的扫描电路的电路装置 |
US6427217B1 (en) * | 1999-04-15 | 2002-07-30 | Agilent Technologies, Inc. | System and method for scan assisted self-test of integrated circuits |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI684774B (zh) * | 2018-12-05 | 2020-02-11 | 瑞昱半導體股份有限公司 | 應用於多個掃描模式來進行測試的電路 |
Also Published As
Publication number | Publication date |
---|---|
US20080005634A1 (en) | 2008-01-03 |
CN101097245A (zh) | 2008-01-02 |
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Effective date of registration: 20171121 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171121 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
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