CN100586027C - MCU +DSP structural system digital multimedia coding-decoding method and corresponding system - Google Patents
MCU +DSP structural system digital multimedia coding-decoding method and corresponding system Download PDFInfo
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Abstract
The invention relates to a digital multimedia coding-decoding method used for an MCU plus DSP structure system. The MCU plus DSP structure system comprises an MCU including an OS, an MCU protocol analysis communication module; a memory used for memorizing arithmetic program files; a DSP including a DSP protocol communication module; an interface between the MCU and the DSP; and a communication protocol between the MCU and the DSP. The method includes that: flows are synchronously started and the cooperative flows are analyzed by protocol. The technical proposal of the invention mainly solves three problems: 1. the cooperation between the MCU and the DSP; 2. the completion of the start, the operation and the conversion of arithmetic by using a unified interface and a protocol frame; 3. the completion of arithmetic updating or new arithmetic development by using the unified interface and the protocol frame.
Description
Technical field
This patent relates to the digital multimedia coding-decoding application, especially, relates to digital multimedia coding-decoding method and corresponding system in a kind of MCU+DSP structural system.
Background technology
When the product of developing mp3 player product or having media play function, all can run into the bit rate how OS (operating system) obtains music file, sample rate, information and the broadcast of controlling music such as total reproduction time, suspend, functions such as F.F. realize, and the play operation of realization different-format file, and all want real-time finishing, when realizing the product of these functions, all use the IC of MCU+DSP framework to realize usually, and OS is placed among the MCU (micro-control unit) usually, and the computational process of these more complicated of function of decoding and complexity just needs DSP (digital signal processor) to finish, thus, produced the problem of cooperating between MCU and the DSP simultaneously and algorithm is realized and the problem of upgrading, how to allow OS finish these real-time functions, reach smooth playing, how to give full play to the collaborative operational capability of MCU and DSP, make problems such as cost reduction.
Digital media player such as mp3 player function are very many in the market, need the broadcast format of support also a lot, but also constantly increasing its function, similar products with medium codec functions are also very many, but not a cover in real time, simply fast expanded function, with irrelevant interface and the protocol frame implementation method of form, and ICP/IP protocol is arranged on network, DLL technology etc. is arranged in the operating system, and do not have a kind of method and system in this field, can be fast and the exploitation of correct complete realization medium encoding and decoding cooperation part.
In addition, technology in the past thinks that it can not play all medium with same agreement, but can adopt the mode of downloading each media protocol respectively, the system that finishes the medium of playing all supports realizes demand, be the corresponding a kind of agreements of each medium, play a kind of medium, will download a kind of agreement with regard to correspondence.For example play mp3, need in player, to have in advance the mp3 agreement, play mp4, need in player, to have in advance the mp4 agreement.Still solution has reached system or the method for playing multiple media formats with same agreement, if can solve non-unified problem, will significantly reduce attendant and each side cost.
Summary of the invention
This patent just produces under such background, the object of the present invention is to provide the digital multimedia coding-decoding method in a kind of MCU+DSP structural system, the real-time implementation that it can finish different-format and multiple function with unified interface and protocol frame has simultaneously and can expand and terseness.
Simultaneously, the present invention also provides corresponding M CU+DSP the multimedia play system of structure.
According to an aspect of the present invention, provide a kind of digital multimedia coding-decoding method in the MCU+DSP structural system, this MCU+DSP structural system comprises: the micro-control unit (MCU) that comprises operating system (OS); Digital signal processor (DSP); And the interface between MCU and the DSP, this method comprises: start flow process: MCU synchronously and allow OS by reading the indexing head structure that has particular index and institutional algorithm routine file, check the algorithm types of supporting synchronously, success synchronously then starts DSP and by algorithm routine file organization structure DSP is read and moved into to corresponding algorithm routine and data, the operation of beginning algorithm, synchronously unsuccessful, then report the upper strata and withdraw from; And protocol analysis collaboration process: after the algorithm operation, communications protocol according to MCU and DSP, DSP utilizes hardware definition interface and software definition interface to send signal and information, MCU utilizes and interrupts by interface acknowledge(ment) signal and information, after handling the work of corresponding signal definition, return to DSP corresponding signal and information, DSP is acknowledge(ment) signal and information again, after handling, algorithm continues down operation, begin new collaboration process to the specific definitions stage then, thereby realize various Codec (codec) function.
According to said method of the present invention, wherein the hardware interface between MCU and the DSP comprises: several register communication interfaces that have between MCU and the DSP, comprise a plurality of data-interfaces (idr) and a plurality of state interface (isr), wherein data-interface is used for transmitting signal between MCU and DSP, state interface indicates each data-interface and has been read or the state of writing, register communication interface between MCU and DSP is after being write, MCU can produce interruption, and the register communication interface all can be indicated in after reading and writing on the bit corresponding in the state interface automatically; And the control register interface (mcr) of DSP internal memory, make DSP internal processes space and data space can be switched and carry out read and write access to MCU.
According to said method of the present invention, several register communication interfaces that wherein have between MCU and the DSP are decided to be the interface of 8 8bit (bit), comprise 6 data interface (idr0, idr1, idr2, idr3, idr4, idr5) and 2 state interface (isr0, isr1).
According to said method of the present invention, the communications protocol of wherein said MCU and DSP, signal definition with a series of paired appearance (is sent signal, inverse signal), each signal is to there being the corresponding action of sign, signal is by grouping planning, accepts and transmits by the idr mouth, defines corresponding running flow process with this.
According to said method of the present invention, wherein the communications protocol of MCU and DSP comprises software interface and functional definition, makes to allow MCU get access to the key message data of DSP computing, returns to OS then and uses.
According to said method of the present invention, wherein the communications protocol of MCU and DSP comprises software interface and functional definition, makes MCU write incoming interface to information, allows DSP get access to the information data that OS need transmit.
According to said method of the present invention, wherein the algorithm routine file is the binary data file (DSP BIN file) that all algorithm routines and data are formed, it by certain textural association together, contain one or more algorithms, have index structure and particular organization's standard, have synchronous index, allocation index and data three big block structures on the structure, can expand as required.
According to said method of the present invention, wherein said index structure and particular organization's normalized definition are as follows:
*.dsp={CodecIndexStruct, Codec_AddressStruct[N], Codec_Data[N], N=support the decoding number of types, promptly have synchronous index, allocation index and data three big block structures
CodecIndexStruct={version, N, IndexStruct[N], IndexStruct={CodecTypeID, CodecName, CodecStartAddress, otherinfo}, CodecStartAddress=Codec_AddressStruct[k] initial address, k algorithm types of k=
Codec_AddressStruct={infomation, banknum, bankStruct[banknum] }, bankStruct={index, setparameter, data_source_address, data_source_length, data_destination_address}, data_source_address=Codec_Data[k] in the address of corresponding index (call number), k algorithm routine of k=or data block
Codec_Data[k]=binary data blocks that a k algorithm routine or data are formed.
According to said method of the present invention, the feature of wherein said index structure is, the DSP file header has the synchronous index of each algorithm, and ensuing address block has algorithm each several part program and data address index, next is the file index structure of each piece program or data.
According to a further aspect in the invention, a kind of multimedia play system of MCU+DSP structure is provided, comprises: micro-control unit (MCU), in operating system (OS) is arranged, contain MCU program and MCU protocol analysis communication module, the processing of communications protocol rule is arranged in the MCU protocol analysis communication module; Memory stores the algorithm routine file, and this algorithm routine file has particular index and organization; Digital signal processor (DSP) is started DSP and by algorithm routine file organization structure DSP is read and moved into to corresponding algorithm routine and data by MCU when successful when synchronous, the operation of beginning algorithm; Algorithm routine contains software function interface, DSP protocol communication module, and the processing of communications protocol rule is arranged in the DSP protocol communication module; And the hardware interface between MCU and the DSP; Wherein, communications protocol according to MCU and DSP, DSP utilizes hardware definition interface and software definition interface to send signal and information, and MCU utilizes and interrupts by interface acknowledge(ment) signal and information, handle the work of corresponding signal definition after, return to DSP corresponding signal and information, DSP is acknowledge(ment) signal and information again, and after handling, algorithm continues down operation, begin new collaboration process to the specific definitions stage then, thereby realize various Codec (codec) function.
According to said system of the present invention, wherein the hardware interface between MCU and the DSP comprises: several register communication interfaces that have between MCU and the DSP, comprise a plurality of data-interfaces (idr) and a plurality of state interface (isr), wherein data-interface is used for transmitting signal between MCU and DSP, state interface indicates each data-interface and has been read or the state of writing, register communication interface between MCU and DSP is after being write, MCU can produce interruption, and the register communication interface all can be indicated in after reading and writing on the bit position corresponding in the state interface automatically; And the control register interface (mcr) of DSP internal memory, make DSP internal processes space and data space can be switched and carry out read and write access to MCU.
According to said system of the present invention, several register communication interfaces that wherein have between MCU and the DSP are decided to be the interface of 8 8bit, comprise 6 data interfaces (idr0, idr1, idr2, idr3, idr4, idr5) and 2 state interface (isr0, isr1).
According to said system of the present invention, the communications protocol of wherein said MCU and DSP, signal definition with a series of paired appearance (is sent signal, inverse signal), each signal is to there being the corresponding action of sign, signal is by grouping planning, accepts and transmits by the idr mouth, defines corresponding running flow process with this.
According to said system of the present invention, wherein the communications protocol of MCU and DSP comprises software interface and functional definition, makes to allow MCU get access to the key message data of DSP computing, returns to OS then and uses.
According to said system of the present invention, wherein the communications protocol of MCU and DSP comprises software interface and functional definition, makes MCU write incoming interface to information, allows DSP get access to the information data that OS need transmit.
According to said system of the present invention, wherein the algorithm routine file is the binary data file (DSP BIN file) that all algorithm routines and data are formed, it by certain textural association together, contain one or more algorithms, have index structure and particular organization's standard, have synchronous index, allocation index and data three big block structures on the structure, can expand as required.
According to said system of the present invention, wherein said index structure and particular organization's normalized definition are as follows:
*.dsp={CodecIndexStruct, Codec_AddressStruct[N], Codec_Data[N], N=support the decoding number of types, promptly have synchronous index, allocation index and data three big block structures
CodecIndexStruct={version, N, IndexStruct[N], IndexStruct={CodecTypeID, CodecName, CodecStartAddress, otherinfo}, CodecStartAddress=Codec_AddressStruct[k] initial address, k algorithm types of k=
Codec_AddressStruct={infomation, banknum, bankStruct[banknum] }, bankStruct={index, setparameter, data_source_address, data_source_length, data_destination_address}, data_source_address=Codec_Data[k] in the address of corresponding index (call number), k algorithm routine of k=or data block
Codec_Data[k]=binary data blocks that a k algorithm routine or data are formed.
According to said system of the present invention, the feature of wherein said index structure is, the DSP file header has the synchronous index of each algorithm, and ensuing address block has algorithm each several part program and data address index, next is the file index structure of each piece program or data.
In technical scheme of the present invention, in MCU+DSP structure multimedia application IC, bring into play the collaboration capabilities between MCU and DSP greatly, interface between software and hardware between MCU and DSP is fixed up, the DSP BIN file that has new digital media encoding/decoding algorithm only to need the user to regenerate the new algorithm program later on gets final product, need not change MCU CODEC part again, with other interface section, unless new interface protocol is arranged.It has been equivalent to build the standard of the hardware and software between a MCU and DSP, and simple and fast, modularization and standard that the increase of media algorithm is become make the cooperation of each arithmetic element (CPU) obtain that speed promotes and smooth clear.
Technical scheme of the present invention has solved the problem of three aspects at least:
1.MCU with the problem of cooperating between the DSP;
2. finish startup, operation and the transformation problem of various algorithms with unified interface and protocol frame
3. finishing the renewal of algorithm or new algorithm with unified interface and protocol frame expands the solution of problem problem 1 MCU and DSP are moved fast, raise the efficiency, problem 2 and 3 solution can reduce attendant and cost, make things convenient for the client to upgrade fast simultaneously or expand new algorithm.The present invention finishes the real-time implementation of different-format and multiple function with unified interface and protocol frame, and complete realization the cooperation of a whole set of mechanism.
Superior technique effect of the present invention can be summarized as:
A: succinct real-time, promptly simple in structure, realize simple and easyly, and real-time response is moved.
B: complete extensibility, can satisfy the demand of present multi-functional multi-format, and constantly simple and fast expansion.
C: the form uniformity that has nothing to do, can support all to present media compression formats that promptly as long as increase related definition, all unify with this kind protocol specification, software and hardware need not change.
Its operational capability is given full play in the quick and smooth cooperation of each CPU element of D: collaborative: MCU and DSP.
In a word, this patent can greatly be brought into play the collaboration capabilities between MCU and DSP, and the interface between software and hardware of MCU and DSP will be fixed, and realizes simple and easyly, and irrelevant with the media algorithm form, algorithm function is fast expanded.
The term that present specification is used is as follows:
Mp3: a kind of music compression file meets mpeg 1 layer 3 standards
MCU:micro control unit, micro-control unit
DSP:digital signal processor, digital signal processor
Bin:binary, binary
IC:integrate circuit chip, integrated circuit (IC) chip
TCP/IP: be used for one group of communications protocol of network, comprise IP (Internet Protocol) and TCP (Transmission Control Protocol, transmission control protocol)
DLL:danamic link library, dynamic link library
OS:operation system, operating system
Ext: the part of file suffixes
DAC:digital to analog change, digital to analog converter
Fs:frequency of sample, sample rate
Codec:software that is used to compress or decompress a digitalmedia file codec
DSP BIN file: DSP binary data file
CPU: arithmetic element
Memory: internal memory
The Bit:(binary system) position, bit
Index: call number
ROM: read-only memory
Ms: millisecond
Yes: be; No: not
Idr: the data register interface, the numeral of back band is its sequence number
Isr: the status register interface, the numeral of back band is its sequence number
Mcr: the control register interface of internal memory
Description of drawings
Fig. 1: interface and protocol frame figure according to an embodiment of the invention: the layout and the relation that have disclosed whole agreement each several part on the whole;
Fig. 2: the synchronous startup flow chart of having described one embodiment of the invention: OS starts synchronously by the algorithm of agreement with needs;
Fig. 3: the concise and to the point protocol analysis flow chart of MCU of having described one embodiment of the invention: the flow process of crucial several agreement runnings, accept and transmit signal by the idr5 mouth.
Embodiment
For making those skilled in the art can understand the present invention, below an implementation of the present invention is described with a specific embodiment.Should be appreciated that specific embodiment can not limit all technical schemes of the present invention.
Patent of the present invention relates to the digital multimedia coding-decoding application, especially, relates to digital multimedia coding-decoding method and corresponding system in a kind of MCU+DSP structural system.A specific embodiment of the relation between the interface of the integral body of MCU+DSP structural system of the present invention and protocol frame and each several part is seen Fig. 1.
Fig. 1 is interface and protocol frame figure according to an embodiment of the invention: the layout and the relation that have disclosed whole agreement each several part on the whole.As can be seen from the figure, structural relation is that MCU and DSP can carry out communication and transfer of data by the hardware interface between them, MCU can carry out transfer of data with Memory, store the algorithm routine file in the Memory, OS is arranged in operation in the MCU, OS contains MCU program and MCU protocol analysis communication module, the processing of the communications protocol rule of definition is arranged in the MCU protocol analysis communication module, and algorithm routine and data that DSP has MCU to move into are being moved, algorithm routine contains the software function interface, DSP agreement communication module and other algorithm routines and data, the processing of the communications protocol rule of definition is arranged, the agreement flow processing that DSP agreement communication module and MCU protocol analysis communication module define by hardware interface in the DSP agreement communication module.
For realizing purpose of the present invention, the invention provides a kind of in MCU+DSP structure multimedia application IC the digital media interface collaboration protocols, be called for short the Digital Media collaboration protocols, be Digital Media Collaboration Protocol (DMCP), this agreement will make the interface between software and hardware between MCU and DSP be fixed up, the file (DSP BIN file) that has new digital media encoding/decoding algorithm only to need the user to regenerate the new algorithm program later on gets final product, need not change MCU CODEC part again, with other interface section, unless new interface protocol is arranged.It has been equivalent to build the standard of the hardware and software between a MCU and DSP, and simple and fast, modularization and standard that the increase of media algorithm is become make the cooperation of each arithmetic element (CPU) obtain that speed promotes and smooth clear.Say that briefly this technical scheme comprises 5 parts:
(a). collaboration process
(b). hardware interface
(c) communications protocol of .MCU and DSP
(d). the algorithm routine file structure
(e). software interface and functional definition
Below described respectively at specific embodiment.
1. collaboration process
(1) start flow process synchronously, as shown in Figure 2: MCU allow OS by read the algorithm routine file (
*.dsp) indexing head structure is checked the algorithm types of supporting synchronously, and success synchronously then starts DSP and by the institutional framework of algorithm routine file DSP is read and moved into to corresponding algorithm routine and data, and the operation of beginning algorithm is unsuccessful then report the upper strata and withdraw from.
(2) protocol analysis collaboration process: after the operation of beginning algorithm, according to the MCU of definition and the communications protocol of DSP, DSP utilizes the hardware and software defining interface to send signal and information, MCU utilizes and interrupts by interface acknowledge(ment) signal and information, after handling the work of corresponding signal definition, return to DSP corresponding signal and information, DSP is acknowledge(ment) signal and information again, and after handling, algorithm continues down operation, begin new collaboration process to the specific definitions stage then, constantly like this realize various Codec functions repeatedly together, and reach smooth running, all utilize the idr mouth to carry out the signal transmission, utilize mcr and memory read-write method to carry out mobile data, MCU partly sees Fig. 3.
Fig. 3: the concise and to the point protocol analysis flow chart of MCU of having described one embodiment of the invention: as seen from the figure, after the operation of beginning algorithm, DSP writes the 0x11 signal to the idr5 mouth, MCU interrupts producing and entering the protocol analysis interrupt routine, inquiry idr5 mouth, signal value is compared one by one, retrieving is the 0x11 signal, then handle respective action (promptly 1. read bit stream initial address 2. backup breakpoints recover addresses 3. decoding parametric is set), after finishing, need judging whether breakpoint to recover, is then to recover breakpoint information to DSP, not then to skip this step, then write the 0x22 signal to the idr5 mouth at last and return to DSP and withdraw from, a protocol processes is finished, and algorithm continues down operation, begin new collaboration process (as 0x12 to the specific definitions stage then, 0x72,0x91, the processing of other agreement such as 0x94), constantly like this realize various Codec functions repeatedly together, and reach smooth running.
The similar MCU of DSP part utilizes the idr5 mouth to carry out the signal transmission among the figure, utilize mcr and memory read-write method to carry out mobile data.
(3) flow scheme design: the communications protocol by definition MCU and DSP different, and software interface and functional definition is different, but flexible design or improve concrete individual function collaboration process.
2. hardware interface
According to a specific embodiment of the present invention, in hardware system, increase as lower interface:
The register communication interface that has several between MCU and DSP is decided by protocol contents, comprises a plurality of data-interfaces and state interface.Usually can decide the interface of 4 or 8 8bit, that is, and 1 state interface of 3 data interfaces, or 2 state interface of 6 data interfaces, define by 8 below and illustrate, data-interface idr is used for transmitting signal and (is designated as idr0, idr1 between MCU and DSP, idr2, idr3, idr4, idr5), state interface isr indicates each data-interface and has been read or the state of writing (is designated as isr0, isr1).
Register communication interface (idr0-5) between MCU and DSP is after being write, and MCU can produce interruption, and idr0-5 can be indicated in after reading and writing on the bit position corresponding in isr0 or the isr1 automatically
DSP internal processes space and data space can be switched to MCU and carry out read and write access, and the control register interface mcr of a DSP internal memory is arranged simultaneously.
3.MCU communications protocol with DSP
Below be decoded as example with Digital Media and describe this communications protocol.Table 1 is an example of communications protocol definition for this reason.
Table 1
Illustrate: send signal=0x11 as DSP initial set-up procedure: DS, MCU inverse signal=0x21, after expression DSP started synchronously, initialization finished the DSP parameter, and DSP will write 0x11 to idr5, request MCU is provided with decoding parametric, MCU interrupts producing, and inquiry idr5 also receives 0x11, then carries out the action of expression, return after finishing and write 0x21 to idr5, this process finishes.The rest may be inferred by analogy for it.Those skilled in the art are appreciated that fully that by this table table 1 is decoded as example with Digital Media and has provided communications protocol definition between MCU and DSP.
In more detail, communication can be operated by the communication interface between MCU and DSP (idr0-5), and by isr0, isr1 inquires about its state, needs read-write DSP data to control its switching state by mcr, operates then
The Idr5=0xXX explanation: numerical value 0xXX is the signal definition value
4. algorithm routine file
In an embodiment of the present invention, the algorithm routine file be called DSP BIN file (
*.dsp), it is the binary data file that all algorithm routines and data are formed, and together by certain textural association, its characteristics have index structure and particular organization's standard exactly, have synchronous index, allocation index and data three big block structures on the structure, the expansion of can controlling oneself as required of other information that need, the purpose of this file be allow the algorithm types of OS support synchronously and with corresponding program and data when algorithm starts or the DSP of moving in service.
Wherein said index structure and particular organization's normalized definition are as follows:
*.dsp={CodecIndexStruct, Codec_AddressStruct[N], Codec_Data[N], N=support the decoding number of types, promptly have synchronous index, allocation index and data three big block structures
CodecIndexStruct={version, N, IndexStruct[N], IndexStruct={CodecTypeID, CodecName, CodecStartAddress, otherinfo}, CodecStartAddress=Codec_AddressStruct[k] initial address, k algorithm types of k=
Codec_AddressStruct={infomation, banknum, bankStruct[banknum] }, bankStruct={index, setparameter, data_source_address, data_source_length, data_destination_address}, data_source_address=Codec_Data[k] in the address of corresponding index (call number), k algorithm routine of k=or data block
Codec_Data[k]=binary data blocks that a k algorithm routine or data are formed.
The feature of wherein said index structure is, the DSP file header has the synchronous index of each algorithm, and ensuing address block has algorithm each several part program and data address index, next is the file index structure of each piece program or data.
5. software interface and functional definition
Software interface and functional definition can allow MCU get access to some key message data (information of following table definition) of DSP computing, return to OS then and use, and perhaps MCU writes incoming interface to information, allows DSP get access to the information data that OS need transmit.
For example, following is a kind of software interface of DSP internal data internal memory and the example of functional definition: (this is decoded as example with Digital Media)
From the description of the above embodiment that is decoded as example at Digital Media as can be seen, technical scheme of the present invention has solved the problem of cooperating between MCU and the DSP, and finish the real-time implementation of different-format and multiple function with unified interface and protocol frame, have simultaneously and can expand and terseness, and complete realization the cooperation of a whole set of mechanism.
The present invention allows various corrections and optional form, and the graphic specific embodiment of accompanying drawing here just is described in detail as an example.It should be understood that to illustrate that here specific embodiment is not to limit the invention to disclosed concrete form that the present invention should comprise interior all modifications, equivalent and the possibility of the spirit and scope of the present invention that claims limit.
Claims (18)
1. digital multimedia coding-decoding method in the MCU+DSP structural system, this MCU+DSP structural system comprises: the micro-control unit (MCU) that comprises operating system (OS); The memory that comprises the algorithm routine file; Digital signal processor (DSP); Interface between MCU and the DSP; The communications protocol of MCU and DSP,
This method comprises:
Start flow process: MCU synchronously and allow OS by reading the indexing head structure of algorithm routine file, check the algorithm types of supporting synchronously, described algorithm routine file has particular index and organization;
Success synchronously then starts DSP and by algorithm routine file organization structure DSP is read and moved into to corresponding algorithm routine and data, and the operation of beginning algorithm is unsuccessful synchronously, then reports the upper strata and withdraws from; And
Protocol analysis collaboration process: after the algorithm operation, communications protocol according to MCU and DSP, DSP utilizes hardware definition interface and software definition interface to send signal and information, and MCU utilizes and interrupts by interface acknowledge(ment) signal and information, handle the work of corresponding signal definition after, return to DSP corresponding signal and information, DSP is acknowledge(ment) signal and information again, and after handling, algorithm continues down operation, begin new collaboration process to the specific definitions stage then, thereby realize various Codec functions.
2. according to the process of claim 1 wherein that the hardware interface between MCU and the DSP comprises:
Several register communication interfaces that have between MCU and the DSP, comprise a plurality of data-interface idr and a plurality of state interface isr, wherein data-interface is used for transmitting signal between MCU and DSP, state interface indicates each data-interface and has been read or the state of writing, register communication interface between MCU and DSP is after being write, MCU can produce interruption, and the register communication interface all can be indicated in after reading and writing on the bit position corresponding in the state interface automatically; And
The control register interface mcr of DSP internal memory makes DSP internal processes space and data space can be switched to MCU and carries out read and write access.
3. according to the method for claim 2, the register communication interface that wherein has between MCU and the DSP is the interface of 8 8bit, comprises 6 data interfaces, is respectively idr0, idr1, and idr2, idr3, idr4, idr5 and 2 state interface are respectively isr0, isr1.
4. according to the method for claim 1, the communications protocol of wherein said MCU and DSP, signal definition with a series of paired appearance, the signal of described paired appearance comprises sends signal and inverse signal, each signal is to there being the corresponding action of sign, signal is by grouping planning, accepts and transmits by the idr mouth, defines corresponding running flow process with this.
5. according to the method for claim 4, wherein the communications protocol of MCU and DSP comprises software interface and functional definition, makes to allow MCU get access to the key message data of DSP computing, returns to OS then and uses.
6. according to the method for claim 4, wherein the communications protocol of MCU and DSP comprises software interface and functional definition, makes MCU write incoming interface to information, allows DSP get access to the information data that OS need transmit.
7. according to the method for claim 1, wherein the algorithm routine file is the binary data file that all algorithm routines and data are formed, it by certain textural association together, contain one or more algorithms, have index structure and particular organization's standard, have synchronous index, allocation index and data three big block structures on the structure, can expand as required.
8. according to the method for claim 7, wherein said index structure and particular organization's normalized definition are as follows:
*.dsp={CodecIndexStruct, Codec_AddressStruct[N], Codec_Data[N], the decoding number of types that N=supports promptly has synchronous index, allocation index and data three big block structures
CodecIndexStruct={version, N, IndexStruct[N], IndexStruct={CodecTypeID, CodecName, CodecStartAddress, otherinfo}, CodecStartAddress=Codec_AddressStruct[k] initial address, k algorithm types of k=
Codec_AddressStruct={infomation, banknum, bankStruct[banknum] }, bankStruct={index, setparameter, data_source_address, data_source_length, data destination_address}, data_source_address=Codec_Data[k] in the address of corresponding index, k algorithm routine of k=or data block
Codec_Data[k]=binary data blocks that a k algorithm routine or data are formed.
9. method according to Claim 8, the feature of wherein said index structure be, the DSP file header has the synchronous index of each algorithm, and ensuing address block has algorithm each several part program and data address index, next is the file index structure of each piece program or data.
10. the multimedia play system of a MCU+DSP structure comprises:
Micro-control unit (MCU), in operating system (OS) is arranged, contain MCU program and MCU protocol analysis communication module, the processing of communications protocol rule is arranged in the MCU protocol analysis communication module;
Memory stores the algorithm routine file, and this algorithm routine file has particular index and organization;
Digital signal processor (DSP) is started DSP and by algorithm routine file organization structure DSP is read and moved into to corresponding algorithm routine and data by MCU when successful when synchronous, the operation of beginning algorithm; Algorithm routine contains software function interface, DSP protocol communication module, and the processing of communications protocol rule is arranged in the DSP protocol communication module; With
Hardware interface between MCU and the DSP;
The communications protocol of MCU and DSP, DSP utilizes hardware definition interface and software definition interface to send signal and information, MCU utilizes and interrupts by interface acknowledge(ment) signal and information, after handling the work of corresponding signal definition, return to DSP corresponding signal and information, DSP is acknowledge(ment) signal and information again, after handling, algorithm continues down operation, begins new collaboration process to the specific definitions stage then, thereby realizes various Codec functions.
11. according to the system of claim 10, wherein the hardware interface between MCU and the DSP comprises:
Several register communication interfaces that have between MCU and the DSP, comprise a plurality of data-interface idr and a plurality of state interface isr, wherein data-interface is used for transmitting signal between MCU and DSP, state interface indicates each data-interface and has been read or the state of writing, register communication interface between MCU and DSP is after being write, MCU can produce interruption, and the register communication interface all can be indicated in after reading and writing on the bit position corresponding in the state interface automatically; And
The control register interface mcr of DSP internal memory makes DSP internal processes space and data space can be switched to MCU and carries out read and write access.
12. according to the system of claim 11, several register communication interfaces that wherein have between MCU and the DSP are decided to be the interface of 8 8bit, comprise 6 data interfaces, are respectively idr0, idr1, idr2, idr3, idr4, idr5 and 2 state interface are respectively isr0, isr1.
13. system according to claim 10, the communications protocol of wherein said MCU and DSP, signal definition with a series of paired appearance, the signal of described paired appearance comprises sends signal and inverse signal, each signal is to there being the corresponding action of sign, signal is by grouping planning, accepts and transmits by the idr data-interface, defines corresponding running flow process with this.
14. according to the system of claim 13, wherein the communications protocol of MCU and DSP comprises software interface and functional definition, makes to allow MCU get access to the key message data of DSP computing, returns to OS then and uses.
15. according to the system of claim 13, wherein the communications protocol of MCU and DSP comprises software interface and functional definition, makes MCU write incoming interface to information, allows DSP get access to the information data that OS need transmit.
16. system according to claim 10, wherein the algorithm routine file is the binary data file that all algorithm routines and data are formed, it by certain textural association together, contain one or more algorithms, have index structure and particular organization's standard, have synchronous index, allocation index and data three big block structures on the structure, can expand as required.
17. according to the system of claim 16, wherein said index structure and particular organization's normalized definition are as follows:
*.dsp={CodecIndexStruct, Codec_AddressStruct[N], Codec_Data[N], the decoding number of types that N=supports promptly has synchronous index, allocation index and data three big block structures
CodecIndexStruct={version, N, IndexStruct[N], IndexStruct={CodecTypeID, CodecName, CodecStartAddress, otherinfo}, CodecStartAddress=Codec_AddressStruct[k] initial address, k algorithm types of k=
Codec_AddressStruct={infomation, banknum, bankStruct[banknum] }, bankStruct={index, setparameter, data_source_address, data_source_length, data_destination_address}, data_source_address=Codec_Data[k] in the address of corresponding index, k algorithm routine of k=or data block
Codec_Data[k]=binary data blocks that a k algorithm routine or data are formed.
18. system according to claim 17, the feature of wherein said index structure is, the DSP file header has the synchronous index of each algorithm, and ensuing address block has algorithm each several part program and data address index, next is the file index structure of each piece program or data.
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| CN105988773B (en) * | 2015-02-10 | 2021-03-09 | 恩智浦美国有限公司 | Hardware interface assembly and method for hardware interface assembly |
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