CN100578981C - The method that system clock and frame pulse change in the employing async framing pulse solution optical-fiber network - Google Patents

Abstract

A kind of employing async framing pulse (FP) solves the method that system clock in Synchronous Digital Hierarchy (SDH) optical-fiber network and FP change, wherein single-deck is decided system FP signal and system's multi-frame pulse (MFP) signal of frame signal from clock Cross Trade receiving system clock and as system, and obtains the single-deck clock by system clock; Utilize this single-deck clock to come detection system to decide the high level of frame signal, and utilize system to decide frame signal in single-deck, to produce single-deck and decide frame signal (LOCAL_FP); Judge whether single-deck is decided frame signal is high level, when being judged as high level, begin the SDH data of single-deck are write in the first memory of single-deck, the data in the second memory of single-deck are taken out be sent to the SDH chip simultaneously; Judge whether system decides frame signal is high level, when being judged as high level, begin data temporary in the first memory of single-deck are taken out, and data are sent to the clock Cross Trade, be written in the second memory of single-deck for the data of single-deck the clock Cross Trade simultaneously.

Description

The method that system clock and frame pulse change in the employing async framing pulse solution optical-fiber network

Technical field

The invention belongs to optical communication field, relate in particular to a kind ofly in Synchronous Digital Hierarchy (SDH) optical network system, adopt async framing pulse (FP) to solve the method that system clock or FP change or shake.

Background technology

In the SDH optical network system, general all is the multi-frame pulse (MFP) that a FP and the 2K of the clock of an overall situation, a 8K are provided by the clock Cross Trade, wherein, FP signal and MFP signal all conduct are decided frame signal, and other each single-deck all adopts these several overall signals to reach the synchronous of the whole network.

For the clock Cross Trade,, and exchange because will handle from the data of each branch road with the group road.At this moment, if in order to reach the time slot requirement, he adapts to respectively the signal of each groove position,, its workload can be very big so, and be easy to make mistakes.So general mode of concentrating exchange that adopts of clock Cross Trade.So just requiring each following single-deck to be sent to the SDH signal of clock Cross Trade all must be consistent with the desired signal phase of clock Cross Trade, otherwise, the clock Cross Trade will can not find frame head, can't handle these data or may transmit the data of a mistake.For this reason, just require under the clock Cross Trade band each single-deck signal must Cross Trade be maintained fixed with clock all the time.

At present, high speed processing is all adopted in the inside of a lot of chips, and 622Mbps is more common transfer rate.This to the clock that offers chip or the requirement of deciding frame signal just than higher.If clock or decide frame signal and change or shake, the FIFO of chip internal and decide frame etc. and all can make a mistake so, thus cause service disconnection.Concerning clock, can be introduced into the chock smotthing module of this dish, thereby suppress the shake and the variation of clock.But for deciding frame signal, it is unactual to introduce the chock smotthing module.General way all is that chip is resetted now, allows it recover professional again.Here just long problem of a service outage duration appears.To producing some problems at random in the process of a chip reset, sometimes the problem of Chan Shenging might have influence on other chip, and other problem occurs in addition.

In addition, also needing to consider the problem of Virtual Concatenation, is example with the Ethernet.There are mismatch problem in the hard speed of SDH and the access rate of Ethernet data business.For instance, if the 100M Ethernet inserts the SDH network, we must dispose the circuit of 155Mbps to him, and so nearly 33% bandwidth resources have just slatterned, and in fact, potential waste may reach 67%.In order to solve this bandwidth waste, G.707/Y.1322 the ITU-T that the 15th group (being responsible for the research unit of transmission relevant criterion) of ITU-T published in October, 2000 formally describes in detail and has stipulated virtual container (VC) concatenation technology.The VC concatenation technology is to transmit employed for those net loads that can not meet SDH virtual container standard well.ITU-T has defined two kinds of Cascading Methods: continuous (adjacent) cascade and Virtual Concatenation.Ethernet inserts the Virtual Concatenation technology that generally all adopts now.The Virtual Concatenation technology can will be distributed in the method for the VC-n (same route with different routes all can) of different synchronous transfer mode STM-N according to cascade, forming a virtual macrostructure (VC-n-Xv) transmits, wherein each VC-n all has independent structures and corresponding path overhead (POH), has complete VC-n structure.Several VC-n Virtual Concatenations just are equivalent to interleaving of a plurality of VC-n.Each VC-n can carry out independent transmission, selects different paths, and middle transmission equipment is not had specific demand, just recombinates in terminal.Because different propagation velocitys, independently VC-n may produce time-delay.Different time-delays must compensate, and for the net load integral body of Virtual Concatenation, each virtual container must be recombinated.Reorganization must can overcome the time-delay of 125us at least.Tackle the time-delay (being 256ms to the maximum) of 125us in the Virtual Concatenation by the multi-frame structure of introducing a two-layer 512ms.For the virtual container in the virtual cascade group of recombinating, must know the independent sequence number of delay compensation and each VC-n.

In sum as can be seen, at first, must keep the phase relation of single-deck and clock Cross Trade constant, could keep professional stablizing; After the clock Cross Trade is switched, can cause SDH chip (EOS chip, 2M mapping chip etc., chip is shone upon in SDH encapsulation the chip of this common name except that the clock Cross Trade in) fifo error of inside and decide the frame mistake, the physical link of single-deck and clock Cross Trade interrupts, cause the SDH step-out, professional obstructed.After the complete step-out of SDH, mechanism according to SDH at first will pick up frame head synchronously within several frames, this needs certain hour synchronously, also will find the independent sequence number of each VC-n after the SDH frame synchronization owing to Virtual Concatenation, this time of service interruption that further extended again.If adopt the time of the method for the chip that resets with regard to the OOF that extended more.

Summary of the invention

The objective of the invention is in the SDH optical network system, adopt async framing pulse (FP) to solve system clock or FP and change or shake, thereby can keep the single-deck steady operation, reduce service damage, improve professional stability simultaneously, shorten service outage duration to a great extent.

A kind of employing async framing pulse (FP) solves the method that system clock in Synchronous Digital Hierarchy (SDH) optical-fiber network and FP change, wherein single-deck is decided system FP signal and system's multi-frame pulse (MFP) signal of frame signal from clock Cross Trade receiving system clock and as system, and obtains the single-deck clock by system clock; Utilize this single-deck clock to come detection system to decide the high level of frame signal, and utilize system to decide frame signal in single-deck, to produce single-deck and decide frame signal (LOCAL_FP); Judge whether single-deck is decided frame signal is high level, when being judged as high level, begin the SDH data of single-deck are write in the first memory of single-deck, the data in the second memory of single-deck are taken out be sent to the SDH chip simultaneously; Judge whether system decides frame signal is high level, when being judged as high level, begin data temporary in the first memory of single-deck are taken out, and data are sent to the clock Cross Trade, be written in the second memory of single-deck for the data of single-deck the clock Cross Trade simultaneously.

According to another aspect of the present invention, provide a kind of single-deck of using said method, comprising: the chock smotthing module is used for from clock Cross Trade receiving system clock, and produces new single-deck clock; And field programmable device (FPGA), be used to produce constant single-deck and decide frame signal, and provide temporary from the data of SDH chip or clock swapdisk, FGPA further comprises: decide the frame signal generation module, be used for deciding frame signal according to system, the single-deck clock that the chock smotthing module is produced carries out frequency division, produces that to decide the frame signal cycle identical with system, and the single-deck that phase place is different is decided frame signal; Memory, be used for temporary from the SDH chip data-signal or come the data-signal of self-clock Cross Trade; And counter, be used for producing memory data read address or write address.

By the present invention, after system clock and FP variation, the physical link of single-deck and clock Cross Trade only has only the interruption of a frame.Can keep the physical link of single-deck and clock Cross Trade, not interrupt as far as possible, even and occur to interrupt, also can be dropped to its break period minimum, thereby shorten step-out to the synchronous again time, reach the purpose that shortens service outage duration.

Description of drawings

When Fig. 1 is direct application system FP, the schematic diagram of the time requirement of clock Cross Trade;

Fig. 2 is the schematic diagram that concerns of some time etching system FP and LOCA_LFP;

Fig. 3 is by the schematic diagram of RAM after adaptive with the SDH data;

Fig. 4 be the FP of clock Cross Trade change back SDH data by RAM the schematic diagram after adaptive;

Fig. 5 is the calcspar according to single-deck structure of the present invention;

Fig. 6 is the flow chart of the inventive method RAM part;

Fig. 7 illustrates the service outage duration of the method that adopts chip reset;

Fig. 8 distributes 1 VC12 software to switch the service outage duration of clock Cross Trade after illustrating and adopting the present invention;

Fig. 9 distributes 1 VC12 hardware to switch the service outage duration of clock Cross Trade after illustrating and adopting the present invention;

Figure 10 distributes 63 VC12 softwares to switch the service outage duration of clock Cross Trade after illustrating and adopting the present invention;

Figure 11 distributes 63 VC12 hardware to switch the service outage duration of clock Cross Trade after illustrating and adopting the present invention.

Embodiment

In Fig. 5, show calcspar according to single-deck structure of the present invention.Comprising chock smotthing module and field programmable device (FPGA).

Constant in order to allow single-deck keep, just need the clock in the single-deck and decide frame signal FP to remain unchanged.Here the clock of system is introduced the chock smotthing module, will offer whole single-deck by the clock that the chock smotthing module provides again, the purpose that the clock that reaches single-deck does not thus change with the variation of clock Cross Trade.The constant frame signal of deciding is then produced by FPGA.When just powering on, in FPGA, adopt the clock that provides by the chock smotthing module to come the FP of detection system and the high level of MFP, be benchmark wherein with the FP of system and first high level of MFP, produce again and decide frame signal.After this, this produces again decides frame signal free oscillation always, remains unchanged, and is not subjected to the influence of FP of system and MFP.So, no matter be to pull out the clock Cross Trade or switch the clock Cross Trade, the clock in the single-deck and decide frame signal and exist always and remain unchanged.

The single-deck clock and decide frame signal maintenance constant after, it is constant that the sequential relationship of SDH signal also keeps thereupon, can not change with system clock and FP.Because exchange adopt is concentrated in the clock Cross Trade, exist between the SDH signal that need provide by single-deck and the FP of system one regular time relation.So at the system clock of clock Cross Trade with after decide the frame signal variation, the FP of system and this dish FPGA produce decides the deviation that frame signal LOCAL_FP (just unite with FP and referred to the FP of 8K and the MFP of 2K) exists phase place and time, the deviation of clock Cross Trade just of this deviation and single-deck SDH signal here.Like this, the SDH signal just no longer satisfies the requirement of clock Cross Trade.So, if they are not handled, will cause service disconnection, and irrecoverable.In this case, want the time relationship that single-deck SDH signal reaches clock Cross Trade requirement, just need to handle adjusting.Here utilize FPGA that the signal of clock Cross Trade and single-deck is adapted to again.Because the principle of following words is the same with last words, so only above words are introduced in detail for example.

Adopt a kind of method that is similar to carrying among the present invention: at first, utilize its RAM resource that carries to produce a dual port RAM with certain depth in the FPGA the inside.Then, with single-deck decide frame signal LOCAL_FP be time reference to produce one be the address sequence in cycle with a certain numerical value, the SDH data that single-deck will be gone to the clock Cross Trade are as the criterion with this address sequence earlier and are written to the RAM the inside according to certain order and carry out buffer memory.Simultaneously, be that one of time reference generation is the address sequence in cycle with a certain numerical value with the FP of system, with this address sequence data in buffer among the RAM is taken out by certain sequence, be sent to backboard.Like this, just can finish the adaptation of clock Cross Trade and single-deck signal.

The operation principle here just is similar to following Example: the streamline of a circulation, constantly put different materials of numbering at certain on a bit toward above, when a bit assembling in addition, as required, take down the material of needed numbering from streamline and assemble.

In the present invention, with single-deck LOCAL_FP is that benchmark produces the address and controls the process that writes RAM and just be equivalent to putting material on the streamline, RAM is the equal of this streamline, with the FP of system is that benchmark produces the address and the data of RAM the inside are read is equivalent to take down the material assembling from streamline, and the SDH signal is like the material of difference numbering.

When supposing the direct application system FP of single-deck, the relation that single-deck is gone to the J0 of SDH signal of clock Cross Trade and the FP of system when business is normal as shown in Figure 1.SDH frame and the FP of system that each system all requires each single-deck to be sent to the clock Cross Trade have a fixed relationship, and how long position and the FP of system of the J0 of the SDH signal of sending such as single-deck differ.Here we suppose the SDH signal that certain system requirements single-deck is sent J0 the position just in time with the FP of system at same position, this moment, the SDH frame just just in time can reach the requirement of clock Cross Trade.

When single-deck is used the LOCAL_FP of single-deck oneself generation, suppose that LOCAL_FP and the FP of system that single-deck oneself produces concern as shown in Figure 2.LOCAL_FP that single-deck oneself produces and the FP of system concerned in their cycle multiple possibility.Here suppose there be not other external action sometime, and their phase relation is fixing so, this moment LOCAL_FP than system FP leading a system clock cycle.We illustrate by the analysis of Fig. 3 how he reaches prior figures 1 desired clock Cross Trade and require under this phase relation.

Illustrated among Fig. 3 with the SDH data by RAM adaptive after, write the process of data and reading of data.In the address 0 that LOCAL_FP writes the SDH data by (be single-deck SDH signal J0 come time) in high RAM module 1 is taken up space, at other constantly,, the SDH signal is write in other address space of RAM module 1 also according to certain address rule.Simultaneously, when FP is high (the SDH signal J0 position that the clock Cross Trade requires), take out the temporary data in the inside, 0 space, 1 li address of RAM module, other the time appropriate address rule when writing, data temporary in 1 li other address space of RAM module are taken out.The data that write data and taking-up just as shown in Figure 3.Compare with Fig. 2, can see, the signal after the processing has just in time met the requirement of clock Cross Trade.

Shown in Figure 4, after the clock Cross Trade changed, the time that differs between FP and the LOCAL_FP changed, and has fallen behind 3 cycles such as FP than LOCAL_FP.Professional like this if communicate, delay 3 cycles when data are also normal than original business, just can meet the requirement of clock Cross Trade.According to the read-write rule of the FPGA the inside dual port RAM that we did, the relation of data of taking out in RAM and the FP of system is the same in the time of still normal with original business, has reached the requirement of clock Cross Trade thus.

So how the clock of guard system and FP do not change, the clock in the single-deck and decide frame signal constant all the time, and and the time relationship of clock Cross Trade after data are passed through RAM, just carried out automatic adjustment, guarantee can reach all the time the requirement of clock Cross Trade.

In the SDH system, because system itself is a Synchronous Digital Hierarchy, so each single-deck all is to use the clock of systematic unity and decides frame signal, all are to be benchmark with them.In the present invention, no longer be proper synchronous.Clock with the inner generation of this dish in each single-deck dish is a benchmark with deciding frame signal, just be to use the asynchronous frame signal of deciding, get rid of the clock of system and decide frame signal, be operated in asynchronous state with clock Cross Trade contrast, just adopt a kind of method that is similar to carrying to handle with FPGA in the place of their two linkings, with the clock of system with decide frame signal and carry out one subsynchronous, back level reach with the clock Cross Trade synchronously, make each single-deck go the SDH signal of clock Cross Trade and clock Cross Trade to adapt.That is to say, two asynchronous things, a transformational relation by the centre reaches synchronous.

In Fig. 6, the flow chart of method provided by the present invention is shown.Below the operating process of above words (being that the SDH signal is sent to the clock Cross Trade in the single-deck) be that example is set forth, following words are with upward to talk about principle the same, do not repeat them here (the counter 3, counter 4 and the RAM module 2 that are among Fig. 5 to be drawn that following words process is used.His course of work is consistent with last words process described below, the setting of counter 3, counter 4 is being provided with equally of sum counter 1, counter 2 also, operation for the RAM module also is the same, is that counter 3, counter 4 generation write addresses and the benchmark of reading the address are just in time opposite with last words process.Last words and following words are parallel processings, carry out simultaneously.So the narration of talking about operating process is down omitted).

When single-deck just powers on, first high level of detection system FP, FPGA is a benchmark with first high level of the FP of system, with the single-deck clock signal frequency division that the chock smotthing module lives again out, obtain a phase place and the FP of system and have certain relation, duplicate single-deck of cycle is decided frame signal Local_FP.Other the time Local_FP do not change with outside (as the clock Cross Trade), as long as the clock that the chock smotthing module is lived again exists, just free oscillation always.

Next, utilize its RAM resource, be the RAM of 1 twoport in the FPGA the inside.Whether be high: if for high, then counter 2 is changed to fixing several X2 if detecting Local_FP; If be low, be the cycle to produce other numerical value with N then with counter 2, form a series of Serial No.s at last.

Next, all sequences number that counter 2 is produced is as the write address of RAM module 1.

When single-deck needed toward back plate to send the SDH data, the address according to counter 2 produces write data in RAM module 1 space of distribution.

Meanwhile, whether detection system FP is high: if for high, then counter 1 is changed to fixing several X1; If be low, be the cycle to produce other numerical value with N then with counter 1, form a series of Serial No.s at last.

Then, all sequences number that counter 1 is produced is as the address of reading of RAM module 1.

According to the address that counter 1 produces, the SDH data that are temporarily stored among the RAM are read.

Send to the clock Cross Trade behind the SDH alignment of data that will from RAM module 1, take out.

The value of X1 and X2 is according to each system clock Cross Trade different and different to the RAM size of the requirement of following each single-deck and employed FPGA.When the simplest RAM of being module 1 is enough deposited next STM-1 frame or a STM-1 multi-frame, can allow X1 and X2 select same arbitrary value, regulate SDH signal that the SDH chip sends and the relation of LOCAL_FP by the register of configuration SDH chip then, the signal that single-deck is seen off reaches the requirement of clock Cross Trade.Also the register of SDH chip can be selected an arbitrary value, the value (X1=X2) of regulating X1 and X2 then reaches this purpose.Certainly X1 and X2 also can be unequal, can X1 choose arbitrarily and regulate the X2 value, also can X2 choose arbitrarily and regulate the X1 value.As long as be adjusted to the requirement that has reached the clock Cross Trade at last, the value of X1 and X2 is just fixing.

The value of N and RAM size, need data in buffer amount and single-deck clock relevant.Such as the data wire that is sent to the clock Cross Trade is 4, and clock is 38.88M.Under the enough situation of RAM, you will keep in the data of a STM-1 frame, and the value of N just is 4860 so; The data of a temporary STM-1 multi-frame, the value of N just is 19440.What meaning deposits 2 or 3 STM-1 frames does not have, concerning multi-frame too.When RAM deposited a STM-1 frame inadequately, the value when supposing to deposit next STM-1 frame was M, and the value of N be between the 0-M just, but controls more complicated, choose with the difficulty or ease of controlling according to the actual requirements.

When the RAM inside the FPGA is big inadequately, can shorten the degree of depth (promptly reducing the N value) of RAM, at this time need the control address counter, adjust the address sequence that counter produces, complicated in the time of enough than RAM, but all be that the principle of deferring to this carrying comes the Cross Trade of final sum clock synchronous.

The present invention uses the method for RAM only effective to the TelecomBus interface than low speed, also can be with the thought (adding control in addition) of the single-deck among the present invention oneself generation FP to CML or LVDS interface.

Fig. 7 is the service outage duration that certain EOS single-deck adopts the method for chip reset to record, and only distributes a VC12 (substantially quite not having Virtual Concatenation), can see that time of service interruption is bigger, basically about 1 second.Also occurred resetting the back business recovery not situation, do not write within this form.Decide frame signal because when some alien influences have shake in system clock or system like this, service damage bigger (just losing under the situation of linear speed about 148810 bags), the request that may cause the user as the 100M Ethernet do not have to respond or user's request repeatedly after abandon task (if any request only continue 512 milliseconds).Fig. 8 and Fig. 9 only distribute 1 VC12 (substantially quite not having Virtual Concatenation) after adopting this method, respectively the data that software switches and the hardware switching records.Time of service interruption is very short, is to adopt similar 1/100 of chip reset method.Figure 10 and Figure 11 distribute 63 VC12 (all Virtual Concatenations) after adopting this method, respectively the data that software switches and the hardware switching records.Because the relation of Virtual Concatenation, service outage duration have increase slightly, still more a lot of than the method for taking chip reset, basically within the scope of some retransmission mechanisms of business.

The foregoing description only is exemplary, it will be apparent to those skilled in the art that not break away from the spirit and scope of the present invention, can make amendment and changes the present invention.Scope of the present invention is defined by appended claim.

Claims (10)

1. one kind is adopted async framing pulse (FP) to solve the method that system clock in Synchronous Digital Hierarchy (SDH) optical-fiber network and FP change, and it is characterized in that may further comprise the steps:

A) single-deck is decided system FP signal and system's multi-frame pulse (MFP) signal of frame signal from clock Cross Trade receiving system clock and as system, and obtains the single-deck clock by system clock;

B) utilize this single-deck clock to come detection system to decide the high level of frame signal, and utilize system to decide frame signal in single-deck, to produce single-deck and decide frame signal (LOCAL_FP);

C) judge whether single-deck is decided frame signal is high level, when being judged as high level, begin the SDH data of single-deck are write in the first memory of single-deck, the data in the second memory of single-deck are taken out be sent to the SDH chip simultaneously;

D) judge whether system decides frame signal is high level, when being judged as high level, begin data temporary in the first memory of single-deck are taken out, and data are sent to the clock Cross Trade, be written in the second memory of single-deck for the data of single-deck the clock Cross Trade simultaneously.

2. in accordance with the method for claim 1, wherein decide frame signal when first high level occurring when system, with single-deck clock signal frequency division, produce that to decide the frame signal cycle identical with system, the single-deck that phase place is different is decided frame signal.

3. in accordance with the method for claim 2, if wherein do not detect first high level that system decides frame signal, single-deck is decided frame signal and is kept free oscillation, remains unchanged.

4. in accordance with the method for claim 1, wherein single-deck is decided frame signal and is comprised single-deck FP signal and single-deck MFP signal.

5. in accordance with the method for claim 1, wherein the single-deck clock is constant, does not change with the clock Cross Trade.

6. in accordance with the method for claim 1, wherein to decide frame signal constant for single-deck, do not decide frame signal with system and change.

7. in accordance with the method for claim 1, wherein, produce a write address, and the SDH data are write in the first memory of single-deck according to the write address X2 that is produced with fixed value X2 when judging that single-deck decides frame signal when being high level; Simultaneously, produce a address of reading, and read address X1, the data in the second memory of single-deck are taken out be sent to the SDH chip according to what produce with fixed value X1; Decide frame signal when being low level when judging single-deck, the generation one-period is that the Serial No. of N is used as write address, and write the SDH data in the first memory of single-deck according to the write address that is produced, the Serial No. that produces one-period simultaneously and be N is used as reading the address, the data in the second memory of single-deck is taken out be sent to the SDH chip.

8. in accordance with the method for claim 1, wherein decide frame signal when being high level when the judgement system, produce a address of reading with fixed value X1, and read address X1 according to what produce, read in the SDH data of keeping in the first memory of single-deck, produce a write address simultaneously, and, be written in the second memory of single-deck for the data of single-deck the clock Cross Trade according to the write address that is produced with fixed value X2; When the judgement system decides frame signal when being low level, the generation one-period is that the Serial No. of N is used as reading the address, and will be according to the address of reading that is produced, read in the SDH data of keeping in the first memory of single-deck, simultaneously, the generation one-period is that the Serial No. of N is used as write address, is written in the second memory of single-deck for the data of single-deck the clock Cross Trade.

9. in accordance with the method for claim 1, wherein after reading temporal data, clock Cross Trade or SDH chip will be sent to behind the alignment of data.

10. an application rights requires the single-deck of any one described method of 1-9, and wherein, this single-deck comprises:

The chock smotthing module is used for from clock Cross Trade receiving system clock, and produces new single-deck clock; And

Field programmable device is used to produce constant single-deck and decides frame signal, and provides temporary from the data of SDH chip or clock swapdisk, and it further comprises:

Decide the frame signal generation module, be used for deciding frame signal according to system, the single-deck clock that the chock smotthing module is produced carries out frequency division, produces that to decide the frame signal cycle identical with system, and the single-deck that phase place is different is decided frame signal;

Memory, be used for temporary from the SDH chip data-signal or come the data-signal of self-clock Cross Trade; And counter, be used for producing memory data read address or write address.

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