CN100573858C - 芯片封装体 - Google Patents

芯片封装体 Download PDF

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Publication number
CN100573858C
CN100573858C CNB200710180151XA CN200710180151A CN100573858C CN 100573858 C CN100573858 C CN 100573858C CN B200710180151X A CNB200710180151X A CN B200710180151XA CN 200710180151 A CN200710180151 A CN 200710180151A CN 100573858 C CN100573858 C CN 100573858C
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chip
reference planes
support plate
guide hole
packing
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CN101136382A (zh
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许志行
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Via Technologies Inc
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Via Technologies Inc
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Abstract

一种芯片封装体，其包括一载板、至少一配置在载板上的芯片、多条电连接载板及芯片的导线及一包覆芯片及这些导线的封胶。芯片具有一半导体基底、一内连线结构、至少一第一参考平面、至少一第二参考平面及至少一芯片导孔，其中第一参考平面及第二参考平面分别位于半导体基底的两面，而内连线结构位于第一参考平面及半导体基底上。芯片导孔将第一参考平面连接至第二参考平面。芯片封装体更包括至少一导电接合层，其将第二参考平面接合至载板。

Description

芯片封装体
技术领域
本发明涉及一种集成电路(Integrated Circuit，以下简称IC)芯片封装体，且特别是有关于一种将芯片的两面分别电连接至承载芯片的载板的封装体。
背景技术
集成电路(IC)工艺技术的进步使得芯片的信号密度增加。就导线接合(wire bonding)搭配载板的封装型态而言，芯片是配置在载板上，并藉由多条导线来电连接芯片及载板。然而，当芯片的信号密度的增加时，电磁效应在导线间所产生的电感性耦合相对增加，这使得传输于导线中的信号在切换时所受到的噪声串音干扰相当严重。
因此，为了有效维持信号传输的品质，倒装芯片接合(flip chip bonding)搭配载板的封装型态已受到采用，而这样的封装型态可以减少噪声串音干扰。然而，在成本上，倒装芯片接合搭配载板的封装型态仍高于前述的导线接合搭配载板的封装型态。因此，无论是上述那种封装型态，如何维持信号传输品质同时降低制造成本便成为发展的目标。
发明内容
本发明涉及一种芯片封装体，用以封装芯片。
本发明提供一种芯片封装体，其包括一载板、至少一芯片、至少一导电接合层、至少一导线及一封胶。载板具有一第一载板表面。芯片具有一半导体基底、一内连线结构、至少一第一参考平面、至少一第二参考平面及至少一芯片导孔，其中半导体基底具有一第一基底表面及相对的一第二基底表面，而第一参考平面及第二参考平面分别位于第一基底表面及第二基底表面上，且内连线结构位于第一参考平面及第一基底表面上并具有至少一芯片信号垫，而芯片导孔将第一参考平面连接至第二参考平面。导电接合层将第二参考平面接合至载板的第一载板表面。导线将芯片信号垫连接至载板的第一载板表面。封胶包覆芯片及导线。
本发明藉由芯片导孔来穿过半导体基底以将芯片的参考平面直接电连接至载板，故可减少用来连接参考平面的导线的数量，并可缩小芯片的面积。
为让本发明的上述和其它目的、特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1绘示本发明一实施例的一种芯片封装体的局部剖面。
图2绘示图1的A部分的放大图。
图3绘示本发明另一实施例的一种芯片封装体的局部剖面放大。
附图标记说明
100：芯片封装体           110：载板
110a：第一载板表面        110b：第二载板表面
110s：载板信号垫          112：第一参考接垫
114：第二参考接垫         116：载板导孔
120：芯片                 121：半导体基底
121a：第一基底表面        121b：第二基底表面
122：内连线结构           122s：芯片信号垫
123：第一参考平面         124：第二参考平面
125：芯片导孔             125A：芯片导孔
126：绝缘层
130：导线                 140：封胶
150：导电接合层           160：导电体
170：电子元件
具体实施方式
图1绘示本发明一实施例的一种芯片封装体局部剖面，而图2绘示图1的A部分的放大图。请参考图1及图2，本发明一实施例的一种芯片封装体100包括一载板110、一芯片120、多条导线130及一封胶140，其中芯片120配置于载板110上，而这些导线130将芯片120电连接至载板110，且封胶140包覆芯片120及这些导线130。
芯片120包括一半导体基底121及一内连线结构122。半导体基底121例如为一硅基底，并具有一第一基底表面121a及相对的一第二基底表面121b，且内连线结构122位于第一基底表面121a上。
内连线结构122包括多个芯片信号垫122s，其由内连线结构122的金属线路所构成，并位于内连线结构122的顶部。此外，载板110具有多个载板信号垫110s，其位于载板110的一第一载板表面110a上，而这些导线130连接这些载板信号垫110s及这些芯片信号垫122s。因此，芯片120中位于第一基底表面121a上的电子元件170，例如：晶体管或是电容等，可藉由内连线结构122及这些导线130电连接至载板110。前述电子元件170可以藉由半导体工艺技术形成，电子元件170并不限于是有源元件或无源元件，而第一基底表面121a可视为芯片有源面。
芯片120更包括多个第一参考平面123，而这些第一参考平面123位于第一基底表面121a上，且内连线结构122则位于第一基底表面121a及这些第一参考平面123上。因此，芯片120中位于第一基底表面121a上的电子元件170，例如：晶体管或是电容等，可藉由内连线结构122电连接至这些第一参考平面123。
芯片120更包括多个第二参考平面124及多个芯片导孔125，其中第二参考平面124位于第二基底表面121b，而这些芯片导孔125穿过半导体基底121内部，而将这些第一参考平面123分别连接至这些第二参考平面124。在本实施例中，芯片更具有一绝缘层126，例如为二氧化硅(SiO2)层，其位于半导体基底121及这些第二参考平面124之间与半导体基底121及这些芯片导孔125之间。
在本实施例中，这些第一参考平面123可包括接地平面、电源平面或两者，而这些第二参考平面124可依照其所电连接的第一参考平面123而为接地平面或电源平面。此外，这些第二参考平面124可为单一层，例如金层，或为一复合层，例如包括钛层、铜层及镍层的复合层或包括钛层、镍钒层及铜层的复合层。此外，参考平面123、124的形状可为环状。
在本实施例中，这些芯片导孔125是穿过半导体基底121的内部来分别连接这些第一参考平面123及这些第二参考平面124。在另一实施例中，如图3所示，芯片导孔125A可绕过半导体基底121的外侧来分别连接这些第一参考平面123及这些第二参考平面124。
请继续参考图1及图2，芯片封装体100更包括多个导电接合层150，而这些导电接合层150分别将这些第二参考平面124接合至载板110的第一载板表面110a，以与载板110相电连接。这些导电接合层150的材质可为焊料，例如锡银铜合金、锡银合金、锡铜合金或锡铅合金，或为导电胶(conductive adhesive)。
因此，这些参考平面123可不经由这些导线130来电连接至载板110，而是藉由这些芯片导孔125、这些第二参考平面124及这些导电接合层150来电连接至载板110。
在本实施例中，载板110可具有多个第一参考接垫112，其位于载板110的第一载板表面110a上，而这些导电接合层150将这些第二参考平面124分别接合至这些第一参考接垫112。此外，载板110更可具有多个第二参考接垫114及多个载板导孔116，而第二参考接垫114位于一相对于第一载板表面110a的第二载板表面110b上，且这些载板导孔116将第一参考接垫112分别电连接至第二参考接垫114。
此外，芯片封装体100更可包括多个导电体160，其分别连接至这些第二参考接垫114。在本实施例中，这些导电体160可为导电球。在其它未绘示的实施例中，这些导电体160可为导电针。因此，芯片120可经由这些导电体160而电连接至下一层级的元件或装置。
综上所述，在上述实施例中，藉由芯片导孔来穿过半导体基底以将芯片的参考平面直接电连接至载板，故可减少用来连接参考平面的导线的数量，并可缩小芯片的面积。因此，芯片封装体的生产成本可相对降低，而其生产速度亦可相对提升。此外，在导线数量降低的情况下，原先用来传输信号的导线的长度亦可对应缩短，故可降低噪声串音干扰的程度及信号线的阻抗不匹配的程度。另外，芯片封装体的参考平面可更加完整。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中的技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视所附的权利要求书所界定者为准。

Claims (10)

1.一种芯片封装体，包括：
一载板，具有一第一载板表面；
至少一芯片，具有一半导体基底、一内连线结构、至少一第一参考平面、至少一第二参考平面及至少一芯片导孔，其中该半导体基底具有一第一基底表面及相对的一第二基底表面，而该第一参考平面及该第二参考平面分别位于该第一基底表面及该第二基底表面上，且该内连线结构位于该第一参考平面及该第一基底表面上并具有至少一芯片信号垫，而该芯片导孔将该第一参考平面连接至该第二参考平面；
至少一导电接合层，将该第二参考平面接合至该载板的该第一载板表面；
至少一导线，将该芯片信号垫连接至该载板的该第一载板表面；以及
一封胶，包覆该芯片及该导线。
2.如权利要求1所述的芯片封装体，其中该第一参考平面为接地平面或电源平面，而该第二参考平面对应其所连接的该第一参考平面为接地平面或电源平面。
3.如权利要求1所述的芯片封装体，其中该第二参考平面包括金层。
4.如权利要求1所述的芯片封装体，其中该第二参考平面为一复合层，其包括钛层、铜层及镍层。
5.如权利要求1所述的芯片封装体，其中该第二参考平面为一复合层，其包括钛层、镍钒层及铜层。
6.如权利要求1所述的芯片封装体，其中该芯片导孔穿过该半导体基底的内部来将该第一参考平面连接至该第二参考平面。
7.如权利要求1所述的芯片封装体，其中该芯片导孔绕过该半导体基底的外侧来将该第一参考平面连接至该第二参考平面。
8.如权利要求1所述的芯片封装体，其中该载板具有至少一第一参考接垫，其位于该载板的该第一载板表面上，而该导电接合层将该第二参考平面接合至该第一参考接垫。
9.如权利要求8所述的芯片封装体，其中该载板具有一相对于该第一载板表面的一第二载板表面、至少一第二参考接垫及至少一载板导孔，而该第二参考接垫位于该第二载板表面上，且该载板导孔将该第一参考接垫连接至该第二参考接垫。
10.如权利要求1所述的芯片封装体，其中该芯片更包括一电子元件，该电子元件配置于该第一基底表面上，而该电子元件藉由该内连线结构电连接至该第一参考平面。
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