CN100570832C - Slow down towards the manufacture method of layer concentration inner transparent collecting zone igbt - Google Patents

Slow down towards the manufacture method of layer concentration inner transparent collecting zone igbt Download PDF

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CN100570832C
CN100570832C CNB2008102405149A CN200810240514A CN100570832C CN 100570832 C CN100570832 C CN 100570832C CN B2008102405149 A CNB2008102405149 A CN B2008102405149A CN 200810240514 A CN200810240514 A CN 200810240514A CN 100570832 C CN100570832 C CN 100570832C
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manufacture method
micron
layer
helium
thickness
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CN101436542A (en
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亢宝位
胡冬青
吴郁
单建安
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Beijing University of Technology
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Beijing University of Technology
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Abstract

Slow down and belong to transistorized manufacturing field towards the manufacture method of layer concentration inner transparent collecting zone igbt.The present invention forms an extremely low excess carrier Lifetime Control district in the certain limit near the collector region of device.Its technical scheme is to utilize injection of high dose helium and subsequent anneal technology to introduce local lar nanometric cavities layer near the nearly collector junction of device collector region, this lar nanometric cavities not only can be introduced defect level near center, silicon forbidden band, reduce carrier lifetime greatly, and has good high-temperature stability, this technology can be made original adoption at device, with the common process flow process good processing compatibility is arranged.This technology, the technology routine, controllability is strong, and is applied widely, help realizing low cost and high finished product rate, and device performance is good.

Description

Slow down towards the manufacture method of layer concentration inner transparent collecting zone igbt
Technical field:
The present invention relates to a kind of method, semi-conductor device manufacturing method, more specifically saying so relates to a kind of manufacture method of insulated gate bipolar transistor with silicon material inner transparent collecting zone, the withstand voltage scope of this device below 1200V in, low pressure range.Be applicable to planar gate and trench-gate device.
Background technology:
Igbt (IGBT) is as switching device important in the power electronic technology, combine the advantage of bipolar junction transistor (BJT) and mos field effect transistor (MOSFET), have combination property advantages such as conduction loss is low, switching speed is fast, operating frequency height, it is widely used in motor variable-frequency speed-regulating circuit, uninterrupted power supply circuit, inverter type welder circuit etc.IGBT since the 1980's inventions (referring to 1982 IEDM Tech.Dig., pp.246-247, IEEE Transaction on Power Electronics, Vol.PE-2, No.3, PP.194-207), the optimization of device architecture---and then performance index improve---has obtained great development.Single with regard to structure, comprise punch (PT), non-punch (NPT) and a termination type (FS).
PT-IGBT is parent material (substrate) with the P+ monocrystalline of hundreds of micron thickness, extension N+ resilient coating and N-Withstand voltage layer afterwards, and complicated Facad structure is made on epitaxial loayer.PT-IGBT is a ripe the earliest class IGBT who goes into operation, and it has technical maturity, easy to control, rate of finished products advantages of higher.But the IGBT of this structure, its collector region are the thick substrate of heavy doping, are nontransparent to the minority carrier electronics.Compromise between break-over of device pressure drop and the turn-off power loss, main control by optimization buffer layer structure (mixing and thickness) and overall carrier lifetime realized.The low life-span of overall situation charge carrier is caused conduction voltage drop V CEsatHave negative temperature coefficient, the thermoelectric positive feedback effect is easy to make current concentration, brings out second breakdown, and the device poor high temperature stability is unfavorable for parallel operation.
In the high pressure IGBT development process, in order to evade expensive that thick extension brings, 1980 generation ends NPT-IGBT occurred (referring to 1989 PESC Record 1, PP.21-25; 1996 ISPSD, PP.331-334 and PP.164-172).It is parent material that NPT-IGBT adopts N-type monocrystalline, positive complicated structure is fabricated directly on the single crystalline substrate, adopt grinding, corroding method to be thinned to withstand voltage required thickness from substrate back after Facad structure is finished, inject formation P+ collector region by ion afterwards.This collector region is very thin, is no more than 1 micron, and doping content is lower, is transparent to few sub-electronics, and the electric current by collector junction is based on electron stream (accounting for 70%).In the device turn off process, the excessive electronic energy that is stored in the drift region flows out rapidly by transparent collecting zone, and the hole just can flow to emitter originally smoothly.Like this, NPT-IGBT does not need carrier lifetime control just can realize turn-offing fast by the transparent collecting zone technology.And because the life-span long enough of drift region charge carrier, so on-state voltage drop V CEsatHas positive temperature coefficient.This main advantages of transparent collecting zone technology just, after the NPT-IGBT invention, emerging various IGBT substantially adopt the transparent collecting zone technology.For example, FS-IGBT (referring to 2000 ISPSD PP.355-358).
But adopt all kinds of IGBT structures of transparent collecting zone technology, manufacturing to the above IGBT of kilovolt is particularly suitable for, and for making the withstand voltage very big manufacturing difficulty that runs into when the IGBT of 1200V and following extensive application: because of the silicon wafer thickness of required withstand voltage correspondence too thin, easily take place in the manufacture process that fragment, song stick up etc., cause that rate of finished products is low, cost is high.FS-IGBT with withstand voltage 600V is an example, when chip thinning also will have repeatedly cleaning, ion injection, annealing, metallization deposition, alloy or the like behind the 70-80 micron, how to keep not that fragment, non-warpage, defective are low, the rate of finished products height is an extremely severe problem.This meets difficulty applying of this technology.For this reason, applicant has proposed to have the igbt structure (referring to Chinese patent 200710063086.2) of inner transparent collecting zone.
High dose helium is injected into silicon semiconductor material, can in silicon, bring out and form the helium bubble, subsequent anneal technology makes the evaporation of helium bubble, form lar nanometric cavities, this lar nanometric cavities has changed silicon materials Local Structure and electrical characteristics, in semiconductor technology, can be used for the excess carrier Localized Lifetime Control (referring to 1997 IEEE electron devices, PP.333-335), super shallow junction boron diffusion (J.Appl.Phys.101,2007), SiGe substrate Stress Release (Nucl.Instrum.Methods Phys.Res.B175-177,2001) etc., but this technology is not seen the collector region that is used for power semiconductor.The objective of the invention is to utilize this technology, introduce an extremely low excess carrier Lifetime Control district, for realizing transparently in the collector region providing a kind of manufacture method at the collector region of IGBT.This manufacturing process is equally applicable to semiconductor die brake tube and MCT.
Summary of the invention
The present invention is directed to existing 1200V (containing) with interior IGBT manufacturing technology all not really ideal improve, collector region inject by high dose helium near the position of collector junction and annealing to form the lar nanometric cavities thin layer be the emphasis (referring to the zone 2 of Fig. 1) of the technology of the present invention.Lar nanometric cavities itself can be introduced defect level near the central authorities of silicon forbidden band, can greatly reduce lar nanometric cavities layer and near zone excess carrier life-span, and this is that it can make transparent key in the collector region.The lar nanometric cavities layer has good high-temperature stability simultaneously, and in the introducing that begins most of device manufacturing, ion implantation energy is relatively low, and the conventional ion implanter just can meet the demands, and does not need special injection device, and this is another characteristics of the present invention.The 3rd, lar nanometric cavities has the effect of absorbing impurity, can absorb the impurity that device active region is not expected, improve device performance, and the absorption of metal impurities can further increase the compound of excess carrier, improves the collector region transparency.
This manufacture method is at first carried out following steps:
A) be that the surface of the monocrystalline silicon P+ substrate of 0.02-0.005 Ω cm is carried out the helium ion and injected in resistivity, the dosage that each helium ion injects is 1 * 10 15-1 * 10 17Cm -2, the energy range that helium injects is at 20keV-1000keV,
B) implement low, high annealing, atmosphere low, high annealing is argon gas or vacuum; The process annealing temperature is at 400-900 ℃, and the time is at 30-300 minute, and the temperature of high annealing is at 1000-1150 ℃, time 10-300 minute;
C) epitaxial buffer layer: implement earlier substrate to be thrown erosion before the epitaxy technique, throwing erosion thickness is the 0.1-1 micron; The resilient coating extension adopts varying doping concentration extension, and varying doping concentration buffer layer ground floor is higher-doped concentration, and the doping scope is in 1-50 * 10 17Cm -3, thickness 0.1-5 micron; The second layer is than light dope, concentration 1-10 * 10 16Cm -3, thickness 1-15 micron;
All the other technologies are made the technology that is adopted according to punch IGBT;
Near the nearly collector junction of device collector region, form an extremely low excess carrier Lifetime Control district, be called the lar nanometric cavities layer with stabilized nano cavity defective; The thickness of lar nanometric cavities layer is the 0.2-3 micron, and between the 0.1-5 micron, the doping content on final collector region surface is 5 * 10 from the final distance of collector junction in lar nanometric cavities layer coboundary 16Cm -3To 5 * 10 18Cm -3
The characteristics of the technology of the present invention are to form the concrete manufacture method of lar nanometric cavities layer, the number of times that the width that this manufacture method can make the lar nanometric cavities layer injects by helium and energy is reasonably combined adjusts, scope is from 0.2 micron to 3 microns, lar nanometric cavities layer coboundary and can be from 0.1 micron to 5 microns apart from the position of collector junction, methods such as the energy that it injects by helium, buffer layer concentration adjusting realize.Concrete technology process is as follows:
(1) carrying out high dose helium on resistivity is the low-resistance P+ single crystalline substrate of 0.02-0.005 Ω cm injects.The purpose that high dose helium injects is to introduce high concentration defective and helium bubble (referring to the zone 11 of accompanying drawing 2 (a)) at the silicon single crystal regional area, and the number of times that helium injects is 1-5 time, for example 1 time, and 2 times, 3 times.Each dosage that injects is 1 * 10 15-1 * 10 17Cm -2Scope, for example 3 * 10 16Cm -2, 4 * 10 16Cm -2Or 5 * 10 16Cm -2Each energy that injects is at 20keV-1000keV, 50keV for example, 100keV, 200keV, 400keV, 600keV etc.The combination of different-energy, dosage is injected, and has determined the scope of high concentration defect area and the high concentration defect center distance apart from the surface.The typical case is injected to: once inject energy 20-1000keV, dosage 1-10 * 10 16Cm -2(implementing to inject the back effect) referring to accompanying drawing 2 (a-1); Twice injection, the energy that injects is 20-600keV for the first time, dosage 1-10 * 10 16Cm -2For the second time injecting energy is 300-1000keV, dosage 2-8 * 10 16Cm -2, perhaps order (implements to inject the back effect referring to accompanying drawing 2 (a-2)) on the contrary; Inject for three times: the energy that injects is 20-300keV for the first time, dosage 1-5 * 10 16Cm -2For the second time injecting energy is 200-700keV, dosage 2-6 * 10 16Cm -2Injecting energy for the third time is 300-1000keV, dosage 2-6 * 10 16Cm -2, perhaps order is opposite.
(2) lower temperature annealing under inert atmosphere or under the vacuum condition, purpose is to make the evaporation of helium bubble, form the lar nanometric cavities floor---a low excess carrier Lifetime Control district (a helium injection is referring to the zone 2 of accompanying drawing 2 (b-1), and secondary helium injects the zone 2 referring to accompanying drawing 2 (b-2)).Annealing temperature is at 400-900 ℃, and the duration is 30-300 minute, and for example 600 ℃, 200 minutes; Perhaps 700 ℃, 50 minutes; Perhaps 750 ℃, 40 minutes.
(3) higher temperature annealing under inert atmosphere or under the vacuum condition.The purpose of high annealing has three: the first, recover surperficial lattice damage (referring to the zone 14 of the zone 13 of accompanying drawing 2 (a-1), accompanying drawing 2 (a-2) and accompanying drawing 2 (b-1), accompanying drawing 2 (b-2)), and guarantee the quality of epitaxial loayer in the follow-up epitaxy technique; The second, make surperficial P+ impurity concentration reduce (referring to accompanying drawing 2 (c-1), accompanying drawing 2 (c-2)), weaken in the subsequent process in the P+ substrate impurity to the diffusion of epitaxial loayer; The 3rd, make lar nanometric cavities further grow up, stablize, finally the scope (polyphones of several lar nanometric cavities floor) in low excess carrier Lifetime Control district is between the 0.2-3 micron, for example 0.3 micron, 0.5 micron, 1 micron etc., number of times and energy combination decision that occurrence is injected by helium.
High annealing is to finish direct intensification the in back in process annealing to carry out.Annealing temperature is 1000-1150 ℃, time 10-300 minute, for example is warmed up to 1100 ℃, 200 minutes retention times.Surface region impurity concentration after the annealing forms certain concentration gradient and distributes in (referring to the zone 16 of Fig. 2 (c-1), Fig. 2 (c-2)) than low in the body, and surface concentration can be than reducing an order of magnitude (referring to Fig. 2 (d)) in the body.
(4) epitaxial buffer layer.In order to guarantee good epitaxial growth plane, the growth front surface is thrown erosion 0.1-1 micron, for example 0.3 micron, 0.5 micron, 0.8 micron grade (referring to the zone 4 of accompanying drawing 2 (c-1), accompanying drawing 2 (c-2)).At this moment, the collector junction of device is positioned at epitaxial loayer and substrate interface (referring to the position 5 of accompanying drawing 2 (e-1), accompanying drawing 2 (e-2)).In order to slow down of the propelling of subsequent process collector junction to resilient coating, guarantee that extremely low excess carrier Lifetime Control offset collector junction is enough near, the resilient coating extension is divided into two-layer: ground floor is than heavy doping, concentration 1-50 * 10 17Cm -3, for example 2 * 10 17Cm -3, 5 * 10 17Cm -3, 7 * 10 17Cm -3, 1 * 10 18Cm -3, 2 * 10 18Cm -3Thickness 0.1-10 micron; For example 2 microns, 3 microns, 5 microns etc.Concentration 1-10 * 10 16Cm -3, for example 1 * 10 16Cm -3, 5 * 10 16Cm -3, 7 * 10 16Cm -3, thickness 1-15 micron, for example 2 microns, 5 microns, 10 microns etc.
(5) extension Withstand voltage layer (referring to the zone 22 of Fig. 2 (f-1), Fig. 2 (f-2)).This technology is identical with conventional PT-IGBT.Extension concentration is relevant with thickness and requirement of withstand voltage.
(6) finish positive MOS structure and thinning back side and multi-layered electrode technology.This step is identical with conventional PT-IGBT manufacturing process.
After the experience entire device manufacturing process, collector junction can leave initial epitaxial interface and further advance to epitaxial loayer, and propelling degree and epitaxial layer concentration, substrate concentration are relevant.Final collector junction position is respectively as the position 6 of Fig. 2 (f-1), Fig. 2 (f-2).They are the 0.1-5 micron apart from the distance from top of lar nanometric cavities layer, and representative value is as 0.2 micron, 0.5 micron, 0.8 micron, 1 micron, 1.5 microns, 2 microns etc.; The lar nanometric cavities layer is crossed over scope at the 0.2-3 micron, and for example 0.3 micron, 0.5 micron, 1 micron etc.; The doping content on simultaneously final collector region surface (referring to the position 6 of Fig. 2 (f-1), Fig. 2 (f-2)) is 5 * 10 16Cm -3To 5 * 10 18Cm -3, for example 1 * 10 17Cm -3, 5 * 10 17Cm -3, 7 * 10 17Cm -3, 1 * 10 18Cm -3Deng.
More than manufacture method of the present invention and procedure arrangement, with existing PT-IGBT manufacturing process good compatibility is arranged, only need formation lar nanometric cavities layer the common process flow process begins before.Technology is simple and clear, and controllability is strong, helps realizing high finished product rate.In addition, this method is not only applicable to IGBT, and is applicable to thyristor and MOS control thyristor, thereby the scope that is widely used.Because the present invention can introduce low excess carrier Lifetime Control district near the nearly collector junction of collector region, make collector region by transparent in nontransparent the becoming, therefore can produce the following IGBT of withstand voltage 1200V that switching speed is fast, combination property is excellent.
Description of drawings
Fig. 1 has the planar gate IGBT structural representation (passivation layer does not draw) of inner transparent collecting zone
1---low-resistance P+ single crystalline substrate
2---the lar nanometric cavities layer
3---actual collector region
4---thrown the substrate part of erosion before the extension
5---the epitaxial loayer original position
6---final collector junction position
7---resilient coating
8---Withstand voltage layer
9---positive MOS structure
10---back side multi-layered electrode
The main technique that Fig. 2 manufacture method of the present invention comprises
(a) high dose helium injects;
(b) lower temperature annealing under inert atmosphere or under the vacuum condition;
(c) higher temperature annealing under inert atmosphere or under the vacuum condition;
(d) the surperficial low concentration district CONCENTRATION DISTRIBUTION of high annealing formation
(e) resilient coating extension
(f) other preceding road technologies are finished chip structure
11---high density of defects and helium bubble compact district
12---the high density of defects center
13---the surface is than the low-density defect area
14---the superficial layer that helium atom evaporation, defect part are eliminated
2---lar nanometric cavities floor (low excess carrier Lifetime Control district)
16---surface doping concentration transition region
4---thrown the surf zone of erosion before the extension
18---remaining lattice perfection district before the extension
19---the heavy doping resilient coating
20---the light dope resilient coating
5---epitaxial interface (initial collector junction position)
22---extension Withstand voltage layer (base)
23---technology finishes the expansion of rear region 18 to epitaxial loayer
6---final collector junction position
Embodiment
Choice points such as the ion implantation dosage in the technical solution of the present invention concrete steps, energy, annealing temperature, time, atmosphere, epitaxial layer concentration and thickness, as long as drop on the scope that the present invention provides, just can reach the requirement of the IGBT with inner transparent collecting zone structure of manufacturing of the present invention.The common technical staff that is adjusted into of these choice points grasps and technique known.
With reference to the accompanying drawings technology is done a review paper below: on single crystalline substrate 1, carry out high energy helium and inject, form high concentration helium bubble and defect area 11, under argon gas or vacuum atmosphere, carry out low, high annealing afterwards, process annealing makes the evaporation of helium bubble form lar nanometric cavities layer 2, and high annealing is restored the lattice damage of the low defect area 13 in surface.Low, high-temperature annealing process finishes laggard row buffering layer extension.For guaranteeing good epitaxial growth interface, before the extension surface region 4 is thrown eating away, and the certain thickness perfect lattice of residue district 18 on the lar nanometric cavities floor.The resilient coating extension adopts the varying doping extension, is made of higher concentration district 19 and low concentration district 20.Resilient coating technology is finished follow-up operation according to conventional punch IGBT manufacturing process after finishing, and comprises extension Withstand voltage layer 22, forms surperficial MOS structure 9, substrate thinning and 10 manufacturings of back side multi-layered electrode etc.After whole technology finished, collector junction was advanced to position 6 by initial position 5, and actual collector region is zone 3.
According to technical scheme of the present invention, the manufacture method of enumerating a helium injection, twice and 5 times helium injection inner transparent collecting zone IGBT respectively illustrates operational feasibility of the present invention below.
Embodiment 1: single, monoergic helium inject the manufacture method of surperficial grid n ditch inner transparent collecting zone IGBT:
Referring to Fig. 2, adopt the present invention to make a kind of n ditch IGBT, withstand voltage 600V with inner transparent collecting zone.The technology manufacturing step that adopts is as follows: (1) is implemented high dose helium in p+ low resistivity substrate (about resistivity 0.01 Ω cm) and is injected, and the energy that the helium ion injects is 200keV, and dosage is 2 * 10 16Cm -2(2) silicon chip is annealed under argon gas atmosphere, concrete annealing was divided into for two steps: be warmed up to 700 ℃ earlier, kept 50 minutes, be warmed up to 1100 ℃ afterwards again, kept 300 minutes; (3) epitaxial buffer layer and Withstand voltage layer: in the epitaxial process, earlier substrate is thrown erosion, throwing erosion thickness is about 0.5 micron, carries out extension afterwards.Epitaxial buffer layer concentration is divided two-layer, ground floor concentration 1 * 10 17Cm -3, 5 microns of thickness; Second layer concentration 2 * 10 16Cm -3, 10 microns of thickness.The Withstand voltage layer doping content is 7 * 10 13Cm -3, 55 microns of thickness.(4) afterwards technology routinely flow process carry out, finish surperficial MOS earlier and make, surface passivation, thinning back side, metallization etc. finally form the cross-section structure shown in Fig. 2 (f).
About 0.3 micron of the thickness of the lar nanometric cavities layer that forms by this technology, lar nanometric cavities layer coboundary is about about 2.5 microns from the final distance of collector junction, and the doping content on collector region surface is 1 * 10 17Cm -3About.Resulting devices conduction voltage drop representative value is 1.5V, and representative value fall time of turn off process is 600ns.Zero temperature coefficient point corresponding current density is 40A/cm 2About, be lower than nominal current density and (be generally 150-200A/cm 2), in the device working range, have the voltage positive temperature coefficient.
Embodiment 2: single, monoergic helium inject the manufacture method of surperficial grid n ditch inner transparent collecting zone IGBT:
Referring to Fig. 2, adopt the present invention to make a kind of n ditch IGBT, withstand voltage 600V with inner transparent collecting zone.The technology manufacturing step that adopts is as follows: (1) is implemented high dose helium in p+ low resistivity substrate (about resistivity 0.01 Ω cm) and is injected, and the energy that the helium ion injects is 1000keV, and dosage is 1 * 10 17Cm -2(2) silicon chip is annealed under vacuum atmosphere, concrete annealing was divided into for two steps: be warmed up to 400 ℃ earlier, kept 300 minutes, be warmed up to 1000 ℃ afterwards again, kept 300 minutes; (3) epitaxial buffer layer and Withstand voltage layer: in the epitaxial process, earlier substrate is thrown erosion, throwing erosion thickness is about 1 micron, carries out extension afterwards.Epitaxial buffer layer concentration is divided two-layer, ground floor concentration 1 * 10 17Cm -3, 3 microns of thickness; Second layer concentration 1 * 10 16Cm -3, 15 microns of thickness.The Withstand voltage layer doping content is 1 * 10 14Cm -3, 55 microns of thickness.(4) afterwards technology routinely flow process carry out, finish surperficial MOS earlier and make, surface passivation, thinning back side, metallization etc. finally form the cross-section structure shown in Fig. 2 (f).
About 0.3 micron of the thickness of the lar nanometric cavities layer that forms by this technology, lar nanometric cavities layer coboundary is about 5.0 microns from the final distance of collector junction, the doping content on collector region surface is 5 * 10 17Cm -3About.Resulting devices conduction voltage drop representative value is 2.0V, and representative value fall time of turn off process is 100ns.Zero temperature coefficient point corresponding current density is 60A/cm 2About, be lower than nominal current density and (be generally 150-200A/cm 2), in the device working range, have the voltage positive temperature coefficient.
Embodiment 3: twice, dual energy helium inject the manufacture method of surperficial grid n ditch inner transparent collecting zone IGBT:
Referring to Fig. 3, adopt the present invention to make a kind of n ditch IGBT, withstand voltage 600V with inner transparent collecting zone.The technology manufacturing step that adopts is as follows: (1) is implemented high dose helium in p+ low resistivity substrate (about resistivity 0.01 Ω cm) and is injected, and the energy of helium ion injection for the first time is 200keV, and dosage is 3 * 10 16Cm -2The energy of helium injection for the second time is 400keV, dosage 5 * 10 16Cm -2(2) silicon chip is annealed under argon gas atmosphere, concrete annealing was divided into for two steps: be warmed up to 900 ℃ earlier, kept 20 minutes, be warmed up to 1100 ℃ afterwards again, kept 300 minutes; (3) epitaxial buffer layer and Withstand voltage layer: in the epitaxial process, earlier substrate is thrown erosion, throwing erosion thickness is about 0.5 micron, carries out extension afterwards.Epitaxial buffer layer concentration is divided two-layer, ground floor concentration 1 * 10 18Cm -3, 2 microns of thickness; Second layer concentration 2 * 10 16Cm -3, 5 microns of thickness.The Withstand voltage layer doping content is 7 * 10 13Cm -3, 55 microns of thickness.(4) afterwards technology routinely flow process carry out, finish surperficial MOS earlier and make, surface passivation, thinning back side, metallization etc. finally form the cross-section structure shown in Fig. 2 (f).
About about 0.8 micron of the thickness of the lar nanometric cavities layer that forms by this technology, lar nanometric cavities layer coboundary is about 1.5 microns from the final distance of collector junction, the doping content on collector region surface is 5 * 10 17Cm -3About.Resulting devices conduction voltage drop representative value is about 2V, and representative value fall time of turn off process is 90ns.Zero temperature coefficient point corresponding current density is 80A/cm 2About, be lower than nominal current density and (be generally 150-200A/cm 2), in the device working range, have the voltage positive temperature coefficient.
Embodiment 4:5 time, multipotency helium inject the manufacture method of surperficial grid n ditch inner transparent collecting zone IGBT:
Adopt the present invention to make a kind of n ditch IGBT, withstand voltage 600V with inner transparent collecting zone.The technology manufacturing step that adopts is as follows: (1) is implemented high dose helium in p+ low resistivity substrate (about resistivity 0.01 Ω cm) and is injected, and the energy of helium ion injection for the first time is 20keV, and dosage is 1 * 10 15Cm -2The energy of helium injection for the second time is 200keV, dosage 5 * 10 15Cm -2The energy of helium injection for the third time is 500keV, dosage 2 * 10 16Cm -2The energy of the 4th helium injection is 800keV, dosage 4 * 10 16Cm -2The energy of the 5th helium injection is 1000keV, dosage 5 * 10 16Cm -2(2) silicon chip is annealed under argon gas atmosphere, concrete annealing was divided into for two steps: be warmed up to 900 ℃ earlier, kept 30 minutes, be warmed up to 1100 ℃ afterwards again, kept 300 minutes; (3) epitaxial buffer layer and Withstand voltage layer: in the epitaxial process, earlier substrate is thrown erosion, throwing erosion thickness is about 0.1 micron, carries out extension afterwards.Epitaxial buffer layer concentration is divided two-layer, ground floor concentration 5 * 10 18Cm -3, 0.1 micron of thickness; Second layer concentration 2 * 10 16Cm -3, 5 microns of thickness.The Withstand voltage layer doping content is 7 * 10 13Cm -3, 55 microns of thickness.(4) afterwards technology routinely flow process carry out, finish surperficial MOS earlier and make, surface passivation, thinning back side, metallization etc. finally form the cross-section structure shown in Fig. 2 (f).
About about 3 microns of the thickness of the lar nanometric cavities layer that forms by this technology, lar nanometric cavities layer coboundary is about 0.1 micron from the final distance of collector junction, the doping content on collector region surface is 5 * 10 16Cm -3About.Resulting devices conduction voltage drop representative value is about 2V, and representative value fall time of turn off process is 90ns.Zero temperature coefficient point corresponding current density is 80A/cm 2About, be lower than nominal current density and (be generally 150-200A/cm 2), in the device working range, have the voltage positive temperature coefficient.

Claims (9)

1, slow down towards the manufacture method of layer concentration inner transparent collecting zone igbt, it is characterized in that, this manufacture method is at first carried out following steps:
A) be that the surface of the monocrystalline silicon P+ substrate of 0.02-0.005 Ω cm is carried out the helium ion and injected in resistivity, the dosage that each helium ion injects is 1 * 10 15-1 * 10 17Cm -2, the energy range that helium injects is at 20keV-1000keV,
B) implement low, high annealing, atmosphere low, high annealing is argon gas or vacuum; The process annealing temperature is at 400-900 ℃, and the time is at 30-300 minute, and the temperature of high annealing is at 1000-1150 ℃, time 10-300 minute;
C) epitaxial buffer layer: implement earlier substrate to be thrown erosion before the epitaxy technique, throwing erosion thickness is the 0.1-1 micron; The resilient coating extension adopts varying doping concentration extension, and varying doping concentration buffer layer ground floor is higher-doped concentration, and the doping scope is in 1-50 * 10 17Cm -3, thickness 0.1-5 micron; The second layer is than light dope, concentration 1-10 * 10 16Cm -3, thickness 1-15 micron;
D) extension Withstand voltage layer;
E) finish positive MOS structure and thinning back side and multi-layered electrode technology;
Near the nearly collector junction of device collector region, form an extremely low excess carrier Lifetime Control district, be called the lar nanometric cavities layer with stabilized nano cavity defective; The thickness of lar nanometric cavities layer is the 0.2-3 micron, and between the 0.1-5 micron, the doping content on final collector region surface is 5 * 10 from the final distance of collector junction in lar nanometric cavities layer coboundary 16Cm -3To 5 * 10 18Cm -3
2, manufacture method according to claim 1 is characterized in that: the number of times that helium injects is 1-5 time.
3, manufacture method according to claim 1 is characterized in that: the number of times that helium injects is 1 time, and the energy that helium injects is 100-400keV, and dosage is 1-5 * 10 16Cm -2
4, manufacture method according to claim 1 is characterized in that: the number of times that helium injects is 2 times, and the energy that injects is 100-200keV for the first time, dosage 1-3 * 10 16Cm -2For the second time injecting energy is 200-400keV, dosage 2-6 * 10 16Cm -2
5, manufacture method according to claim 1 is characterized in that: the dosage that helium injects is 2 * 10 16Cm -2, 3 * 10 16Cm -2Or 4 * 10 16Cm -2
6, manufacture method according to claim 1 is characterized in that: the energy that helium injects is 200keV or 300keV.
7, manufacture method according to claim 1 is characterized in that: 700 ℃ of stress relief annealed temperature, 50 minutes time; 1100 ℃ of the temperature of high annealing, 300 minutes time.
8, manufacture method according to claim 1 is characterized in that: implement earlier substrate to be thrown erosion before the epitaxy technique, throwing erosion thickness is 0.5 micron or 0.8 micron.
9, manufacture method according to claim 1 is characterized in that: varying doping concentration buffer layer ground floor higher-doped concentration is 1 * 10 17Cm -3, 5 * 10 17Cm -3Or 1 * 10 18Cm -3, thickness is 1 micron or 2 microns.
CNB2008102405149A 2008-12-19 2008-12-19 Slow down towards the manufacture method of layer concentration inner transparent collecting zone igbt Expired - Fee Related CN100570832C (en)

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