CN100568173C

CN100568173C - Adjustment for multiple micro-controller system task

Info

Publication number: CN100568173C
Application number: CNB2006100307551A
Authority: CN
Inventors: 胡越黎; 冉峰; 丁倩
Original assignee: University of Shanghai for Science and Technology
Current assignee: Shanghai University; University of Shanghai for Science and Technology
Priority date: 2006-09-01
Filing date: 2006-09-01
Publication date: 2009-12-09
Anticipated expiration: 2026-09-01
Also published as: CN1940860A

Abstract

The present invention relates to a kind of micro controller system task call method.This method is based on the MCS-51 system, under the constant prerequisite of order set, several microcontrollers based on the MCS-51 system are connected into a multi-microcontroller system by on-chip bus, and one of them microcontroller is as the direct intended for end consumers of primary processor, and other conduct is from processor.Task call method among the design is integrated in each from the program storage of processor with each task program in application system field, and is super order code with these mission numbers.System is by bus mechanism to calling of these tasks, to sending corresponding super order code from processor accordingly, promptly by finding task program from processor according to specific addressing method, finishes this task automatically by primary processor, realizes task call.The design's super instruction task call method has reduced the requirement to primary processor storage capacity and processing intensity, improves the parallel processing capability of system.This can be applicable to single chip microcontroller based on the MCS-51 instruction system based on the super instruction task call of many MCU system method, also can be applicable to fields such as other multi-microcontroller, microprocessor.

Description

Adjustment for multiple micro-controller system task

Technical field

The present invention relates to the method for the task call of a kind of many MCU (Micro Control Unit) system, can be applicable to the multi-microcontroller system of MCS-51 instruction system, also can be applicable to fields such as other multi-microcontroller, multimicroprocessor.

Background technology

In service at microcontroller, need call a lot of subroutines and subtask.These tasks and master routine might not be to deposit successively in program storage area in order, but by interruption or calling program such as ACALL, orders such as LCALL realize.Traditional task call is the method by pure software; the scene needs protection when using task call; to have information such as program pointer now is pressed onto in the storehouse; after task termination, again the information of pop down is ejected; this method is no problem for better simply relatively system; but for the very huge particular system of data operation quantity; such as digital image processing system; the quantity of information of every two field picture is just very huge; if this system also comprises knowledge-base management; functions such as self study; realizing that these functional programs all are integrated among the single MCU as subroutine call; need very big storage space, and all call and finish and seriously to have influence on the operating rate of system by single processor.If under the prerequisite that does not change order set, adopt many MCU system, these a large amount of tasks and subroutine are distributed to several finish,, and improve the parallel processing capability and the speed of system greatly the requirement that reduces the primary processor storage space from processor.

Summary of the invention

The object of the present invention is to provide a kind of based on adjustment for multiple micro-controller system task.Under the constant prerequisite of order set, each independently task call program of application system is assigned to each from processor, finish the task call work of system jointly by a plurality of microcontrollers, thereby reduce requirement to primary processor storage capacity and processing intensity, so that price is relatively low, widely used MCS-51 framework microcontroller need in the high-end system of large amount of complex algorithm to be applied to.

For achieving the above object, design of the present invention is as follows:

Several microprocessors are connected into MCU system more than by on-chip bus, and one of them microprocessor is as the direct intended for end consumers of primary processor, and other conduct is from processor.Each task call program in application system field is integrated in each from the program storage of processor, and these tasks are numbered, they one by one corresponding to several groups of codes, are called super order code among the present invention.When user program need call these task call programs,, to sending corresponding super order code from processor accordingly, can realize calling of task by finishing this task automatically from processor by primary processor by the communication of the many MCU of bus mechanism realization.And want from processor to finish these particular tasks automatically, just need a kind of effective addressing mode, can find the entry address of task call program according to the super order code that sends, and to the length of each task call program almost without limits.

According to above-mentioned design, the present invention adopts following technical proposals:

The super instruction task call of a kind of multi-microcontroller system method, based on the MCS-51 system, it is characterized in that: under the constant prerequisite of order set, several MCU based on the MCS-51 system are connected into MCU system more than by on-chip bus, one of them MCU is as the direct intended for end consumers of primary processor, and other conduct is from processor; Each task program in application system field is integrated in each from the program storage of processor, and is super order code these mission numbers; To calling of these tasks is by bus mechanism, to sending corresponding super order code from processor accordingly, promptly by finding task program from processor according to specific addressing method, finishes this task automatically by primary processor, realizes task call.

The concrete steps of above-mentioned many MCU system task call method are:

A. add the host processor bus interface module in primary processor, the realization primary processor is connected with bus;

B. from processor, adding from the processor bus interface module, realizing being connected from processor and bus;

C. the program pointer module in the primary processor is changed, realize selected from processor the wait retray function of primary processor when busy; (annotate: the program pointer module among the MCU mainly is responsible for the control of reading of program storage, and its program pointer register PROGA is used to deposit the present procedure address);

D. the operation register module from processor is changed, make that can distinguish current being in from processor carries out during the ordinary instruction still during the processor automatic addressing.The original function of operation register module during carrying out ordinary instruction is with machine code in the instruction and several immediately making a distinction, and gives decoding module and arithmetic logic unit alu respectively and handles.Handle herein when when processor receives super order code, and not according to the ordinary instruction sign indicating number, also promptly decoding is not sent in the entry address that obtains, but replace blank operation, allow this continue to remain on waiting status from processor.

E. the program pointer module from processor is changed, realize from processor according to the function of super order code by the hardware automatic addressing.

Above-mentioned interpolation host processor bus interface module in primary processor, the concrete steps that the realization primary processor is connected with bus are as follows:

A. the method for above-mentioned many MCU of setting control special function register MPCON of system is:

(a) address of determining many MCU system control special function register MPCON is 0CAH, realizes selection and control from processor by reading and writing the control special function register MPCON of many MCU system;

MPCON address: CAH

MPCON.7

-

MUL

TI_ADD

R[2:0]

(b) many MCU system control special function register MPCON is 00H when system reset, the user is by command M OV MPCON, #8xH (x=1～n, n is from number of processors) control this special function register MPCON, its most significant digit is put the principal and subordinate processor communication of the current many MCU of carrying out of 1 expression system; Low three address labels that are used to deposit from processor of this special function register simultaneously, when primary processor will carry out once super instruction task call, at first to send from processor address label need to select to carry out current task from processor;

B., super order code special function register SCOM is set in primary processor:

(a) address of determining the super order code special function register SCOM of many MCU system is 0CBH, and all super order codes realize by read-write special function register SCOM;

SCOM address CBH

SCOM.7

SCOM.6

SCOM.5

SCOM.4

SCOM.3

SCOM.2

SCOM.1

SCOM.0

(b) the super order code special function register of many MCU system SCOM is 00H after system reset, the user is by MOV SCOM, this special function register of #**H instruction control SCOM, after primary processor sends address label, if that chooses can receive an assignment from the processor free time, then primary processor sends to super order code from processor by writing special function register SCOM;

C. in primary processor, be provided with from processor feedback receiving register SREADY:

Invisible from processor feedback receiving register SREADY user, its figure place equals from number of processors, its each be connected respectively to respectively from the idle marker position RHx of processor; Primary processor is accepted register SREADY[x by inquiry from processor feedback] state know corresponding current state from processor;

SREADY[(n-1):0]

D. set retry cancel message DONTSTAY, the state that determines DONTSTAY jointly from the feedback states and the primary processor oneself state of processor, this signal be put when after the several times retry took place, no longer needing retry 1 effective, the expression primary processor breaks away from " retry " state at this moment, does not need OPADD label again again;

E. after super order code special function register SCOM is set, when user program is MOV SCOM, during #**H, give S_COM with the data on the microprocessor internal data line, other time register S_COM is 0;

F. set MCU communication mark signal MPSOC_STROBE, this signal is according to the most significant digit MPCON[7 of many MCU system control special function register MPCON] state variation; If MPCON[7] take place to become 1 saltus step by 0, then master-slave communication takes place in expression, and MPSOC_STROBE is 1, and only keeps a clock period.MPSOC_STROBE is 0 under other situation.

Above-mentioned at the bus interface module that from processor, adds from processor, realize that the concrete steps that are connected with bus from processor are as follows:

A. from the processor bus interface module, setting from processor idle marker READY:

(a) determine address bit 0CCH from processor idle marker special function register READY, from the processor tasks completion status by this register flag;

READY address: CCH

RHx

-

(b) be 80H from processor idle marker special function register READY when the system reset, most significant digit called after RHx (x=1～n of this special function register READY, n is from number of processors), RHx=1 represents corresponding to current free time of processor, wait task; RHx=0 represents corresponding current still carrying out previous task from processor, does not accept new task; RHx is by the hardware zero clearing, software set; The user is by MOV READY, and the instruction of #80H puts 1 with the most significant digit RHx of register READY; Other position of READY is defaulted as 0 temporarily for keeping the position, and it can be used for system in the future expands, and can feed back more information to primary processor from processor; RHx is connected to each position of the SREADY of primary processor, forms from the feedback information of processor to primary processor;

B. setting data input gate-control signal S_COM_ENTRY reaches from the super order code register of processor S_COM_NUM; When data inputs gate-control signal S_COM_ENTRY is 1 effective, super order code on the data bus of permission master-slave communication enters this from processor, promptly the output S_COM of primary processor is read in from processor inside, and give super order code register S_COM_NUM in the processor; S_COM_ENTRY zero clearing behind the entry address of finding the task call program from processor;

C. set internal register RH_tp, it is than 2 clock period of RH signal delay, and purpose is that the RH signal condition is postponed, and judges that to avoid RH signal and other signal changes the risk of competing simultaneously;

D. ought satisfy following three conditions simultaneously: (1) address label and self coupling; (2) RH_tp is 1, promptly should be from the processor free time; (3) the super order code of primary processor is effective with imitating signal;

The S_COM_ENTRY signal was opened and was allowed super order code to enter this moment, and the RHx signal is by the hardware zero clearing simultaneously;

E. set the signal from processor accepting state signal RECEPTEDx (x=1～n, n are from number of processors), this signal will output in the primary processor, characterize that super order code is whether designated to be obtained from processor; If obtained super order code, then corresponding RECEPTEDx is 1, otherwise is 0;

RECEPTED[(n-1):0]

Each accepting state signal RECEPTEDx (x=1～n) output respectively delivers to the accepting state register RECEPTED[(n-1 of primary processor): 0 from processor] everybody.

Above-mentioned to primary processor update routine pointer module, the concrete steps of the retray function that realization is waited for when processor hurries are:

A. set inner mark position NEEDSTAY, put 1 what detect selection when processor is just busy, it is unsuccessful that expression this time sends super instruction task call, and primary processor needs retry;

B. set retry and cancel marking signal DONTSTAY, deliver to the host processor bus interface module as output, whether MPCON is by assignment in control;

C. take place and selectedly when just busy, need do three things when master-slave communication from processor:

(a) the internal register PROGRAM_COUNT_LAST of She Dinging deposits the preceding current pointer position PROGRAM_COUNT of pointer rollback;

(b) current pointer position PROGRAM_COUNT is subtracted 6, makes pointer get back to the section start of super instruction task call;

(c) internal register NEEDSTAY is put 1, and the expression primary processor need be carried out the preliminary work of retry;

D. when NEEDSTAY=1, the expression primary processor may need retry; Continue need to judge whether retry in this case:

(a) when by the accepting state register RECEPTED[(n-1 that transmits from processor): 0] corresponding positions RECEPTED[x]=1, expression is specified and has been received super order code from processor, then

Again give current pointer position PROGRAM_COUNT with the address PROGRAM_COUNT_LAST before the rollback of depositing just now;

The NEEDSTAY zero clearing illustrates that super instruction receives, need not retry;

DONTSTAY puts 1, outputs to the host processor bus interface module, as Rule of judgment, when DONTSTAY is effective, illustrate that this retry is successful, specify and received the super instruction of sending just now from processor, this need not to give the MPCON assignment again, and directly MPCON being composed is 0;

(b) when by the accepting state register RECEPTED[(n-1 that transmits from processor): 0] corresponding positions RECEPTED[x]=0, then explanation is specified just busy from processor, can't receive super order code, then NEEDSTAY cancels after continuing to keep 3 time clock, get back to state 0, restart to send super instruction so that primary processor enters retry state;

E. when NEEDSTAY=0, illustrate to need not to enter retry state other instruction of the normal execution downwards of primary processor.Above-mentioned realization is distinguished current being in from processor and is carried out the method that still receives during the ordinary instruction during the super instruction automatic addressing and be:

Operation register module from processor is changed, after the content of fetch program storer, whether judgement rigidly connects super instruction still during seeking the entry address from processor, being Rule of judgment receives order RHx (x=1～n)=0 from processor, and still whether set up at searching entry address S_COM_ENTERY=1 from processor, if set up, illustrate that the data of reading are not operational codes or count immediately, but the part of task call program entry address, processor changes special state over to, is about to operational code and fills with the 00H blank operation; If above-mentioned condition is false, then normally carry out.

Above-mentioned realization from processor according to super order code by the concrete steps of hardware automatic addressing is:

A. be provided with from the special storage configuration of the program storage of processor:

(a) should leave in successively its program storage from each independently task call program that processor is responsible for, do not have positive connection between them;

(b) respectively open up a shadow zone at each from the program storage area of processor, just the entry address of each task call program is left in this shadow zone successively in compiling, it deposits that sequence number works out is 8 super order code.Respectively can find the entry address of task call program according to super order code automatically from processor;

B. change program pointer module, realize as follows from the task call automatic addressing functional steps of processor from processor:

(a) rest on 0 from processor program pointer under the state of idle waiting, i.e. the program storage section start;

(b) just receiving during super instruction do not find the entry address as yet from processor, promptly when RHx=0 and S_COM_ENTRY=1, doing following calculating:

The position offset ADDR_OFFSET=super order code S_COM_NUM * m of entry address in the shadow zone, wherein m is the shared byte number in each entry address, for example the address space of 16M needs 24 address, then needs to take 3 bytes, m=3;

Position, entry address " ADDR_LOCATION=` shadow zone start address ADDR_START+ADDR_OFFSET ";

Promptly obtain the location address that deposit the entry address of task call program in the shadow zone;

(c) give the program pointer register with address, position, entry address, allow and read the entry address that general procedure equally reads m byte from processor is similar;

(d) though above-mentioned entry address read method with to read ordinary procedure the same, but the content of reading is not decoded or calculating as normal operations sign indicating number or several immediately sending to, because the content that it is read not is operational code or counts immediately, but the entry address of task call.Therefore, give the program pointer register again with the entry address of reading, thereby turn to this entry address to begin the calling program of executing the task as common MCU from processor.

C. will put 1 each task call procedure epilogue user from the Status Flag RHx of processor with instruction, expression should be got back to idle condition again from processor; Program pointer comes back to 0.

Above-mentioned realization finds the specific implementation method of task call program entry address to be from processor according to super order code automatically:

I. set home address register ENTRY_ADDR, its figure place identical with the entry address figure place (for example: the program memory space of 16M needs 24 address, and ENTRY_ADDR just is 24) is used for the entry address of temporary task call program.

Ii. at the internal counter MP_COUNTERx that sets 4 from the program pointer module of processor, x=1...n, n are from the processor number; In the different moment of MP_COUNTERx, do corresponding conversion from the program pointer register of processor, elder generation is according to the entry address location address of the task call program that calculates of " shadow zone start address+super order code * m ", read true entry address again and give home address register ENTRY_ADDR, give program pointer again with the content of ENTRY_ADDR at last.After program pointer was endowed real entry address, MP_COUNTERx was by zero clearing again, changed the normal mode calling program of executing the task over to from processor.

The present invention compared with prior art, have following outstanding substantial characteristics and remarkable advantage: based on many MCU framework of 8051 single-chip microcomputers, carry out a plurality of tasks respectively with a plurality of MCU, remedy the deficiency of MCU performance, carry out the work of high-end system with the low side microprocessor with the advantage of quantity.The primary processor user oriented is carried out certain computing of application system fully with the order set of microcontroller; And the algorithm that certain application is commonly used is integrated in from processor, task call program by professional person's write specialized in this field, the user need not to participate in specialty is required high bottom layer treatment, can be conveniently implemented in the task call that is defined as super instruction among the design, and two common instructions are just carried out in this task call for the user.The method of the super instruction task call of this kind is applicable in the various application of chip multiprocessors system, for those systems that can be partitioned into relatively independent basic operation and often repeat calling program, can significantly reduce the burden of primary processor, the parallel processing capability of raising system, and reduced the requirement of user to the underlying algorithm in certain system applies field.

Description of drawings:

Fig. 1 is many MCU system architecture diagram of an instantiation of the present invention.

Fig. 2 be Fig. 1 example from processor program storage area structure synoptic diagram.

Fig. 3 is the bus interface module structured flowchart of many MCU system of Fig. 1 example.

Fig. 4 is that super instruction task call is from the processor workflow diagram.

Fig. 5 is super instruction task call primary processor workflow diagram.

Fig. 6 carries out super instruction task call primary processor sequential chart smoothly.

Fig. 7 is that retry is carried out super instruction task call primary processor sequential chart.

Fig. 8 is that super instruction task call is from the processor sequential chart.

Table 1 is the super order code mapping table of part.

Table 2 is principal and subordinate processor address label tables.

Embodiment

A preferred embodiment of the present invention is an example with a purpose Vision Builder for Automated Inspection based on many MCU (4 cycle MCS-51 system) framework, realizes the multi-microcontroller system task call by abovementioned steps:

A. make up many MCU of host-guest architecture hardware system based on the MCS-51 system;

B. opening up the shadow zone from the program storage of processor, each independently task call program is deposited in other zone except that the shadow zone, and the shadow zone is deposited the entry address of task call program specially; For each determines corresponding super order code mapping table from processor, corresponding to the task call program from processor respectively;

C. in principal and subordinate processor, set up the master-slave communication that host processor bus interface module and corresponding handshake realize super instruction task call;

D. change the program pointer module of principal and subordinate processor, realize from the automatic addressing of processor and the retray function of execution function and primary processor.

The result who sends super instruction task call is divided into following two kinds of situations:

(a) call smoothly: selected from the processor free time, all are normal in super instruction task call, from the processor automatic addressing and the calling program of executing the task.After primary processor sends super instruction, continue to carry out other instruction downwards.And respectively behind processor comparison address label, that chooses reads in super order code from processor, and oneself state is changed to busy, according to " shadow zone start address+super order code * m " (the 16M program space in this example, the address is 24, therefore m=3) calculate the position, entry address of program, read task call program entry address and put into its program pointer register, thereby should turn to task call program section start to carry out automatically from processor.After carrying out end, be that RHx puts 1 with Status Flag by the instruction of task call program the last item;

See accompanying drawing 4 from the processor workflow diagram.

(b) retry calls: busy this moment in elected from processor, then do not accept next task.This moment primary processor need resend super instruction, up to choose from the processor free time, super instruction sends successfully, primary processor changes following procedure over to;

The primary processor workflow diagram is seen accompanying drawing 5.

E. the operation register module from processor is changed,, the content in the program memory cell of reading is not deciphered as operational code, but allow this carry out blank operation from processor from the processor address period.

The super instruction task call method of many MCU of present embodiment system makes up following many MCU structure (seeing accompanying drawing 1):

Four MCU based on the MCS-51 system constitute many MCU system, and primary processor and three are from processor;

Each MCU has the data-carrier store of 16M program storage and 16M separately, and the address is 24;

4M program storage area unified addressing is arranged, as shared memory in each 16M data storage area;

Present embodiment is taked following from processor program storage area structure (seeing accompanying drawing 2):

A. in the 15M program's memory space from 000000H to 0EFFFFFH, deposit the independently task call program of Vision Builder for Automated Inspection, wait for when calling and carrying out;

B. open up from the 1M space that 0F00000H begins and be the shadow zone, common program is not deposited in this zone, and in the 15M space entry address of each task call program before depositing according to the order of sequence;

The position of every section task call program entry address in the shadow zone is corresponding to super order code, and promptly super order code is similar to a sequence number of changeing in the jumping table, characterizes the entry address of corresponding program.When processor receives super order code, only need to obtain the position, entry address according to " shadow zone start address+super order code * 3 (24 program entry addresses take 3 bytes) ".For example in the accompanying drawing 2, the task call program of task 2 is BMP-YIQ color of image space conversion programs, and this program leaves program storage area from processor in from the place that address 332211H begins, and the super order code of its correspondence is 02H.Then obtaining BMP-YIQ color of image space conversion program according to " 0F00000H+02H * 3=0F00006H " is placed in the shadow zone in three unit of 0F00006H～0F00008H at this program entry address branch from processor.

C. set super command mappings table for each from processor.The user need not to understand the bottom-layer design from those task call programs of processor or algorithm when in use, as long as the mapping table of a task call program and super order code is arranged, accompanying drawing 3 is the super order code mapping table of part (seeing attached list 1).

The step of the handshake of setting the bus interface module of principal and subordinate processor in the present embodiment and relating to is as follows: (seeing accompanying drawing 3)

A. in the special function register that MCU kept (SFR) of the MCS-51 of standard system, define two special function registers, a multiprocessor control register MPCON and a super order code register SCOM:

(a) multiprocessor control special function register MPCON is defined as follows:

MPCON address: CAH

MPCON.7

-

MUL

TI_ADD

R[2:0]

MPCON.7: the zone bit of master-slave communication.Primary processor is effective to put 1 when processor sends super instruction.When its from 0 to 1 saltus step, its state is reflected to the output of host processor bus interface module by host processor bus interface module internal register MPSOC_STROBE, MPSOC_STROBE postpones 2 clock period outputs than MPCON.7, and only keeps a clock period.

MULTI_ADDR: primary processor to send from processor address label select specific for processor,

MULTI_ADDR=001/010/011 has represented respectively from processor 1/2/3 (seeing attached list 2).MPCON is defaulted as 00H, when needing to call a certain a certain task from processor in the user program, then by instruction: MOV MPCON, #8xH, MPCON.7 (and then with MPSOC_STROBE) is put 1, and simultaneously address label MULTI_ADDR is sent on the address bus.

(b) super order code special function register SCOM is defined as follows:

SCOM address: CBH

SCOM.7

SCOM.6

SCOM.5

SCOM.4

SCOM.3

SCOM.2

SCOM.1

SCOM.0

This special function register is deposited super order code, and which task call program the user need call, and only needs to get final product to sending super order code from processor accordingly in conjunction with from the processor address label.Also promptly, the user is by command M OV SCOM, and #**H writes this super order code special function register SCOM, is about to super order code and is put on the data bus.

B. primary processor also is that primary processor mainly contains to the output from processor to send super instruction from processor:

(a) MULTI_ADDR[2:0]: the address label of each processor among many MCU extends to eight processors.Four processors have been connected in this example;

(b) S_COM[7:0]: super order code;

(c) S_COM_RITE: the super order code of primary processor is with imitating signal, outputs in the processor as one of read control signal;

C. mainly contain from the feedback of processor primary processor:

(a)SREADY[2:0]：

RECEPTED[2:0]

As the input of primary processor, by 3 output RH1 from processor, RH2, RH3 are connected and form.

Whether each sign of SREADY is in idle condition from processor accordingly;

(b)RECEPTED[2:0]

SREADY[2:0]

As the input of primary processor, by 3 output RECEPTED1 from processor, RECEPTED2, RECEPTED3 are connected and form.Each of RECEPTED characterizes accordingly whether do not receive super order code owing to be in busy condition from processor after selected.

Program pointer module for primary processor in the present embodiment is changed, and, can realize respectively calling smoothly and call two kinds with retry and call situation successively to sending twice super instruction task call from processor 1 at primary processor, and implementation step is as follows:

A. set MCU communication mark signal input MPSOC_STROBE, this signal is exported by the host processor bus interface module.Most significant digit MPCON[7 according to control special function register MPCON in the host processor bus interface module] take place to become 1 saltus step by 0, then master-slave communication takes place in expression, MPSOC_STROBE is 1 after 2 clock period, and only keeps a clock period.MPSOC_STROBE is 0 under other situation.This signal is input in the program pointer module of primary processor as one of Rule of judgment of master-slave communication;

B. set address label input MULTI_ADDR[2:0], in conjunction with every Rule of judgment as another master-slave communication from the feedback SREADY of processor;

C. set internal retry status signal NEEDSTAY, when primary processor sends super instruction but corresponding from processor when just busy, it is 1 effective that the NEEDSTAY signal is put;

D. export retry cancel message DONTSTAY and send to the host processor bus interface module, the host processor bus interface module is cancelled retry according to this signal.When primary processor is carried out MOV MPCON, during #8xH, judge the DONTSTAY signal in last clock period of this instruction, if DONTSTAY is 1, represent that then primary processor breaks away from from " retry " state, and address label has read in MPCON=0 this moment; When DONTSTAY is 0, then retry does not take place in explanation, and task call is carried out smoothly, and MPCON receives article one command content of super instruction task call, the address acquisition label, and be maintained to primary processor and export after the super order code.Other moment, MPCON was 0;

E. set internal register PROGRAM_COUNTER_LAST, deposit the preceding program pointer of retry;

Whether the state from processor when f. setting Rule of judgment and judge sending super instruction needs retry, and then carries out corresponding operating;

Sequential step when the above-mentioned primary processor of present embodiment is carried out smoothly super instruction task call is as follows: (seeing accompanying drawing 6)

4 clock period were among the MCU of 1 machine cycle in this example, and MOV MPCON, #8xH and MOV SCOM, two instructions of #0CH are used in super instruction task call.The machine code of these two instructions is 75H all, and takies 2 machine cycles.During this period, if SREADY[2:0] certain position be 1, then explanation is in idle condition from processor accordingly, if should call from selected the executing the task of processor, then super instruction task call can normally be carried out.In article one instruction is MOV MPCON, last clock period of #8xH, it is effective that primary processor is write special function register MPCON, in the next clock period, when also being this order fulfillment, special function register MPCON is by assignment, and its last three MULTI_ADDR are selected address label from processor, and after 2 clock period, MPSOC_STROBE is effective for the output of master-slave communication zone bit; Effective in last clock period that second MOV instruction is carried out with imitating signal S_COM_WRITE, it is effective to be that primary processor is write special function register SCOM, in a clock period thereafter, special function register SCOM is endowed super order code, exports by S_COM.Other moment, SCOM was 00H.

It is as follows that the sequential step that retry calls takes place when super instruction task call the above-mentioned primary processor of present embodiment: (seeing accompanying drawing 7)

A. primary processor each system clock rising edge judge the principal and subordinate whether communicate by letter and choose whether idle from processor:

if(MPSoC_STROBE&&((MULTI_ADDR[2:0]＝＝3′b001&&～SREADY[0])||

(MULTI_ADDR[2:0]＝＝3′b010&&～SREADY[1])||

(MULTI_ADDR[2:0]＝＝3′b011&&～SREADY[2])))

If that chooses is just busy from processor, though then obtained super order code in the SCOM register, that chooses can't receive super order code from processor.As shown in accompanying drawing 8, this moment since choose just busy from processor, S_COM_ENTRY is invalid, super order code do not enter choose from processor, but carry out following operation:

(a) current pointer is saved among the PROGRAM_COUNTER_LAST standby;

(b) current pointer is subtracted 6 and come back to transmission MOV MPCON, previous program address place's beginning retry of this instruction of #8xH, because 2 MOV instructions of super instruction task call take the program memory space of 6 bytes altogether, so it is initial to having increased by 6 downwards through pointer at this moment to send address label from super instruction, therefore subtracts 6 herein;

(c) with NEEDSTAY set, primary processor sends the preliminary work that super instruction need be carried out retry under the expression present case;

B. zone bit NEEDSTAY only represent primary processor need carry out retry preparation and and uncertain retry be because, though each processor in this system adopts same system clock source, but they can independently be worked, so their order fulfillment time is different, machine cycle and disunity.Also be primary processor choose may behind above-mentioned condition distinguishing, begin from processor idle, therefore also need another one accepting state sign RECEPTED[2:0], everybody each accepting state signal RECEPTEDx (x=1...3) from processor of connection of RECEPTED exports, and characterizes whether received super instruction from processor:

(a) if RECEPTED[x]=0, the expression choose do not receive really from processor (x+1), then after primary processor begins retry with NEEDSTAY clear 0;

(b) if RECEPTED[x]=1, expression choose from processor (x+1) free time after primary processor is judged, though primary processor best the preparation of retry, need not retry, then from processor:

Just now the program address PROGRAM_COUNTER_LAST that preserved is sent back to the program pointer of primary processor, so that it jumps out " retry " normally executive routine down;

NEEDSTAY clear 0;

DONTSTAY puts 1, outputs to the bus interface module of primary processor.Because primary processor has been carried out a part of MOV MPCON once more before the primary processor pointer reduction of preserving, the #8xH instruction, and primary processor is owing to received super instruction at this moment, state is for busy.Therefore set up once more for fear of declaring the retry condition, when the DONTSTAY signal is effective, no longer gives MPCON in the host processor bus module, but give MPCON, so that principal and subordinate processor can normally be carried out following procedure with 00H with the data that obtain.

Change for program pointer module respectively in the present embodiment, realize receiving super instruction automatic addressing and the function of the calling program of executing the task from processor, implementation step following (seeing accompanying drawing 8) from processor:

A. set input RHx (x=1...3) and S COM ENTRY, these 2 signals all from same from the processor bus interface module, from the program pointer module of processor, be used to control opportunity from the variation of processor program pointer;

B. set input S_COM_NUM, this input is by the super order code from the output of processor bus interface module;

C. set entry address deviation post register ADDR_OFFSET and entry address location register ADDR_LOCATION, deposit the side-play amount of the shadow zone, depositing and the location address that calculate the task program entry address from processor according to super order code respectively;

D. set internal counter MP_COUNTERx (x=1...3),, do different conversion, find the position, entry address and the entry address of task call program respectively from the pointer of processor in the different moment of this internal counter.And this signal outputs to the bus interface module from processor, controls the end that super command reception allows position S_COM_ENTRY;

E. set entry address register ENTRY_ADDR, be used for temporary task call program entry address;

F. receive super instruction from processor and realize that the sequential step of task call is as follows: (seeing accompanying drawing 8) is after determining address label MULTI_ADDR and the coupling of oneself from processor, if this moment, this was just idle from processor, then (1) represents that with idle condition zone bit clear 0 this is current busy from processor, (2) the super order code of simultaneously super order code gate-control signal S_COM_ENTRY being opened on the expression data bus can be read in, so far, will carry out following operation from processor:

(a) the super order code on the data bus is given output S_COM_NUM from the processor bus interface module;

(b) the internal counter MP_COUNTERx (x=1...3) from processor begins counting, so that finish different task from processor constantly according to difference;

(c) according to the super order code that obtains, the side-play amount ADDR_OFFSET that deposit in the shadow zone calculation task calling program entry address;

After said process is finished, proceed following work from processor:

(a) obtain the position of task call program entry address according to " shadow zone start address+ADDR_OFFSET ", i.e. the address AD DR_LOCATION of this position and give program pointer register PROGA;

(b) equal moment of 2,4,6 respectively at internal counter MP_COUNTERx and read content in these 3 program storage unit (PSU)s, and equal moment of 3,5,7 respectively at MP_COUNTERx and be reflected to entry address register ENTRY_ADDR_H, ENTRY_ADDR_M and ENTRY_ADDR_L;

(c) equal moment of 11 at MP_COUNTERx, by

PROGA＜＝{ENTRANCE_ADDR_H，ENTRANCE_ADDR_M，ENIRANCE_ADDR_L}；

Give program pointer register PROGA with the high, medium and low position of entry address register, so far, turn to the entry address of task call program to begin to execute the task automatically from processor;

(d) behind the acquisition entry address, MP_COUNTERx resets to 0 with internal counter, exports to corresponding to processor bus interface module controls S_COM_ENTRY zero clearing.

When this section task call EOP (end of program), the task call program is passed through MOV READY, #80H, and RHx puts 1 again with its most significant digit state flag bit, and idle condition is got back in expression at this moment.

In this example the operation register module from processor is changed, realize from processor distinguish current be in to carry out still receive during the ordinary instruction after the super order code during the automatic addressing, its implementation is as follows:

After the content of fetch program storer, judge from processor whether rigidly connect during super instruction is in automatic addressing, promptly Rule of judgment RHx (x=1...3)=0 (receives order) ﹠amp from processor; Whether S_COM_ENTERY=1 (still seeking the entry address from processor) sets up, if set up, illustrate that the data of reading are not operational codes or count immediately, but the part of task call program entry address, processor changes special state over to, promptly the entry address of reading is not used as operational code decoding, and operational code is filled with the 00H blank operation; If above-mentioned condition is false, then the MCU as common MCS-51 series normally carries out decoded operation.

Claims

1. adjustment for multiple micro-controller system task, based on the MCS-51 system, it is characterized in that: under the constant prerequisite of order set, several MCU based on the MCS-51 system are connected into MCU system more than by on-chip bus, one of them MCU is as the direct intended for end consumers of primary processor, and other conduct is from processor; Each task program in application system field is integrated in each from the program storage of processor, and is super order code these mission numbers; To calling of these tasks is by bus mechanism, to sending corresponding super order code from processor accordingly, promptly by finding task program from processor according to specific addressing method, finishes this task automatically by primary processor, realizes task call.

2. adjustment for multiple micro-controller system task according to claim 1 is characterized in that concrete steps are:

C. the program pointer module in the primary processor is changed, realize selected from processor the wait retray function of primary processor when busy;

D. the operation register module from processor is changed, make from processor can distinguish current be in carry out still receive super instruction automatic addressing during the ordinary instruction during, the original function of operation register module during carrying out ordinary instruction is with machine code in the instruction and several immediately making a distinction, and gives decoding module and arithmetic logic unit alu respectively and handles; Handle herein when when processor receives super order code, and not according to the ordinary instruction sign indicating number, also promptly decoding is not sent in the entry address that obtains, but replace blank operation, allow this continue to remain on waiting status from processor;

3. adjustment for multiple micro-controller system task according to claim 2 is characterized in that adding the host processor bus interface module among the described step a in primary processor, realizes that the concrete steps that primary processor is connected with bus are:

A., the control special function register MPCON of many MCU system is set in primary processor:

MPCON address: CAH

MPCON.7 ?- ?- ?- ?- MUI TI_ADD R[2:0]

(b) many MCU system control special function register MPCON is 00H when system reset, the user is by command M OV MPCON, #8xH, x=1～n, n is from number of processors, control this special function register MPCON, its most significant digit is put the principal and subordinate processor communication of the current many MCU of carrying out of 1 expression system; Low three address labels that are used to deposit from processor of this special function register simultaneously, when primary processor will carry out once super instruction task call, at first to send from processor address label need to select to carry out current task from processor;

SCOM address: CBH

SCOM.7 SCOM.6 SCOM.5 SCOM.4 SCOM.3 SCOM.2 SCOM.1 SCOM.7

SREADY[(n-1):0]

F. set MCU communication mark signal MPSOC_STROBE, this signal is according to the most significant digit MPCON[7 of many MCU system control special function register MPCON] state variation; If MPCON[7] take place to become 1 saltus step by 0, then master-slave communication takes place in expression, and MPSOC_STROBE is 1, and only keeps a clock period; MPSOC_STROBE is 0 under other situation.

4. adjustment for multiple micro-controller system task according to claim 2 is characterized in that adding bus interface module among the described step b from processor, realizes that the concrete steps that are connected with bus from processor are:

A. from the processor bus interface module, be provided with from processor idle marker READY:

READY address: CCH

RHx ?- ?- ?- ?- ?- ?- ?-

(b) be 80H from processor idle marker special function register READY when the system reset, the most significant digit called after RHx of this special function register READY, x=1～n, n are from number of processors, RHx=1 represents corresponding to current free time of processor, wait task; RHx=0 represents corresponding current still carrying out previous task from processor, does not accept new task; RHx is by the hardware zero clearing, software set; The user is by MOV READY, and the instruction of #80H puts 1 with the most significant digit RHx of register READY; Other position of READY is defaulted as 0 temporarily for keeping the position, and it can be used for system in the future expands, and can feed back more information to primary processor from processor; RHx is connected to each position of the SREADY of primary processor, forms from the feedback information of processor to primary processor;

E. set the signal from processor accepting state signal RECEPTEDx, x=1～n, n are from number of processors, and this signal will output in the primary processor, characterize that super order code is whether designated to be obtained from processor; If obtained super order code, then corresponding RECEPTEDx is 1, otherwise is 0;

RECEPTED[(n-1):0]

Each is from the accepting state signal RECEPTEDx of processor, and x=1～n exports respectively and delivers to main the processing

The accepting state register RECEPTED[(n-1 of device): 0] every.

5. adjustment for multiple micro-controller system task according to claim 2 is characterized in that among the described step c program pointer module in the primary processor being changed, and the realization primary processor is waiting for that when processor does the concrete steps of retray function are:

(a). when by the accepting state register RECEPTED[(n-1 that transmits from processor): 0] corresponding positions RECEPTED[x]=1, expression is specified and has been received super order code from processor, then

E. when NEEDSTAY=0, illustrate to need not to enter retry state other instruction of the normal execution downwards of primary processor.

6. adjustment for multiple micro-controller system task according to claim 2 is characterized in that in the described steps d realizing that distinguishing current being in from processor carries out the method that still receives during the ordinary instruction during the super instruction automatic addressing and be:

7. adjustment for multiple micro-controller system task according to claim 2 is characterized in that in the described step e from processor according to super order code by the method for hardware automatic addressing being:

(b) respectively open up a shadow zone at each from the program storage area of processor, just the entry address of each task call program is left in this shadow zone successively in compiling, it deposits that sequence number works out is 8 super order code; Respectively find the entry address of task call program automatically according to super order code from processor;

The position offset ADDR_OFFSET=super order code S_COM_NUM * m of entry address in the shadow zone, wherein m is the shared byte number in each entry address, needs 24 address for the address space of 16M, then needs to take 3 bytes, m=3;

(d) though above-mentioned entry address read method with to read ordinary procedure the same, but the content of reading is not decoded or calculating as normal operations sign indicating number or several immediately sending to, because the content that it is read not is operational code or counts immediately, but the entry address of task call; Therefore, give the program pointer register again with the entry address of reading, thereby turn to this entry address to begin the calling program of executing the task as common MCU from processor;

C. will put 1 each task call procedure epilogue user from the idle condition sign RHx of processor with an instruction, expression should be got back to idle condition again from processor; Program pointer comes back to 0.

8. adjustment for multiple micro-controller system task according to claim 7 is characterized in that finding the specific implementation method of task call program entry address to be from processor automatically according to super order code in the described steps A (b):

I. set internal register ENTRY_ADDR, be used for the entry address of temporary task program, its figure place is identical with the entry address figure place;

Ii. at the internal counter MP_COUNTERx that from the PC pointer module of processor, sets 4 respectively, x=1 ... n, n are from number of processors; The different moment at MP_COUNTERx are done different things; After obtaining super order code from processor, calculate the position, entry address through " shadow zone start address+super order code * m ", this moment, MP_COUNTERx began counting, began the fetch program memory block content of m unit after the address of this position, entry address at this moment from processor; Because under the normal condition, per 2 clock period are read unit among the rom, therefore at MP_COUNTERx=2, and 4,6 ... the time read content among the rom respectively, the number of times that reads equals the shared byte number in entry address; And MP_COUNTERx=5,7,9 ... the moment respectively each unit of entry address is put into the high, normal, basic byte of entry address register ENTRY_ADDR; After all having read the entry address, give PC pointer register PROGA with the value of ENTRY_ADDR; And after PROGA was endowed real entry address, MP_COUNTERx was by zero setting again, changed the normal mode program of executing the task over to from processor.