CN100563110C - A kind of forward error compensation bearing calibration and device of pipelined analog-digital converter - Google Patents

Abstract

The present invention relates to a kind of forward error compensation bearing calibration and device of pipelined analog-digital converter, it is characterized in that: the principle of forward error compensation bearing calibration is, sampling hold circuit is in maintenance during the stage in the group pipelining-stage, and the voltage error of output point can be reflected on the input virtual earth point of its operational amplifier; The sub-pipelining-stage operational amplifier of higher level input virtual earth point voltage error amount keeps by a forward error compensation circuit and transmits, and compares calculating with the input voltage of subordinate sub-pipelining-stage, makes the output voltage error of the sub-pipelining-stage of higher level obtain fine compensation; Sampling hold circuit and the pipelining-stage of realizing forward error compensation use same clock signal.The present invention adopts the pipeline system ADC of forward error compensation method to be aided with technology such as multichannel, time overlapping, can reduce the pressure of base band in the communication control processor system, equally also can solve the bottleneck of software and radio technique on ADC resolution and speed in the military equipment.

Description

A kind of forward error compensation bearing calibration and device of pipelined analog-digital converter

Technical field

The present invention relates to a kind of error calibration method of pipelined analog-digital converter, particularly about a kind of forward error compensation bearing calibration and device of pipelined analog-digital converter.

Background technology

Along with electronic technology and development of computer, utilize the situation of digital signaling system Analog signals to become more and more general.But in real life, most signal all is to exist with the form of analog quantity.Real world need become digital signal by analog to digital converter (ADC) by the analog quantity of transducer signals converted form, but just the input digit system handles and controls.Therefore, the interface circuit ADC that analog quantity is converted into digital quantity is the bridge of analog signal and digital signal, equally also is the emphasis and the bottleneck place of electronic technology development.In order to adapt to computer, the developing rapidly of communication and multimedia technology digitlization process, no matter ADC is in framework, technology, or all produced huge variation on the performance requirement, high-resolution, at a high speed, low-power consumption become inevitable development trend.

The ADC type of current popular has traditional walking abreast, successive approximation, and integral form also has flourish in recent years ∑-Δ type and pipeline system ADC.Parallel ADC speed is fast, but because the restriction of technology and structure is difficult to accomplish high-resolution.Successive approximation, integral form and ∑-Δ type ADC precision height, but its transfer principle has limited their conversion speed.Wherein pipeline system is the most promising ADC framework, and the characteristics of its high speed, high resolution meet current application demand very much.

As shown in Figure 1, pipeline system analog-digital converter (pipeline ADC) is a very common framework during a kind of analog-to-digital conversion in high-resolution, high speed is used.Pipeline system ADC generally is made up of the sub-pipelining-stage of a plurality of series connection, and each level is differentiated the B position.In each level, analog input at first is sampled maintenance.Its value is quantified as the B position by a sub-adc converter (sub-ADC) then, as shown in Figure 2.Quantized value deducts from original input signal to produce surplus by a digital to analog converter (DAC), and this surplus multiply by 2 by a surplus amplifier ^BTo return to original full amplitude of oscillation range, output valve is sent into next pipelining-stage in the next clock cycle and is further quantized.Each pipelining-stage has not obtained high-throughput under two-phase does not overlap clock control, can obtain a conversion value in each clock cycle.Sampling rate just is subjected to the influence of single-stage switching rate.

Pipeline system ADC has considerable advantage compared to other framework, simply increases pipelining-stage progression and just can improve resolution, just can achieve the goal as long as consume more hardware and area overhead.And owing to adopt figure adjustment (Digital Correction) technology, the required precision of sub-ADC is greatly diminished.But, because of it needs an accurate sampling hold circuit to obtain good maintenance analog input level, so just to the operational amplifier demands for higher performance.For example, one 12 bit resolution, the operational amplifier that uses in the pipeline ADC of 100MHz sample frequency needs gain A＞90dB usually, gain bandwidth product GBW＞500MHz.This class high performance operational amplifier has limited throughput, and has increased the power consumption expense greatly.Therefore, the deficiency of operational amplifier gain and GBW has become the main bottleneck of restriction pipeline ADC performance.Existing error calibration method at this problem generally all adopts back level pipelining-stage to calculate the error of prime pipelining-stage and carry out feedback compensation.Because these class methods fundamentally do not solve the problem of power consumption and speed, so application prospect is limited.

Summary of the invention

At the problems referred to above, the purpose of this invention is to provide a kind of forward error compensation bearing calibration and device of pipelined analog-digital converter.

For achieving the above object, the present invention takes following technical scheme: a kind of forward error compensation bearing calibration of pipelined analog-digital converter comprises following content:

(1) setting comprises the unit that several are made up of three operational amplifiers, described three operational amplifiers are respectively the sub-pipelining-stage of higher level, the sub-pipelining-stage of subordinate, forward error compensation network component, and the clock switch CLKS and the CLKH that are not overlapped by two-phase control.

(2) sampling hold circuit is in maintenance during the stage in the group pipelining-stage, and the voltage error of output point can be reflected on the input virtual earth point of its operational amplifier; The sub-pipelining-stage operational amplifier of higher level input virtual earth point voltage error amount keeps by a forward error compensation circuit and transmits, and compares calculating with the input voltage of subordinate sub-pipelining-stage, makes the output voltage error of the sub-pipelining-stage of higher level obtain fine compensation;

(3) realize that the sampling hold circuit of forward error compensation and pipelining-stage use same clock signal.

When CLKS was high level, the sub-pipelining-stage of higher level was sampled at described forward error compensation means for correcting, and the sub-pipelining-stage of subordinate keeps, and the forward error compensation circuit keeps; When CLKH was high level, the sub-pipelining-stage of higher level entered the maintenance stage, forward error compensation circuit sampling error signal.

Be in maintenance during the stage at described sub-higher level's pipelining-stage, the voltage VX computational methods of its input virtual earth point x are as follows: wherein

C _F: the maintenance electric capacity of sub-pipelining-stage

C _S: the sampling capacitance of sub-pipelining-stage

C _EF: the maintenance electric capacity of forward error compensation circuit

C _ES: the sampling capacitance of forward error compensation circuit

VIN: the input voltage of the sub-pipelining-stage of higher level

A: the gain of operational amplifier

Obtain $\mathrm{VX}=\frac{(C_F+C_S)\×\mathrm{VIN}}{C_F\×(A+1)+C_S+C_{\mathrm{EF}}+C_{\mathrm{ES}}},$ Feedback factor with main circuit $f=\frac{C_F}{C_S+C_F}$ The substitution following formula gets

$\mathrm{VX}=\frac{\mathrm{VIN}}{\mathrm{Af}+1+(C_{\mathrm{EF}}+C_{\mathrm{ES}})/(C_F+C_S)}.$

In the described virtual earth point voltage VX computing formula,, get C for 1 or 1.5 pipelining-stages _S=C _F=C, promptly feedback factor is 0.5, can obtain:

$\mathrm{VX}=\frac{2\×\mathrm{VIN}}{A+2+(C_{\mathrm{EF}}+C_{\mathrm{ES}})/C}.$

In order to overcome the error that the forward error compensation circuit produces, can adopt and adjust C _EF, C _ESThe method of proportionality coefficient makes the output voltage error that the output valve of forward error compensation circuit can the sub-pipelining-stage of fine compensation higher level; Described forward error compensation circuit C _EF, C _ESProportionality coefficient can be by feedback factor $f=\frac{C_{\mathrm{EF}}}{C_{\mathrm{ES}}+C_{\mathrm{EF}}}=\frac{1}{4}-\frac{1}{A}$ Try to achieve, promptly

$\frac{C_{\mathrm{EF}}}{C_{\mathrm{ES}}}=\frac{A-4}{3A+4}.$

A kind of device of realizing as the forward error compensation bearing calibration of the above-described pipelined analog-digital converter of claim, it is characterized in that: comprise the unit that several are made up of three operational amplifiers, be the sub-pipelining-stage of higher level, the sub-pipelining-stage of subordinate, forward error compensation circuit, the clock switch CLKS and the CLKH that are not overlapped by two-phase control; The virtual earth point of the sub-pipelining-stage of higher level inserts the forward error compensation circuit, and the output of forward error compensation circuit inserts the sub-pipelining-stage of subordinate.

Described operational amplifier can use the fully differential operational amplifier, also can use single-ended operational amplifier.

The present invention is owing to take above technical scheme, and it has the following advantages: 1, the present invention is owing to adopt the forward error recovery method, and feasible low gaining operating amplifier with simple architecture makes up pipeline system ADC becomes possibility; 2, the present invention is owing to use the low gaining operating amplifier of simple architecture, and significantly reducing influences the limit of system bandwidth number, compares the multipole dot system that uses high gain operational amplifier, is more prone to expand gain bandwidth product; 3, the present invention is keeping promoting the sample frequency of pipeline system ADC significantly on the high-resolution basis owing to adopt above method; 4, the present invention adopts the pipeline system ADC of forward error compensation method to be aided with technology such as multichannel, time overlapping, can reduce the pressure of base band in the communication control processor system, equally also can solve the bottleneck of software and radio technique on ADC resolution and speed in the military equipment.

Description of drawings

Fig. 1 is the theory diagram of conventional pipelined analog-digital converter

Fig. 2 is the sub-adc converter schematic diagram of conventional pipelined analog-digital converter

Fig. 3 is the sample phase circuit diagram of pipelined analog-digital converter sampling hold circuit

Fig. 4 is the maintenance stage circuit diagram of pipelined analog-digital converter sampling hold circuit

Fig. 5 is a forward error compensation circuit diagram of the present invention

Fig. 6 is clock signal figure

Embodiment

By the following examples and in conjunction with the accompanying drawings the present invention is described in detail.

Shown in Fig. 3,4, the present invention proposes a kind of new error calibration method---forward error compensation at pipeline ADC, basic principle is as follows: when sampling hold circuit in the pipelining-stage is in maintenance during the stage, the voltage error of its output point 5 can be reflected on the input virtual earth point 6 of operational amplifier 4.

Following method can be similar to the magnitude of voltage of deriving virtual earth point 6.In sample phase, the total electrical charge of input is:

Q _s＝(C _F+C _S)×VIN

C _F: the maintenance electric capacity of sub-pipelining-stage

C _S: the sampling capacitance of sub-pipelining-stage

In the maintenance stage, the total electrical charge of input is:

Q _h＝C _F(A×VX+VX)+C _SVX

For 1 or 1.5 desirable C of pipelining-stage _S=C _F, the magnitude of voltage that can be obtained virtual earth point by charge conservation is:

$\mathrm{VX}=\frac{2\×\mathrm{VIN}}{A+2}$

And the magnitude of voltage of output point 5 is:

$\mathrm{VOUT}=\frac{2\×A\×\mathrm{VIN}}{A+2}$

Therefore

VOUT+2×VX＝2×VIN

Identical with surplus output level value under the ideal conditions.

As shown in Figure 5, be the physical circuit realization of forward error compensation method.Clock CLKS and CLKH control that pipelining-stage 7 and pipelining-stage 8 are not overlapped by two-phase, as shown in Figure 6.When CLKS is high level, pipelining-stage 7 samplings, pipelining-stage 8 keeps, and forward error compensation circuit 9 keeps; Pipelining-stage 7 enters the maintenance stage when CLKH is high level, forward error compensation circuit 9 sampling error signals.Since operational amplifier finite gain thereby cause surplus output 10 that certain error is arranged, and this error is reflected on the virtual earth point 11 of operational amplifier.The sampling of 11 error amount is kept and the output voltage of delivering to next stage and output 10 calculates with forward error compensation circuit 9, compensate output voltage error.The error level value of derivation virtual earth point 11 this moment:

The total electrical charge in maintenance stage

Q _h′＝C _F(A×VX+VX)+C _SVX+(C _EF+C _ES)VX

C _EF: the maintenance electric capacity of forward error compensation circuit

C _ES: the sampling capacitance of forward error compensation circuit

Can obtain by charge conservation:

$\mathrm{VX}=\frac{(C_F+C_S)\×\mathrm{VIN}}{C_F\×(A+1)+C_S+C_{\mathrm{EF}}{+C}_{\mathrm{ES}}}$

Feedback factor with main circuit $f=\frac{C_F}{C_S+C_F}$ The substitution following formula can obtain:

$\mathrm{VX}=\frac{\mathrm{VIN}}{\mathrm{Af}+1+(C_{\mathrm{EF}}+C_{\mathrm{ES}})/(C_F+C_S)}$

For 1 or 1.5 pipelining-stages, get C _S=C _F=C, promptly feedback factor is 0.5, can obtain virtual earth and put 11 voltages:

$\mathrm{VX}=\frac{2\×\mathrm{VIN}}{A+2+(C_{\mathrm{EF}}+C_{\mathrm{ES}})/C}$

Because A is very big, C _EFAnd C _ESThe error of being brought almost can be ignored, therefore increase by one to 11 sampling hold circuit the operation for former streamline exerts an influence hardly.

Because forward error compensation circuit 9 also can cause error, can adjust sampling capacitance 12 and the ratio that keeps electric capacity 13 in the circuit 9, make output valve 14 can compensate 10 error accurately.Proportionality coefficient is derived as follows:

Forward error compensation circuit 9 is approximately in its sample phase total electrical charge:

$Q_{\mathrm{SE}}=\frac{\mathrm{VIN}\×(C_{\mathrm{EF}}+C_{\mathrm{ES}})}{\mathrm{Af}+1}$

Output 14 is to compensate by switched-capacitor circuit when pipelining-stage 8 is in the maintenance stage, for the maintenance output voltage OUTPUT_STAGE2 that makes streamline 8 accurate, must consider the streamline 8 surplus Amplifier Gain factors, with 1/1.5 pipelining-stages is example, and this gain factor gets 2.Therefore forward error compensation circuit 9 keeps output voltage values to be:

$V_{\mathrm{ERROR}\_\mathrm{OUT}}=\frac{4\×\mathrm{VIN}}{\mathrm{Af}+1}$

Then in the maintenance stage, the total electrical charge value is:

$Q_{\mathrm{HE}}=\frac{4\×\mathrm{VIN}}{\mathrm{Af}+1}(C_{\mathrm{EF}}+\frac{C_{\mathrm{EF}}}{A}+\frac{C_{\mathrm{ES}}}{A})$

Keep principle by electric charge, Q is arranged _SE=Q _HE, obtain the feedback factor of error stream waterline 9:

$f=\frac{C_{\mathrm{EF}}}{C_{\mathrm{ES}}+C_{\mathrm{EF}}}=\frac{1}{4}-\frac{1}{A}$

Suppose to be 50dB in the operational amplifier gain, then this feedback factor is about 0.247, can calculate proportionality coefficient thus:

$\frac{C_{\mathrm{EF}}}{C_{\mathrm{ES}}}=\frac{A-4}{3A+4}.$

Because pipeline system ADC generally adopts 1.5/grade figure adjustment algorithm, therefore make sub-ADC can tolerate bigger error, and the error of each grade is just owing to the finite gain of operational amplifier at the corresponding levels causes, be not delivered to next stage, its value can not influence the correct output result of streamline in a controlled scope.Operational amplifier can use the fully differential operational amplifier, also can use single-ended operational amplifier, perhaps existing other operational amplifier.The pipeline system ADC of this class high speed, high resolution has wide application background, and in the communication control processor system, employing high-resolution pipeline ADC at a high speed can reduce the pressure for base band.Equally, the bottleneck of the software and radio technique of one of research focus of military equipment just is resolution and the underspeed of ADC.Adopt the pipeline ADC of the method for forward error compensation, be aided with multichannel, technology such as time overlapping can make sample frequency reach GHz.

Claims (9)

1, a kind of forward error compensation bearing calibration of pipelined analog-digital converter comprises following content:

(1) setting comprises the unit that several are made up of three operational amplifiers, described three operational amplifiers are respectively the sub-pipelining-stage of higher level, the sub-pipelining-stage of subordinate, forward error compensation network component, and the clock switch CLKS and the CLKH that are not overlapped by two-phase control;

(2) sampling hold circuit is in maintenance during the stage in the group pipelining-stage, and the voltage error of output point can be reflected on the input virtual earth point of its operational amplifier; The sub-pipelining-stage operational amplifier of higher level input virtual earth point voltage error amount keeps by a forward error compensation circuit and transmits, and compares calculating with the input voltage of subordinate sub-pipelining-stage, makes the output voltage error of the sub-pipelining-stage of higher level obtain fine compensation;

(3) realize that the sampling hold circuit of forward error compensation and pipelining-stage use same clock signal.

2, the forward error compensation bearing calibration of a kind of pipelined analog-digital converter as claimed in claim 1, it is characterized in that: described forward error compensation means for correcting is when CLKS is high level, the sub-pipelining-stage sampling of higher level, the sub-pipelining-stage of subordinate keeps, and the forward error compensation circuit keeps; When CLKH was high level, the sub-pipelining-stage of higher level entered the maintenance stage, forward error compensation circuit sampling error signal.

3, the forward error compensation bearing calibration of a kind of pipelined analog-digital converter as claimed in claim 1 is characterized in that: described sub-higher level's pipelining-stage is in maintenance during the stage, and the voltage VX computational methods of its input virtual earth point x are as follows:

Wherein

C _F: the maintenance electric capacity of sub-pipelining-stage

C _S: the sampling capacitance of sub-pipelining-stage

C _EF: the maintenance electric capacity of forward error compensation circuit

C _ES: the sampling capacitance of forward error compensation circuit

VIN: the input voltage of the sub-pipelining-stage of higher level

A: the gain of operational amplifier

Obtain $\mathrm{VX}=\frac{(C_F+C_S)\×\mathrm{VIN}}{C_F\×(A+1)+C_S+C_{\mathrm{EF}}+C_{\mathrm{ES}}},$ Feedback factor with main circuit $f=\frac{C_F}{C_S+C_F}$ The substitution following formula gets $\mathrm{VX}=\frac{\mathrm{VIN}}{\mathrm{Af}+1+(C_{\mathrm{EF}}+C_{\mathrm{ES}})/(C_F+C_S)}.$

4, the forward error compensation bearing calibration of a kind of pipelined analog-digital converter as claimed in claim 2 is characterized in that: the sub-pipelining-stage of described higher level is in maintenance during the stage, and the voltage VX computational methods of its input virtual earth point x are as follows:

Wherein

C _F: the maintenance electric capacity of sub-pipelining-stage

C _S: the sampling capacitance of sub-pipelining-stage

C _EF: the maintenance electric capacity of forward error compensation circuit

C _ES: the sampling capacitance of forward error compensation circuit

VIN: the input voltage of the sub-pipelining-stage of higher level

A: the gain of operational amplifier

Obtain $\mathrm{VX}=\frac{(C_F+C_S)\×\mathrm{VIN}}{C_F\×(A+1)+C_S+C_{\mathrm{EF}}+C_{\mathrm{ES}}},$ Feedback factor with main circuit $f=\frac{C_F}{C_S+C_F}$ The substitution following formula gets $\mathrm{VX}=\frac{\mathrm{VIN}}{\mathrm{Af}+1+(C_{\mathrm{EF}}+C_{\mathrm{ES}})/(C_F+C_S)}.$

5, as the forward error compensation bearing calibration of claim 1 or 2 or 3 or 4 described a kind of pipelined analog-digital converters, it is characterized in that: in the described virtual earth point voltage VX computing formula,, get C for 1 or 1.5 pipelining-stages _S=C _F=C, promptly feedback factor is 0.5, can obtain:

$\mathrm{VX}=\frac{2\×\mathrm{VIN}}{A+2+(C_{\mathrm{EF}}+C_{\mathrm{ES}})/C}.$

6, as the forward error compensation bearing calibration of claim 1 or 2 or 3 or 4 described a kind of pipelined analog-digital converters, it is characterized in that:, can adopt and adjust C in order to overcome the error that the forward error compensation circuit produces _EF, C _ESThe method of proportionality coefficient makes the output voltage error that the output valve of forward error compensation circuit can the sub-pipelining-stage of fine compensation higher level; Described forward error compensation circuit C _EF, C _ESProportionality coefficient can be by feedback factor $f=\frac{C_{\mathrm{EF}}}{C_{\mathrm{ES}}+C_{\mathrm{EF}}}=\frac{1}{4}-\frac{1}{A}$ Try to achieve, promptly

$\frac{C_{\mathrm{EF}}}{C_{\mathrm{ES}}}=\frac{A-4}{3A+4}.$

7, the forward error compensation bearing calibration of a kind of pipelined analog-digital converter as claimed in claim 5 is characterized in that: in order to overcome the error that the forward error compensation circuit produces, can adopt and adjust C _EF, C _ESThe method of proportionality coefficient makes the output voltage error that the output valve of forward error compensation circuit can the sub-pipelining-stage of fine compensation higher level; Described forward error compensation circuit C _EF, C _ESProportionality coefficient can be by feedback factor $f=\frac{C_{\mathrm{EF}}}{C_{\mathrm{ES}}+C_{\mathrm{EF}}}=\frac{1}{4}-\frac{1}{A}$ Try to achieve, promptly

$\frac{C_{\mathrm{EF}}}{C_{\mathrm{ES}}}=\frac{A-4}{3A+4}.$

8, a kind of device of realizing as the forward error compensation bearing calibration of any described pipelined analog-digital converter in the claim 1～7, it is characterized in that: comprise the unit that several are made up of three operational amplifiers, be the sub-pipelining-stage of higher level, the sub-pipelining-stage of subordinate, forward error compensation circuit, the clock switch CLKS and the CLKH that are not overlapped by two-phase control; The virtual earth point of the sub-pipelining-stage of higher level inserts the forward error compensation circuit, and the output of forward error compensation circuit inserts the sub-pipelining-stage of subordinate.

9, the forward error compensation means for correcting of a kind of pipelined analog-digital converter as claimed in claim 8, it is characterized in that: described operational amplifier can use the fully differential operational amplifier, also can use single-ended operational amplifier.

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