CN100561725C - The direct electric connection flip chip packaging structure of semiconductor chip - Google Patents
The direct electric connection flip chip packaging structure of semiconductor chip Download PDFInfo
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- CN100561725C CN100561725C CNB2005101233974A CN200510123397A CN100561725C CN 100561725 C CN100561725 C CN 100561725C CN B2005101233974 A CNB2005101233974 A CN B2005101233974A CN 200510123397 A CN200510123397 A CN 200510123397A CN 100561725 C CN100561725 C CN 100561725C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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Abstract
The direct electric connection flip chip packaging structure of semiconductor chip of the present invention comprises: at least one dielectric layer; At least one semiconductor chip, and this semiconductor chip active face is formed with electric connection pad, and connect with its active face and to put on this dielectric layer; And at least one line layer, be formed on this dielectric layer for connecing a side of putting semiconductor chip, and this line layer is electrically connected to the electric connection pad on this semiconductor chip by a plurality of conductive electrodes that are formed in this dielectric layer; The present invention has integrated connecing of semiconductor chip and chip bearing member and has put and electric connection structure, the integration that simplify semiconductor industry processing step, reduces cost and simplify interface, increase the flexibility that structure space utilizes simultaneously, promote the electrical functionality of semiconductor device, in the heat dissipation that promotes chip, make this semiconductor package have more slimming.
Description
Technical field
The invention relates to a kind of direct electric connection flip chip packaging structure of semiconductor chip, particularly about a kind of direct electric connection flip chip packaging structure of slimming semiconductor chip of integrating semiconductor chip.
Background technology
Flourish along with electronic industry, electronic product also progresses into multi-functional, high performance R﹠D direction.For satisfying the encapsulation requirement of semiconductor package part high integration (Integration) and microminiaturized (Miniaturization), the circuit board (Circuit board) that provides a plurality of active, passive components and circuit to connect also develops into multi-layer sheet (Multi-layer bord) by lamina gradually, under limited space, enlarge available wiring area on the circuit board by interlayer interconnection technique (Interlayer connection), cooperate highdensity integrated circuit (Integrated circuit) demand.
The conducting wire number of plies and component density raising because of circuit board, the heat that cooperates the operation of highly integrated (Integration) semiconductor chip to produce also can significantly increase, these heats seriously threaten the chip life-span if untimely eliminating can cause semiconductor package part overheated.At present, spherical grid array type (BGA) structure is more reaching the demand that can't meet electrical and thermal diffusivity more than the high frequency 5GHz more than the multiway number (1500pin).
In view of this; industry develops and the spherical matrix of chip upside-down mounting type (Flip Chip Ball GridArray; FCBGA) encapsulating structure; the U.S. as shown in Figure 1 announces the 6th; 774; prior art in No. 498 patents; it provides the semiconductor chip 10 (die) that has on the acting surface (active surface) as the chip mat 101 (die pad) of signal input and output; on this chip mat 101, be formed with conductive projection 11 (bump) and be electrically connected to the weld pad 121a (bump pad) of a chip package base plate 12 (chip packagesubstrate); this chip package base plate 12 is formed with a plurality of line layers 122 (wiring layer) and insulating barrier 123 (insulation layer); be to connect between two line layers 122 with conductive structure 125 (conductor plug); the line layer 122a of these chip package base plate 12 the superiors is formed with welding resisting layer 13a (patterned solder mask) again, protects this line layer 122 and appears this weld pad 121a.
The line layer 122b of these chip package base plate 12 bottoms is formed with a plurality of weld pad 121b again; and on this line layer 122b, be formed with a welding resisting layer 13b; protection circuit layer 122b also appears this weld pad 121b, forms the conductive structure as tin ball 14 (ball) on this weld pad 121b.
At these chip package base plate 12 upper surfaces, make the chip mat 101 of this semiconductor chip 10 be electrically connected to the weld pad 121a of the line layer 122a of the superiors with conductive projection 11, weld pad 121b at chip package base plate 12 bottom line layer 122b then electrically connects tin ball 14, finishes a chip upside-down mounting type BGA Package.
Yet the technology of this chip upside-down mounting type BGA Package, chip package base plate 12 is the production model of separating with the technology that semiconductor chip 10 is electrically connected to chip package base plate 12 and encapsulation, promptly this chip package base plate 12 is independent process, it is another independent process that this semiconductor chip 10 is encapsulated into chip package base plate 12, two independently technology can produce the problem that yield is low and the production cycle is long, electrical functionality can't effectively promote after rising to certain level again.The spherical grid array type of flip-chip (FCBGA) though structure can use at the multiway number more and the product of high frequency more, but whole packaging cost height, and still have many restrictions technically, especially electrically connecting part, because environmental protection demand, make to electrically connect material, for example the lead of soldering tin material (Pb) etc. will be forbidden, and use other substitution material quality wild effect electrical, mechanical transitivity to occur.
Because existing chip upside-down mounting type ball grid array (FCBGA) packaging technology is a separation processes, has the disappearance that yield is low and the production cycle is long, cause production cost to improve, can't promote competitiveness, become industry problem anxious to be solved.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of direct electric connection flip chip packaging structure of semiconductor chip, integrating semiconductor chip and connecing of chip bearing member are put and electric connection structure simultaneously, the integration that simplify semiconductor industry processing step, reduces cost and simplify interface.
A further object of the present invention is to provide a kind of direct electric connection flip chip packaging structure of semiconductor chip, increases the flexibility that structure space utilizes, and promotes the electrical functionality of semiconductor device.
Another purpose of invention is to provide a kind of direct electric connection flip chip packaging structure of semiconductor chip, can promote the heat dissipation of chip.
Another purpose of the present invention is to provide a kind of direct electric connection flip chip packaging structure of semiconductor chip, makes this semiconductor package have more slimming.
For reaching above-mentioned and other purpose, the direct electric connection flip chip packaging structure of semiconductor chip of the present invention comprises: at least one semiconductor chip, this semiconductor chip has an active face and inactive face, and the active face of this semiconductor chip is formed with electric connection pad; At least one dielectric layer is formed at the active face of semiconductor chip, and the area of this dielectric layer is greater than this active face, and the side surface and the inactive face of this semiconductor chip can directly expose; And at least one line layer, be formed on this dielectric layer for connecing a side of putting semiconductor chip, and this line layer is to be electrically connected to electric connection pad on this semiconductor chip by a plurality of conductive electrodes that are formed in this dielectric layer.
On this dielectric layer, connect a side that is equipped with semiconductor chip and also be formed with electronic pads or the conductive electrode in this dielectric layer is exposed, power supply property connection electronic component (for example active or passive component); Moreover, on this surface lines layer, can plant a plurality of conducting elements, be electrically connected to external device (ED) for this semiconductor chip.
The side surface of semiconductor chip of the present invention and inactive face are to be exposed outside, thereby can promote radiating efficiency, further reduce the whole height of assembling structure simultaneously, effectively realize compact purpose.A side that has exposed this semiconductor chip at this assembling structure can connect puts various electronic component (as active or passive component etc.), and this electronic component is by barish conductive electrode and line layer, and then electrically connect the flexible Application in implementation structure space and the purpose that promotes electrical quality with this semiconductor chip; In addition, on the surface lines of this assembling structure, plant a plurality of conducting elements, supply the direct electric connection flip chip packaging structure of this semiconductor chip to be electrically conducted external device (ED).
In addition, the present invention directly is formed with at least one line layer on the active face of semiconductor chip, this line layer structure can be by conductive electrode, be electrically conducted the electric connection pad of this semiconductor chip, and can be provided with conducting elements such as a plurality of for example soldered balls, weld pad, pin or metal coupling at the circuit outer surface, provide the direct electric connection flip chip packaging structure of this semiconductor chip to be electrically connected to external device (ED).
Therefore the present invention has integrated connecing of semiconductor chip and chip bearing member and has put and electric connection structure, simplifies semiconductor already processing step, the integration that reduces cost and simplify interface, makes this semiconductor package have more slimming.
Description of drawings
Fig. 1 is the generalized section of the semiconductor device of the 6th, 774, No. 498 patents propositions of the U.S.;
Fig. 2 A to Fig. 2 F figure is the generalized section of the direct electric connection flip chip packaging structure embodiment 1 of semiconductor chip of the present invention; And
Fig. 3 A to Fig. 3 C is the generalized section of the direct electric connection flip chip packaging structure embodiment 2 of semiconductor chip of the present invention.
Embodiment
Embodiment 1
Fig. 2 A to Fig. 2 D is the generalized section of the direct electric connection flip chip packaging structure embodiment 1 of semiconductor chip of the present invention.What must note a bit is herein, these accompanying drawings are the schematic diagram of simplification, it only illustrates basic framework of the present invention in a schematic way, therefore only show the formation relevant with the present invention, and the formation that shows not is number, shape and dimension scale drafting when implementing with reality, number, shape and dimension scale during its actual enforcement is a kind of optionally design, and its formation arrangement form may be more complicated.
The direct electric connection flip chip packaging structure of the semiconductor chip of the present invention shown in Fig. 2 A comprises: at least one semiconductor chip 23, this semiconductor chip has an active face 231 and an inactive face, and the active face 231 of this semiconductor chip 23 is formed with electric connection pad 231a, this semiconductor chip 23 is an active element or passive component, and wherein passive component for example is one of group of compositions such as resistor, capacitor and inductor; At least one dielectric layer 24 be formed at the active face 231 of semiconductor chip 23, and the area of this dielectric layer 24 can directly expose the side surface of this semiconductor chip 23 and inactive face greater than this active face 231; And at least one line layer 25, the not confession that is formed on this dielectric layer 24 connects a side of putting semiconductor chip 23, and this line layer 25 is the conductive electrode 25a that are formed in this dielectric layer 24 by a plurality of, is electrically connected to the electric connection pad 231a of this semiconductor chip 23.
The direct electric connection flip chip packaging structure of semiconductor chip of the present invention comprises also can form a circuit layer reinforced structure 26 on this dielectric layer 24 and line layer 25, this circuit layer reinforced structure 26 comprises dielectric layer 260, is formed at the line layer 261 on this dielectric layer 260 and passes the conductive blind hole 262 that this dielectric layer 260 is connected to line layer 261, and makes this circuit layer reinforced structure 26 be electrically connected to this line layer 25 by this conductive blind hole 262; And form welding resisting layer 27 at the outer fringe surface of this circuit layer reinforced structure 26, and this welding resisting layer 27 is formed with a plurality of perforates, expose outside the part line layer of these circuit layer reinforced structure 26 outer fringe surfaces, be formed with conducting elements 28 such as a plurality of for example soldered balls, weld pad, pin or metal coupling thereon, can be electrically conducted external device (ED) for semiconductor chip 23.
Because this semiconductor chip 23 does not connect the side surface and the inactive face of putting at dielectric layer 24 and can directly be emerging in the external world, can promote radiating effect, and can reduce the whole height of assembling structure, reaches compact purpose.
See also Fig. 2 B, this line layer 25 that is formed on dielectric layer 24 surfaces includes a plurality of conductive electrode 25a, wherein partially conductive electrode 25a is the electric connection pad 231a that is electrically connected to this semiconductor chip 23, and there is partially conductive electrode 25a to be emerging in to be positioned at non-connecing on the surface of putting semiconductor chip 23, put exterior electrical components 29 for follow-up on the surface of this dielectric layer 24, connecing, as active element or passive component, and can be electrically connected to internal wiring by the conductive electrode 25a that part exposes, implementation structure space flexible Application and the purpose that promotes electrical quality.Certainly, also can form semiconductor chip and exterior electrical components earlier, on semiconductor chip and exterior electrical components, form above-mentioned dielectric layer, circuit layer reinforced structure, conductive blind hole, welding resisting layer again and be electrically conducted structure as soldered ball etc.
See also Fig. 2 C, be formed with a thin dielectric layer 24 ' at the side surface of this semiconductor chip 23, this semiconductor chip 23 is coated and fixed in the bottom surface of dielectric layer 24, protection semiconductor chip 23 also avoids this semiconductor chip 23 to be subjected to damage of external force.The line layer 25 that is formed on dielectric layer 24 surfaces comprises a plurality of conductive electrode 25a, and this conductive electrode 25a is the electric connection pad 231a that is electrically connected to this semiconductor chip 23.
See also Fig. 2 D, be implemented in these semiconductor chip 23 side surfaces and be formed with thin dielectric layer 24 ', the line layer 25 that is formed on dielectric layer 24 surfaces comprises a plurality of conductive electrode 25a, wherein partially conductive electrode 25a is the electric connection pad 231a that is electrically connected to this semiconductor chip 23, and there is partially conductive electrode 25a to be emerging in to be positioned at non-connecing on the surface of putting semiconductor chip 23, put exterior electrical components for follow-up on the surface of this dielectric layer 24, connecing, the flexible Application in implementation structure space and the purpose that promotes electrical quality.Certainly, also can be formed with semiconductor chip and exterior electrical components earlier, on semiconductor chip and exterior electrical components, form above-mentioned dielectric layer, circuit layer reinforced structure, conductive blind hole, welding resisting layer again and be electrically conducted structure as soldered ball etc.
See also Fig. 2 E, be formed with a metal level 20 in these semiconductor chip 23 non-inactive face of putting at dielectric layer 24 that connect, this metal level 20 is materials of a high coefficient of heat transfer, can strengthen the radiating effect of semiconductor chip 23 by this metal level 20.The line layer 25 that is formed on dielectric layer 24 surfaces comprises a plurality of conductive electrode 25a, and this conductive electrode 25a is the electric connection pad 231a that is electrically connected to this semiconductor chip 23.
See also Fig. 2 F, be implemented in these semiconductor chip 23 non-inactive face that place dielectric layer 24 that connect and be formed with metal level 20, the line layer 25 that is formed on dielectric layer 24 surfaces comprises a plurality of conductive electrode 25a, wherein partially conductive electrode 25a is the electric connection pad 231a that is electrically connected to this semiconductor chip 23, and there is partially conductive electrode 25a to be emerging in to be positioned at non-connecing on the surface of putting semiconductor chip 23, put exterior electrical components 29 for follow-up on the surface of this dielectric layer 24, connecing, the flexible Application in implementation structure space and the purpose that promotes electrical quality.Certainly, also can be formed with semiconductor chip and exterior electrical components earlier, on semiconductor chip and exterior electrical components, be formed with above-mentioned dielectric layer, circuit layer reinforced structure, conductive blind hole, welding resisting layer again and be electrically conducted structure as soldered ball etc.
Said process can use according to the needs matched combined, can be combined into various combination.
Embodiment 2
Other sees also Fig. 3 A to Fig. 3 C, and it is the generalized section of the direct electric connection flip chip packaging structure embodiment 2 of semiconductor chip of the present invention.Embodiments of the invention 2 are approximate with embodiment 1, its main difference is that the lower surface that is dielectric layer forms an electronic pads, make this semiconductor chip and electronic pads exposed to outside, the whole height of reduction structure, realize compact purpose, and, can further provide the electric connection exterior electrical components because of it has electronic pads.
See also Fig. 3 A, the direct electric connection flip chip packaging structure of semiconductor chip of the present invention comprises: at least one semiconductor chip 33, and the active face 331 of this semiconductor chip 33 is formed with electric connection pad 331a; At least one dielectric layer 34, be formed at the active face 331 of semiconductor chip 33, and the area of this dielectric layer 34 connects a side of putting semiconductor chip 33 at this dielectric layer 34 and is formed with a plurality of electronic padses 31 greater than this active face 331, and this electronic pads 31 is emerging in this dielectric layer 34 surfaces; And at least one line layer 35, the not confession that is formed on this dielectric layer 34 connects a side of putting semiconductor chip 33, this line layer 35 that is formed on dielectric layer 34 surfaces comprises a plurality of conductive electrode 35a, wherein partially conductive electrode 35a is the electric connection pad 331a that is electrically connected to this semiconductor chip 33, and there is partially conductive electrode 35a to be electrically conducted electronic pads 31, put exterior electrical components 39 for follow-up on the surface of this dielectric layer 34, connecing, as active element or passive component, and can be electrically connected to internal wiring by the conductive electrode 35a that part exposes, the flexible Application in implementation structure space and the purpose that promotes electrical quality.Certainly, also can be formed with semiconductor chip 33 and exterior electrical components 39 earlier, on semiconductor chip 33 and exterior electrical components 39, be formed with above-mentioned dielectric layer 34, circuit layer reinforced structure 36, conductive electrode 35a, welding resisting layer 34 again and be electrically conducted structure as soldered ball 38 etc.
Form a circuit layer reinforced structure 36 on the surface of this dielectric layer 34 and line layer 35 again, this circuit layer reinforced structure 36 comprises dielectric layer 360, is formed at the line layer 361 on this dielectric layer 360 and passes the conductive blind hole 362 that this dielectric layer 360 is connected to line layer 361, and makes this circuit layer reinforced structure 36 be electrically connected to this line layer 35 by this conductive blind hole 362; And form welding resisting layer 37 at the outer fringe surface of this circuit layer reinforced structure 36, and this welding resisting layer 37 is formed with a plurality of perforates, expose outside the part line layer of these circuit layer reinforced structure 36 outer fringe surfaces, be formed with conducting elements 38 such as a plurality of for example soldered balls, weld pad, pin or metal coupling thereon, can be electrically conducted external device (ED) for semiconductor chip 33.
See also Fig. 3 B; Fig. 3 B and Fig. 3 A are approximate; its main difference is that these semiconductor chip 33 side surfaces are formed with a thin dielectric layer 34 ', and this semiconductor chip 33 is coated and fixed in the bottom surface of dielectric layer 34, and protection semiconductor chip 33 also avoids this semiconductor chip 33 to be subjected to damage of external force.And this dielectric layer 34 is positioned at the electronic pads 31 that connects the surface of putting semiconductor chip 33 1 sides and also can connects and put exterior electrical components for follow-up surface at this dielectric layer 34, the flexible Application that improves structure space with promote electrical quality.
See also Fig. 3 C, Fig. 3 C and Fig. 3 A are approximate, its main difference is that this is formed with a metal level 30 in these semiconductor chip 33 non-inactive face that place dielectric layer 34 that connect, and this metal level 30 is materials of a high coefficient of heat transfer, can strengthen the radiating effect of semiconductor chip 33 by this metal level 30.And this dielectric layer 34 is positioned at the electronic pads 31 that connects the surface of putting semiconductor chip 33 1 sides and also can connects and put exterior electrical components for follow-up surface at this dielectric layer 34, the flexible Application that improves structure space with promote electrical quality.
Direct electric connection flip chip packaging structure by semiconductor chip of the present invention provides this semiconductor chip to be exposed at the surface of dielectric layer outward, the heat that effective loss semiconductor chip produces when operation, and the integral thickness of shortening semiconductor device, realize thin short and small purpose; In addition, the present invention directly is formed with at least one line layer on the semiconductor chip active face, this line layer structure can be by this conductive electrode to be electrically conducted the electric connection pad of this semiconductor chip, and the conducting element of a plurality of for example soldered balls, weld pad, pin or metal coupling etc. can be set at the circuit outer surface, provide the direct electric connection flip chip packaging structure of this semiconductor chip to be electrically connected to external device (ED); Moreover, connecing a side that is equipped with semiconductor chip on this dielectric layer also is formed with electronic pads or the conductive electrode in this dielectric layer is exposed, power supply property connection electronic component (for example active or passive component), make this electronic component can be by line layer and conductive electrode or by line layer and conductive electrode and electronic pads, and then electrically connect the flexible Application in implementation structure space and the purpose that promotes electrical quality with this semiconductor chip.
Therefore, the present invention has integrated semiconductor chip and circuit layer reinforced structure, avoids the shortcoming of existing semiconductor packaging and the integration problem at semiconductor device interface, simultaneously, can improve the quality and acceptance rate, obtain the structure packing quality and the reliability of products of burying in the good semiconductor chip.
Claims (8)
1. the direct electric connection flip chip packaging structure of a semiconductor chip is characterized in that, the direct electric connection flip chip packaging structure of this semiconductor chip comprises:
At least one semiconductor chip and exterior electrical components, this semiconductor chip has an active face and inactive face, and the active face of this semiconductor chip is formed with electric connection pad;
At least one dielectric layer, be formed on the active face of this semiconductor chip and this exterior electrical components and and directly contact with active face and this exterior electrical components of this semiconductor chip, and the area of this dielectric layer makes side surface, this inactive face and this exterior electrical components of this semiconductor chip directly expose greater than this active face and this exterior electrical components; And
At least one line layer is formed on this dielectric layer for connecing a side of putting semiconductor chip, and this line layer is directly to be electrically connected to electric connection pad and this exterior electrical components on this semiconductor chip by a plurality of conductive electrodes that are formed in this dielectric layer.
2. the direct electric connection flip chip packaging structure of semiconductor chip as claimed in claim 1, it is characterized in that the direct electric connection flip chip packaging structure of this semiconductor chip also comprises the circuit layer reinforced structure that is formed at this dielectric layer and line layer surface.
3. the direct electric connection flip chip packaging structure of semiconductor chip as claimed in claim 2 is characterized in that, this circuit layer reinforced structure also comprises and is formed at its surperficial conducting element.
4. the direct electric connection flip chip packaging structure of semiconductor chip as claimed in claim 3 is characterized in that, this conducting element is in soldered ball, weld pad, pin or the metal coupling.
5. the direct electric connection flip chip packaging structure of semiconductor chip as claimed in claim 1 is characterized in that, this semiconductor chip is active element or passive component.
6. the direct electric connection flip chip packaging structure of semiconductor chip as claimed in claim 1 is characterized in that, this exterior electrical components is active element or passive component.
7. the direct electric connection flip chip packaging structure of a semiconductor chip is characterized in that, the direct electric connection flip chip packaging structure of this semiconductor chip comprises:
At least one semiconductor chip and exterior electrical components, this semiconductor chip has an active face and inactive face, and the active face of this semiconductor chip is formed with electric connection pad;
At least one dielectric layer, be formed on the active face of this semiconductor chip and this exterior electrical components and and directly contact with active face and this exterior electrical components of this semiconductor chip, and the area of this dielectric layer makes the inactive face of this semiconductor chip and this exterior electrical components directly expose greater than this active face and this exterior electrical components;
One another dielectric layer is formed at the side surface of this semiconductor chip, and the inactive face of this semiconductor chip and this exterior electrical components do not contact this another dielectric layer and are and expose; And
At least one line layer is formed on this dielectric layer for connecing a side of putting semiconductor chip, and this line layer is directly to be electrically connected to electric connection pad and this exterior electrical components on this semiconductor chip by a plurality of conductive electrodes that are formed in this dielectric layer.
8. the direct electric connection flip chip packaging structure of a semiconductor chip is characterized in that, the direct electric connection flip chip packaging structure of this semiconductor chip comprises:
At least one semiconductor chip and exterior electrical components, this semiconductor chip has an active face and inactive face, and the active face of this semiconductor chip is formed with electric connection pad;
At least one dielectric layer, be formed on the active face of this semiconductor chip and this exterior electrical components and and directly contact with active face and this exterior electrical components of this semiconductor chip, and the area of this dielectric layer makes the side surface of this semiconductor chip and this exterior electrical components directly expose greater than this active face and this exterior electrical components;
One metal level is formed at the inactive face of this semiconductor chip; And
At least one line layer is formed on this dielectric layer for connecing a side of putting semiconductor chip, and this line layer is directly to be electrically connected to electric connection pad and this exterior electrical components on this semiconductor chip by a plurality of conductive electrodes that are formed in this dielectric layer.
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| CNB2005101233974A CN100561725C (en) | 2005-11-25 | 2005-11-25 | The direct electric connection flip chip packaging structure of semiconductor chip |
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