CN100550343C - Shallow groove isolation layer of semiconductor element and preparation method thereof - Google Patents
Shallow groove isolation layer of semiconductor element and preparation method thereof Download PDFInfo
- Publication number
- CN100550343C CN100550343C CNB2007100081102A CN200710008110A CN100550343C CN 100550343 C CN100550343 C CN 100550343C CN B2007100081102 A CNB2007100081102 A CN B2007100081102A CN 200710008110 A CN200710008110 A CN 200710008110A CN 100550343 C CN100550343 C CN 100550343C
- Authority
- CN
- China
- Prior art keywords
- silica layer
- groove
- ozone
- rate ratio
- carbon content
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention provides a kind of method of in groove, inserting silica layer, a substrate that includes a plurality of grooves at first is provided, then provide to have one the one O
3The reacting gas of/TEOS flow-rate ratio and carry out one first depositing operation is to form one first silica layer comprehensively in substrate surface and groove.Then, provide and have one the 2nd O
3The reacting gas of/TEOS flow-rate ratio and carry out one second depositing operation, forming one second silica layer in substrate surface, and the 2nd O
3/ TEOS flow-rate ratio is less than an O
3/ TEOS flow-rate ratio.
Description
Technical field
The present invention relates to insulation system of a kind of semi-conducting material and preparation method thereof, relate in particular to a kind of utilization repeatedly insulation system and the method for deposition step making semi-conducting material.
Background technology
In semi-conducting material, often utilize silica material or silicon nitride material to make insulation system, to be used for isolated electrical components.General dielectric layer or insulation system be utilize regional oxidizing process (localizedoxidation isolation, LOCOS) or thin film deposition processes make, for example with monosilane (silane, SiH
4), (tetra-ethyl-ortho-silicate TEOS) and gas chemical reaction to each other such as oxygen, and forms thin film to tetraethoxysilane in the surface of semi-conducting material, and it is had intercept electrical function.
In 0.18 micron technology, the electrical isolation technology of active region (active area) is with shallow groove isolation layer (shallow trench isolation, STI) be main, it is to form shallow trench at semiconductor-based basal surface, and in wherein inserting silica layer, with each adjacent active region of effective electrical isolation.Yet, along with semiconductor technology design live width continue dwindle, enter the deep-submicron epoch, the size of shallow groove isolation layer is also dwindled relatively thereupon, the process conditions of therefore effectively filling up silica layer in shallow trench are also more and more harsh, become a major challenge of semiconductor applications.
Traditional shallow groove isolation layer technology is to utilize high density plasma CVD (highdensity plasma chemical vapor deposition earlier, HDCVD) method, fill up dielectric layer with being formed in the shallow trench of semiconductor-based basal surface, and then etch-back or remove the outer additional dielectric layer of shallow trench in chemico-mechanical polishing (CMP) mode, form smooth substrate surface.But the development that component size is day by day dwindled along with improving constantly of integrated circuit density, in the semiconductor technology below 65 nanometers, when the depth-width ratio (aspect ratio) of shallow trench greater than 6 the time, the ladder that aforementioned high density plasma CVD method can provide covers (step coverage) ability and fills out hole ability (gap fillcapacity) and has not been inconsistent process requirements, can't fill up shallow trench effectively fully.
For improving the problems referred to above, there is the chemical vapour deposition technique of multiple Improvement type to be suggested, wherein with ozone (ozone, O
3) (ozone-assisted sub-atmosphericpressure CVD, SACVD) technology is proved to possess through research the excellent step covering power and the uniformity to auxiliary time aumospheric pressure cvd.The auxiliary time aumospheric pressure cvd technology of above-mentioned ozone is to utilize ozone and tetraethoxysilane (tetra-ethyl-ortho-silicate, TEOS), be about all thick silica layer of inferior condition of normal pressure deposit of 60 holders (torr) in for example reaction pressure as the initial gas of reaction.
Yet the auxiliary time aumospheric pressure cvd technology of aforesaid ozone but still has many shortcomings and still treats further to overcome and improvement in practical application.The silicon oxide thin film itself that is deposited with the auxiliary time aumospheric pressure cvd technology of existing ozone at high temperature can shrink, for example after handling 30 minutes under 1050 ℃, have up to about shrinkage amplitude of about 7% (shrink), and the characteristic of SACVD silicon oxide thin film is also relatively poor, for example, the wet etching rate is very fast, and high surfaces selectivity (deposition sensitivity) is arranged.In addition, tradition is easy to generate cavity (void) and impervious seam problems such as (seam) with the auxiliary time aumospheric pressure cvd technology of ozone, has a strong impact on the electrically isolated effect of shallow groove isolation layer.Please refer to Fig. 1, Fig. 1 is the existing generalized section of utilizing the auxiliary time formed shallow groove isolation layer of aumospheric pressure cvd technology of ozone.When using the auxiliary time aumospheric pressure cvd technology of ozone in substrate 10 surfaces and shallow trench 14, to form silica layer film 12, its film growth characteristic mainly is to be grown up and fill up shallow trench 14 to the centre by the sidewall 16 of shallow trench 14, therefore, finally can in the middle of groove 14, form impervious seam 18, and form cavity 20 easily, and also can't remove with traditional nitrogen environment annealing way in these seam 18 defectives and cavity 20, and be subjected to the erosion of follow-up cleaning step easily, cause being communicated with problems such as the formation of groove and polysilicon lines short circuit.
The production method of present another kind of shallow groove isolation layer is repeatedly SACVD (multi-step with TEOS ramp-up SACVD) method of utilizing TEOS cumulative, to improve the shortcoming of silica layer that traditional SACVD is formed.The cumulative repeatedly SACVD method of TEOS is to continue to feed silicon-containing gas (silicon-containing gas) in reative cell, also oxygen-containing gas is fed in the reative cell simultaneously, to carry out SACVD technology, and during forming silica layer, continue to change the inflow velocity that improves silicon-containing gas, in groove, to insert silica layer.Though the method can be improved the surface selectivity problem of traditional SACVD silica layer that method forms, below groove dimensions is 65 nanometers even during the situation of 45 nanometers, still problems such as aforementioned impervious seam or cavity can take place.
Therefore, how in the groove that size is day by day dwindled, to insert dielectric material fully, and do not produce cavity or impervious seam, still the problem of demanding urgently studying for present industry.
Summary of the invention
Main purpose of the present invention is to provide a kind of repeatedly deposition step to make the method for silica layer, to form the insulation system with multilayer silica layer in substrate surface.
According to the present invention, disclose a kind of method of in groove, inserting silica layer, one substrate that includes a plurality of grooves at first is provided, then provide to have first ozone/reacting gas of tetraethoxysilane flow-rate ratio and carry out one first depositing operation, in substrate surface and groove, to form one first silica layer comprehensively.Then, provide to have second ozone/reacting gas of tetraethoxysilane flow-rate ratio and carry out one second depositing operation, forming one second silica layer in substrate surface, and second ozone/tetraethoxysilane flow-rate ratio is less than first ozone/tetraethoxysilane flow-rate ratio.
According to the present invention, other discloses a kind of insulation system that is positioned at substrate surface, and this insulation system includes at least one first groove and one second groove is located at substrate surface, and wherein the width of first groove is less than the width of second groove.Insulation system also includes inwall and lower surface and one second silica layer that one first silica layer fills up first groove inside respectively and is located at second groove, be located in second groove and cover the surface of first silica layer, and the carbon content of first silica layer is different from the carbon content of second silica layer.
Because the present invention utilizes ozone/higher reacting gas of tetraethoxysilane flow-rate ratio to form one first silica layer earlier, therefore first silica layer has preferable quality, the hole ability of well filling out, low surface selectivity and lower high-temperature shrinkage amplitude are for example arranged, so first silica layer can be formed in the groove by adequate relief, even can effectively fill up width and be lower than the groove of 45 nanometers and also do not produce problem such as impervious seam.In addition, the present invention is behind first depositing operation, and other uses the less reacting gas of second ozone/tetraethoxysilane flow-rate ratio to carry out one second depositing operation, and comparatively fast deposition velocity forms second silica layer, can effectively fill up the bigger groove of width.Therefore the present invention can take into account the making of the different shallow groove isolation layer of size simultaneously, also can produce the insulation system with better quality under the situation of process speed considering.
In order to make those skilled in the art can clearer understanding feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
Fig. 1 is the existing generalized section of utilizing the auxiliary time formed shallow groove isolation layer of aumospheric pressure cvd technology of ozone;
Fig. 2 to Fig. 6 is the generalized section of substrate surface shallow groove isolation layer structure of the present invention with first embodiment that makes flow process;
Fig. 7 to Figure 11 is the shallow groove isolation layer structure of semiconductor element of the present invention and the generalized section of second embodiment that makes flow process.
The main element symbol description
10 substrates, 12 silica layer films
14 shallow trenchs, 16 sidewalls
18 impervious seams, 20 cavities
50 pad oxides of the semiconductor-based ends 52
54 pad nitration cases, 56 shielding layers
58 openings, 60 shallow trenchs
62 shallow trench sidewalls, 64 shallow trenchs bottom
66 thermal oxidation layings, 68 first silica layers
70 second silica layers, 72 shallow groove isolation layers
100 pad oxides of the semiconductor-based ends 102
104 pad nitrogen silicon layers, 106 first shallow trenchs
108 second shallow trenchs 110 the 3rd shallow trench
112 first trenched side-walls, 114 second trenched side-walls
116 the 3rd trenched side-walls, 118 first channel bottoms
120 second channel bottoms 122 the 3rd channel bottom
124 first silica layers, 126 second silica layers
128 the 3rd silica layers, 130 first shallow groove isolation layers
132 second shallow groove isolation layers
134 the 3rd shallow groove isolation layers
136 semiconductor elements
Embodiment
Please refer to Fig. 2 to Fig. 6, Fig. 2 to Fig. 6 is the generalized section of shallow groove isolation layer structure of the present invention with first embodiment that makes flow process.At first, as shown in Figure 2, provide semiconductor substrate 50, for example silicon base.Then, on the semiconductor-based end 50, form the pad oxide 52 that a thickness is about 30 dust to 200 dusts.Pad oxide 52 can utilize chemical vapour deposition technique or thermal oxidation pattern of growth to form.Subsequently, on pad oxide 52, cover the pad nitration case 54 that a thickness is about 500 dust to 2000 dusts, and with pad oxide 52 jointly as shielding layer 56.
Then as shown in Figure 3, in shielding layer 56, form opening 58 with photoetching process and etch process, and then the semiconductor-based end 50 that utilizes shielding layer 56 to come out via opening 58 downward etch exposed as etching mask, to form a shallow trench 60, wherein the ratio of the depth H of shallow trench 60 and width W is defined as depth-width ratio (aspect ratio), and the depth-width ratio of shallow trench 60 can be greater than 4, even greater than 6.Then, optionally carry out a thermal oxidation technology, form a thermal oxidation laying 66 with 64 surfaces, bottom with sidewall 62 in shallow trench 60.
Please refer to Fig. 4, carry out one first silica layer depositing operation, in reative cell, feed ozone/tetraethoxysilane flow-rate ratio, form one first silica layers 68 with 64 surfaces, bottom with sidewall 62 in shallow trench 60 greater than 18 reacting gas.Because ozone/tetraethoxysilane flow-rate ratio has less surface selectivity and well fills out the hole ability greater than the formed silica layer of 18 reacting gas, therefore can form uniform first silica layer 68 with 64 surfaces, bottom at the sidewall 62 of shallow trench 60.
After can overcoming first silica layer 68 of surface selectivity with the formation of the first silica layer depositing operation, carry out one second silica layer depositing operation again, feed ozone/tetraethoxysilane flow-rate ratio less than 18 reacting gas, form one second silica layer 70, be covered in first silica layer, 68 surfaces, and fill up shallow trench 60 fully.Then, with the H of boiler tube at high flow capacity
2/ O
2Carry out a steam annealing technology under gaseous environment and 700 ℃, be warming up to 1000 ℃ again, so that first silica layer 68 and 70 densifications of second silica layer, as shown in Figure 5.
At last, as shown in Figure 6, carry out a chemico-mechanical polishing (chemical mechanical polishing, CMP) technology, and to fill up nitration case 54 as stopping layer, remove first silica layer 68 and second silica layer 70 on the surface, the semiconductor-based ends 50, to finish the making of a shallow groove isolation layer 72.
In addition, in the semiconductor chip, being used for electrically, the shallow groove isolation layer of isolated each element may have different dimension width and depth-width ratio because of demand and circuit design, and various silica layer processes all have the different hole effects of filling out for the shallow trench of different aspect ratios, therefore, the second embodiment of the present invention will illustrate how to utilize the inventive method, insert silica layer simultaneously to produce electrically isolated respond well shallow groove isolation layer in the shallow trench of different aspect ratios.
Please refer to Fig. 7 to Figure 11, Fig. 7 to Figure 11 is the shallow groove isolation layer structure of semiconductor element 136 of the present invention and the generalized section of second embodiment that makes flow process.As shown in Figure 7, semiconductor element 136 includes semiconductor substrate 100, and its surface is provided with a pad oxide 102 and a pad nitration case 104 in regular turn, and is provided with a plurality of semiconductor elements (figure does not show) in addition.At first, carry out a photoetching and etch process, surface etching goes out a plurality of shallow trenchs in the semiconductor-based ends 100, include the shallow trench of at least three kinds of different in width in those shallow trenchs, first shallow trench 106 for example, second shallow trench 108 and the 3rd shallow trench 110, wherein the width of first shallow trench 106 is less than the width of second shallow trench 108, and the width of second shallow trench 108 is less than the width of the 3rd shallow trench 110, for example the width of first shallow trench 106 is 45 nanometers, and the width of second shallow trench 108 is 65 nanometers, and the width of the 3rd shallow trench 110 is 85 nanometers, therefore, the depth-width ratio of first shallow trench 106 is greater than the depth-width ratio of second shallow trench 108, and the depth-width ratio of second shallow trench 108 is greater than the depth-width ratio of the 3rd shallow trench 110.
Please refer to Fig. 8 then, selectivity is carried out a thermal oxidation technology, forms a thermal oxidation silica layer (figure does not show) respectively in the surface of first shallow trench 106, second shallow trench 108 and the 3rd shallow trench 110.Then, in reative cell, feed reacting gas with first ozone/tetraethoxysilane flow-rate ratio, carry out one first silica layer depositing operation, on the semiconductor-based end 100 with in first shallow trench 106, second shallow trench 108 and the 3rd shallow trench 110, to form one first silica layer 124.It should be noted that first ozone/tetraethoxysilane flow-rate ratio greater than 18, and this first silica layer depositing operation is a SACVD technology.Because the depth-width ratio maximum of first shallow trench 106, therefore within first shallow trench 106, fill up silica layer fully and do not produce impervious seam or cavity difficulty the most.Yet when the ratio of ozone in the reacting gas was higher, formed first silica layer 124 had better quality, for example at high temperature was difficult for shrinking, having and well fill out hole ability and low surface selectivity.Therefore, the process time of the first silica layer depositing operation is that first shallow trench 106 that fills up the depth-width ratio maximum fully with first silica layer 124 is a condition, and perhaps half of width that reaches first shallow trench 106 approximately with the thickness of first silica layer 124 is the first silica layer depositing operation dwell time.In a preferred embodiment, the first silica layer depositing operation time was about more than 160 seconds.At this moment, first trenched side-wall 112, first channel bottom 118 and inside are filled up first silica layer 124 all fully, and can not produce any cavity or impervious seam, the surface of second channel bottom 120, second trenched side-wall 114, the 3rd channel bottom 122 and the 3rd trenched side-wall 116 then forms the first all thick silica layer 124 respectively.In this embodiment, first silica layer 124 have about 200 dusts (angstrom,
) above thickness, and owing to tetraethoxysilane ratio in the reacting gas is lower, therefore the carbon content of first silica layer 124 is also lower.
Then, please refer to Fig. 9, use the SACVD method, carry out one second silica layer depositing operation, in reative cell, feed and have second ozone/tetraethoxysilane flow-rate ratio less than 18 reacting gas, it was reacted about more than 300 seconds, to form one second silica layer 126 comprehensively in surface, the semiconductor-based ends 100, wherein second silica layer 126 is to fill up fully in second shallow trench 108 not to be provided with the part of first silica layer 124, and is covered on first silica layer 124 on the 3rd channel bottom 122 and the 3rd trenched side-wall 116 surfaces.
Then, as shown in figure 10, carry out one the 3rd silica layer depositing operation, in reative cell, feed reacting gas with the 3rd ozone/tetraethoxysilane flow-rate ratio, utilize the SACVD method and form one the 3rd silica layer 128 comprehensively, be covered in and also fill up the 3rd shallow trench 110 inside on second silica layer 126 fully in surface, the semiconductor-based ends 100.The 3rd ozone/tetraethoxysilane flow-rate ratio is less than second ozone/tetraethoxysilane flow-rate ratio, therefore in the present embodiment, the carbon content of the 3rd silica layer 128 is higher than the carbon content of first silica layer 124 and second silica layer 126, and the high-temperature shrinkage amplitude of the 3rd silica layer 128 is also greater than the high-temperature shrinkage amplitude of first silica layer 124 and second silica layer 126.Then, first silica layer 124, second silica layer 126 and the 3rd silica layer 128 are carried out a steam annealing technology, for example in 700 ℃ of left and right sides environment, feed the hydrogen and the oxygen of high flow capacity, carry out this steam annealing technology.Then, be warming up to 1000 ℃ again so that the silica layer densification.It should be noted that, because the size of the 3rd shallow trench 110 is bigger, therefore the 3rd silica layer depositing operation of SACVD can also replace by other depositing operations, high density chemistry gas-phase deposition (high density plasma chemicalvapor deposition for example, HDPCVD), to form the 3rd silica layer 128 that can fill up the 3rd shallow trench 110 inside fully.
At last, please refer to Figure 11, carry out a flatening process, a CMP (Chemical Mechanical Polishing) process for example, with remove surface, the semiconductor-based ends 100 on first silica layer 124, second silica layer 126 and the 3rd silica layer 128, till pad nitration case 104, first shallow groove isolation layer 130, second shallow groove isolation layer 132 and the 3rd shallow groove isolation layer 134 that have three kinds of dimension width with formation.By generalized section shown in Figure 11 as can be known, dielectric layer in first shallow groove isolation layer 130 of width minimum only has a kind of carbon content, and second shallow groove isolation layer, 132 internal causes have first silica layer 124 and second silica layer 126, therefore have two kinds of carbon contents, and the carbon content that is positioned at second silica layer 126 of mid portion is higher than the carbon content of first silica layer 124.Moreover, the 3rd shallow groove isolation layer 134 inside are provided with carbon content more and more higher first silica layer 124, second silica layer 126 and the 3rd silica layer 128 successively by the 3rd channel bottom 122 surfaces to mid portion, and therefore the silica layer of the 3rd shallow groove isolation layer 134 has three kinds of carbon contents.
Spirit of the present invention mainly is to utilize in the SACVD technology if the ozone of feeding reacting gas is high more to the ratio of tetraethoxysilane, the characteristic that the quality of its silica layer that forms is good more, design when the higher shallow trench of depth-width ratio is inserted silica layer, in shallow trench, fill up silica layer fully with repeatedly deposition step with different ozone/tetraethoxysilane flow-rate ratio.It should be noted that in each deposition step, ozone is about definite value to the flow ratio of tetraethoxysilane, so formed silica layer all there is separately carbon content concentration in each deposition step.In addition, because the tetraethoxysilane flow of each deposition step is relatively higher than last time deposition step, so the silica layer of back more formation also has higher carbon content, and the silica layer that forms earlier has lower high-temperature shrinkage amplitude, situation described in second embodiment of the invention than back former.Therefore, the silica layer of the formed shallow groove isolation layer of the present invention inside can have layering carbon content difference and the different feature of high-temperature shrinkage amplitude.
Please refer to table, table one is presented at the formed silica layer quality of SACVD technology of different ozone/tetraethoxysilane flow-rate ratio, wherein the ozone of A technology/the tetraethoxysilane flow-rate ratio is greater than B technology, and the ozone of B technology/tetraethoxysilane flow-rate ratio is greater than C technology.As shown in Table 1, formed silica layer has best quality in the A technology of ozone/tetraethoxysilane flow-rate ratio maximum, its high-temperature shrinkage amplitude is minimum, also have wet etching speed ratio (the wet etch rateratio lower to thermal oxide layer, WERR), and the high-temperature shrinkage amplitude of the formed silica layer of C technology of ozone/tetraethoxysilane flow-rate ratio minimum is the highest, and has higher wet etching speed ratio.
Table one
Please referring again to table two, table two is the comparison sheet of the surface selectivity of different ozone/tetraethoxysilane silica layer that flow-rate ratio forms.Ozone/tetraethoxysilane flow-rate ratio is greater than 18 formed silica layers, for Si, SiN, SiON and SiO as shown in Table 2
2Have average surface selectivity Deng material, therefore have better quality.
Table two
| O 3/ TEOS flow-rate ratio | ＞18 | ＜18 |
| SiO 2/ Si surface selectivity ratio | 0.84 | 0.55 |
| SiO 2/ SiN surface selectivity ratio | 0.92 | 0.60 |
| SiO 2/ SiON surface selectivity ratio | 1.00 | 1.08 |
From the above, make width less than 65 nanometers or even shallow groove isolation layer less than 45 nanometers in, earlier form a silica layer film greater than 18 reacting gas with SACVD technology, can effectively overcome surface selectivity and fill out problem such as hole ability with ozone/tetraethoxysilane flow-rate ratio.Compared to prior art, the present invention is high ozone and the low tetraethoxysilane flow formation quality preferable first silica layer film of elder generation with fixed ratio, problems such as surface selectivity to be overcome or fill up the shallow trench of width minimum after, carry out one second silica layer depositing operation again, feeding has the firm discharge ratio but ozone/less reacting gas of tetraethoxysilane flow-rate ratio just can fill up second silica layer with fast speed in the shallow trench of other large-sizes.According to the inventive method, first silica layer in the shallow groove isolation layer has the characteristic of lower high-temperature shrinkage amplitude, and can overcome in the prior art that silica layer has problems such as cavity or impervious seam in the shallow trench, therefore can provide insulation effect good shallow groove isolation layer.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (21)
1. method of in groove, inserting silica layer, this method comprises:
Substrate is provided, and this substrate has a plurality of grooves;
Provide to have first ozone/reacting gas of tetraethoxysilane flow-rate ratio and carry out first depositing operation, in this substrate surface and those grooves, to form first silica layer comprehensively; And
Provide to have second ozone/reacting gas of tetraethoxysilane flow-rate ratio and carry out second depositing operation, on first silica layer, to form second silica layer, and this second ozone/tetraethoxysilane flow-rate ratio is less than this first ozone/tetraethoxysilane flow-rate ratio
Wherein this method is after groove minimum among those grooves is filled up fully by this first silica layer, just stops this first depositing operation.
2. the method for claim 1, wherein this first ozone/tetraethoxysilane flow-rate ratio is greater than 18.
3. the method for claim 1, wherein this second ozone/tetraethoxysilane flow-rate ratio is less than 18.
4. the method for claim 1, wherein this method also comprises providing to have the 3rd ozone/reacting gas of tetraethoxysilane flow-rate ratio and carry out the 3rd depositing operation, with formation the 3rd silica layer on this second silica layer, and the 3rd ozone/tetraethoxysilane flow-rate ratio is less than this second ozone/tetraethoxysilane flow-rate ratio.
5. the method for claim 1, wherein this method also comprises and carries out high density plasma CVD technology, to form the 3rd silica layer on this second silica layer.
6. the method for claim 1, wherein this method also is included in after this second depositing operation, carries out steam annealing technology.
7. the method for claim 1, wherein this first depositing operation comprises time aumospheric pressure cvd technology.
8. the method for claim 1, wherein this second depositing operation comprises time aumospheric pressure cvd technology.
9. method of making shallow groove isolation layer, it comprises:
Substrate is provided, and this substrate surface has first groove and second groove, and the width of this first groove is less than the width of this second groove;
Carry out first depositing operation, to form first silica layer, it is inner and be located at the inwall and the lower surface of this second groove to fill up this first groove respectively; And
Carry out second depositing operation, to form second silica layer, fill in this second groove and be covered on this first silica layer, the carbon content of this second silica layer is different from the carbon content of this first silica layer.
10. method as claimed in claim 9, wherein the carbon content of this first silica layer is less than the carbon content of this second silica layer.
11. method as claimed in claim 9, wherein this second silica layer fills up the part that is not provided with this first silica layer in this second groove fully.
12. method as claimed in claim 9, wherein this method also comprises and carries out the 3rd depositing operation, to form the 3rd silica layer, be covered on this second silica layer, and fill up the part that is not provided with this first silica layer and this second silica layer in this second groove fully.
13. method as claimed in claim 12, wherein the carbon content of the 3rd silica layer is greater than the carbon content of this second silica layer.
14. method as claimed in claim 9, wherein this method also comprises and carries out CMP (Chemical Mechanical Polishing) process, to remove this first silica layer and this second silica layer on this substrate surface.
15. method as claimed in claim 9, wherein this first depositing operation is to feed to have ozone/tetraethoxysilane flow-rate ratio greater than 18 reacting gas, to form this first silica layer.
16. method as claimed in claim 9, wherein this second depositing operation is to feed to have ozone/tetraethoxysilane flow-rate ratio less than 18 reacting gas, to form this second silica layer.
17. a semiconductor element, it comprises:
The semiconductor-based end;
At least one first groove and one second groove are located at this semiconductor-based basal surface, and the width of this first groove is less than the width of this second groove;
First silica layer, it is inner and be located at the inwall and the lower surface of this second groove to fill up this first groove respectively; And
Second silica layer is located in this second groove and is covered on this first silica layer, and the carbon content of this first silica layer is different from the carbon content of this second silica layer.
18. semiconductor element as claimed in claim 17, wherein the carbon content of this first silica layer is less than the carbon content of this second silica layer.
19. semiconductor element as claimed in claim 17, wherein this semiconductor element also comprises the 3rd silica layer, fills up the part that is not provided with first silica layer and this second silica layer in this second groove.
20. semiconductor element as claimed in claim 17, wherein this second silica layer fills up the part that is not provided with this first silica layer in this second groove fully, and this semiconductor element also comprises the 3rd groove, its size is greater than the size of this second groove, and the surface of the 3rd trench wall and bottom to core fills up this first silica layer, this second silica layer and the 3rd silica layer in regular turn.
21. semiconductor element as claimed in claim 17, wherein the carbon content of the 3rd silica layer is greater than the carbon content of this second silica layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100081102A CN100550343C (en) | 2007-01-26 | 2007-01-26 | Shallow groove isolation layer of semiconductor element and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100081102A CN100550343C (en) | 2007-01-26 | 2007-01-26 | Shallow groove isolation layer of semiconductor element and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101231967A CN101231967A (en) | 2008-07-30 |
| CN100550343C true CN100550343C (en) | 2009-10-14 |
Family
ID=39898304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100081102A Active CN100550343C (en) | 2007-01-26 | 2007-01-26 | Shallow groove isolation layer of semiconductor element and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100550343C (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5841306B2 (en) * | 2009-05-08 | 2016-01-13 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US8877602B2 (en) * | 2011-01-25 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms of doping oxide for forming shallow trench isolation |
| CN103187353A (en) * | 2011-12-29 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove isolation area |
| CN103794543B (en) * | 2012-10-31 | 2018-07-10 | 中芯国际集成电路制造(上海)有限公司 | Isolation structure and forming method thereof |
| CN105063576A (en) * | 2015-08-24 | 2015-11-18 | 沈阳拓荆科技有限公司 | Low-temperature film coating method using tetraethyl orthosilicate (TEOS) source |
| CN109148258B (en) * | 2017-06-16 | 2022-05-03 | 联华电子股份有限公司 | Method for forming oxide layer |
| CN107359136B (en) * | 2017-08-09 | 2018-10-02 | 睿力集成电路有限公司 | The fill method of isolated groove, the interstitital texture of equipment and isolated groove |
| CN110707036B (en) * | 2018-07-12 | 2022-03-08 | 联华电子股份有限公司 | Method for manufacturing semiconductor element |
| CN110265352B (en) * | 2019-06-24 | 2021-03-09 | 武汉新芯集成电路制造有限公司 | Method for forming shallow trench isolation structure and method for forming memory device |
| CN114334612B (en) * | 2022-03-14 | 2022-06-28 | 广州粤芯半导体技术有限公司 | Semiconductor device and method for manufacturing the same |
-
2007
- 2007-01-26 CN CNB2007100081102A patent/CN100550343C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101231967A (en) | 2008-07-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100550343C (en) | Shallow groove isolation layer of semiconductor element and preparation method thereof | |
| US10177222B2 (en) | Semiconductor device and method of fabricating the same | |
| KR100621888B1 (en) | Method of forming an isolation layer and method of manufacturing the fin type field effect transistor using the same | |
| KR101831936B1 (en) | Method for forming a thin film and method for manufacturing a semiconductor device by using the same | |
| US20070278576A1 (en) | Fin field effect transistor and method for forming the same | |
| US20020076947A1 (en) | Combined gate cap or digit line and spacer deposition using HDP | |
| US20060046426A1 (en) | Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry | |
| US11715666B2 (en) | Method of fabricating semiconductor device | |
| JP2010251654A (en) | Deposition method and manufacturing method of semiconductor device | |
| JP2006179860A (en) | Capacitor of semiconductor device and manufacturing method thereof | |
| US20080020582A1 (en) | Method of forming an opening in a semiconductor device and method of manufacturing a semiconductor device using the same | |
| KR20030038438A (en) | FILLING SUBSTRATE DEPRESSIONS WITH SiO2 BY HDP VAPOR PHASE DEPOSITION WITH PARTICIPATION OF H2O2 OR H2O AS REACTION GAS | |
| CN101546726B (en) | Method for isolating semiconductor devices with use of shallow trench isolation method | |
| CN107464813A (en) | A kind of semiconductor devices and preparation method thereof and electronic installation | |
| JP2008112826A (en) | Manufacturing method of semiconductor device | |
| CN110310952B (en) | Semiconductor device and method of manufacturing the same | |
| US20080268612A1 (en) | Method of forming isolation layer in semiconductor device | |
| US7358190B2 (en) | Methods of filling gaps by deposition on materials having different deposition rates | |
| JP2001035916A (en) | Method of forming shallow trench element isolations | |
| US10083857B2 (en) | Method for manufacturing semiconductor device with trench isolation structure having plural oxide films | |
| CN112802746B (en) | Trench structure and forming method thereof | |
| US7018905B1 (en) | Method of forming isolation film in semiconductor device | |
| CN100399539C (en) | Technique for forming gapless shallow channel insulation area by subatmospheric CVD method | |
| CN115799160A (en) | Semiconductor structure and method for making the same | |
| KR100244493B1 (en) | Method for fabricating isolation structure of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |