CN100539048C - A kind of method of making quasi double grids MOSFET transistor - Google Patents
A kind of method of making quasi double grids MOSFET transistor Download PDFInfo
- Publication number
- CN100539048C CN100539048C CNB2007101762924A CN200710176292A CN100539048C CN 100539048 C CN100539048 C CN 100539048C CN B2007101762924 A CNB2007101762924 A CN B2007101762924A CN 200710176292 A CN200710176292 A CN 200710176292A CN 100539048 C CN100539048 C CN 100539048C
- Authority
- CN
- China
- Prior art keywords
- gate electrode
- layer
- dielectric layer
- manufacture method
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of method of making quasi double grids MOSFET transistor.The present invention makes the special advantage of quasi double grids MOSFET transistor method: the heavy doping of the inner sacrifice region of source-drain area is to be injected by the ion that is mask to realize with the gate electrode, and the separator in source-drain area and accurate tagma is to form with medium by the heavily doped layer and the filling of corroding this sacrifice region, and therefore the source-drain area and the gate electrode (comprising accurate gate electrode) of made mosfet transistor device have self aligned feature naturally; And, the corrosive liquid of high selectivity has been adopted in the corrosion of heavily doped region, so corrosion process can stop at light doping section automatically.This autoregistration and stop certainly technology make the repeatability of transistor preparation process and evenly performance satisfy the big needs of producing, thereby have wide prospect in industrial application.
Description
Technical field
The present invention relates to a kind of method of making quasi double grids MOSFET transistor.
Background technology
Since the integrated circuit invention, its performance steadily improves always.The raising of performance mainly is to realize by the size of constantly dwindling integrated circuit (IC)-components.At present, the characteristic size of integrated circuit (IC)-components (MOSFET) has narrowed down to nanoscale.Under this yardstick, the various basic restrictions with reality begin to occur, and make the development that is based upon the integrated circuit technique on the silicon planar CMOS technology just suffer unprecedented challenge.It is generally acknowledged that through great efforts, the CMOS technology still might be advanced to 20 nanometers even 10 nm technology node, but after 45 nanometer nodes, traditional planar CMOS technology will be difficult to further develop, new technology must produce in good time.In the middle of the various new technologies that proposed, the double grid MOS device technology is considered to be hopeful most the technology that is applied after inferior 45 nanometer nodes.Compare with the single gate device of tradition, double-gated devices has stronger short channel and suppresses ability, better subthreshold characteristic, higher driving force and can bring higher current densities.
Dual-gate MOS transistor structurally has two kinds of forms usually, and a kind of is to be representative with FinFET, it is characterized in that the surface of the tagma (channel region) of device perpendicular to silicon chip, and another kind is a plane, it is characterized in that tagma (channel region) still is parallel to the surface of silicon chip.The former, self-registered technology easily realizes, but device performance and uniformity are relatively poor, and the latter can make device obtain high-performance and high uniformity, but complicated process of preparation, self-registered technology is difficult to realize.
Summary of the invention
The purpose of this invention is to provide a kind of autoregistration and make the method for quasi double grids MOSFET transistor.
The manufacture method of accurate double gate SOI MOS transistor provided by the present invention comprises the steps:
1) selecting soi wafer for use is backing material, and the semiconductive thin film of photoetching and etching soi wafer is formed with the source region, the gate dielectric layer of growing on this active area then;
2) deposit gate electrode layer and sacrificial dielectric layer, photoetching and etching form gate electrode figure; Gate electrode figure except that covering channel region, also nappe contact area;
3) with the gate electrode figure be mask, the ion implantation doping that concentration is reverse Gradient distribution is carried out in the subregion of the semiconductive thin film of soi wafer, form heavily doped region, as the sacrifice layer in the source region and the drain region of described accurate double gate SOI MOS transistor;
4) deposit sacrificial dielectric layer once more on gate electrode figure, Hui Kehou forms protective layer at gate electrode figure; With described protective layer is that mask corrosion falls the gate dielectric layer that described gate electrode figure both sides appear, and the semiconductive thin film surface of the soi wafer of described gate electrode figure both sides is exposed;
5) the semiconductive thin film surface portion of the described soi wafer of corrosion stops when eroding to described heavily doped region;
6) heavily doped region in the semiconductive thin film of the described soi wafer of selective etching, the corrosion nature stops when arriving light doping section, forms the cavity;
7) deposit dielectric is filled the cavity that corrosion forms, and returns and carves the dielectric of removing the surface;
8) erode behind the protective layer of gate electrode figure again at the gate electrode figure film dielectric layer of growing;
9) ion implantation doping source region, drain region and gate electrode, and with angle-tilt ion method for implanting doped channel regions; Then, return to engrave and state film dielectric layer to form the gate electrode side wall;
10) photoetching and be etched away the gate electrode part of nappe contact zone, and carry out ion implantation doping and make the light doping section under it be transformed into heavily doped region;
11) enter the conventional cmos later process, comprise silicon deposit passivation layer, opening contact hole and metallization, wherein, an additional metal electrode links to each other with the body contact zone by contact hole, and gate electrode becomes to be as the criterion; Like this, make described accurate double gate SOI MOS transistor.
Wherein, the described gate dielectric layer of step 1) is a silicon dioxide layer; Step 2) described gate electrode layer is a polysilicon layer, and described sacrificial dielectric layer is a silicon nitride layer; The described dielectric of step 7) is a silicon dioxide; The step 8) film dielectric layer is a silicon dioxide layer.The implanted dopant of step 3) ion implantation doping is BF
2, the injection energy is 20-50KeV, implantation dosage is (2-8) * 10
14Cm
-2The used corrosive liquid of step 6) selective etching is the mixture of hydrofluoric acid, nitric acid and acetate, and wherein, the volume ratio of hydrofluoric acid, nitric acid and acetate is 1:2.5-3.5:7.5-8.5, is preferably 1:3:8.The implanted dopant that the step 9) ion injects is an arsenic, and the injection energy is 33-60KeV, and implantation dosage is (1-5) * 10
15Cm
-2The implanted dopant that the step 9) angle-tilt ion is injected is BF
2, the angle of inclination of injection is 15-60 °, injects energy 45-70KeV, implantation dosage (1-8) * 10
14Cm
-2The implanted dopant that the step 10) ion injects is BF
2, inject energy 5-20KeV, implantation dosage (1-6) * 10
15Cm
-2
Advantage of the present invention and good effect:
The double grids MOSFET of plane has higher device performance, but the total right and wrong of manufacture method are self aligned.This has hindered the application of plane double grids MOSFET on ULSI.The present invention makes the outstanding advantage of mosfet transistor method: concave structure buried insulating layer forming process has autoregistration and stops feature certainly, thereby makes that device making technics is a self aligned technology.This be because: the initial heavy doping of source-drain area inside is to be injected by the ion that is mask to realize with the gate electrode, and the separator of source-drain area and accurate gate electrode forms with medium by corroding this heavily doped layer and filling, and therefore made device has source-drain area and the self aligned feature of gate electrode (comprising accurate gate electrode) naturally; And the corrosion of heavily doped region is a high selectivity, can stop at light doping section automatically.This autoregistration and stop feature certainly, make plane double-gated transistor and integrated circuit preparation technology's thereof repeatability and evenly performance satisfy big requirement of producing, have wide prospect in industrial application.
Description of drawings
Fig. 1 is the structural representation of used SOI material;
Fig. 2 is the process sequence diagram that active area forms;
Fig. 3 is the process sequence diagram that gate electrode forms;
Fig. 4 is the process sequence diagram of reverse grade doping in the source-drain area body;
Fig. 5 is the process sequence diagram that the grid protective layer forms;
Fig. 6 is the low process sequence diagram of the low-doped silicon layer of corrosion;
Fig. 7 is the process sequence diagram of the highly doped silicon layer of selective etching;
Fig. 8 is the process sequence diagram of filling the silicon groove;
Fig. 9 is that the gate electrode side wall forms for the second time, leak in the source and the process sequence diagram of grid ion implantation doping and the formation of body contact zone;
Figure 10 is the metallization schematic diagram.
Among the figure:
1-silicon substrate, 2-oxygen buried layer
3-monocrystalline silicon membrane 3 '-highly doped silicon
4-body contact zone, 5-gate dielectric layer
6-silicon nitride sacrifice layer, 7-polysilicon
7 '-polysilicon, 8-silicon groove
9-cavity, 10-silicon dioxide
11-silicon dioxide side wall, 12-source region
14-source, 13-drain region electrode
15-drain electrode, 16-grid metal electrode
17-accurate gate electrode 110-passivation layer
120-contact hole
Embodiment
One specific embodiment of manufacture method of the present invention comprises Fig. 1 to Figure 10, and wherein Fig. 1 is the profile of used backing material, among Fig. 2-Fig. 9, (a) be front view, (b) being profile along front view AA ' direction, (c) is the profile along front view BB ' direction, and shown processing step is as follows:
1, as shown in Figure 1, used soi wafer is by silicon substrate 1, and oxygen buried layer 2 and monocrystalline silicon membrane 3 are formed.The crystal orientation of monocrystalline silicon membrane 3 is (100), and thickness is 50-250nm, is initially light dope.
2, shown in Fig. 2 (a is a front view, and b is the profile along front view AA ' direction, and c is the profile along front view BB ' direction), photoetching and etching single crystal silicon film 3 are formed with the source region, and active area contains one contact zone 4.Then active area is carried out thermal oxidation, at surfaces of active regions and lateral growth silicon dioxide gate dielectric layer 5, its thickness is 0.5-3nm.
3, (a is a front view as Fig. 3, b is the profile along front view AA ' direction, and c is the profile along front view BB ' direction) shown in, successively deposit gate electrode polysilicon layer 7 and silicon nitride sacrificial dielectric layer 6, the thickness of polysilicon layer 7 is 50-250nm, and the thickness of silicon nitride layer 6 is 20-40nm.Adopt the sacrificial dielectric layer 6 and the polysilicon layer 7 of conventional cmos technology photoetching and the deposit of etching institute, form gate electrode figure.Gate electrode figure except that covering channel region, also some nappe contact area 4;
4, (a is a front view as Fig. 4, b is the profile along front view AA ' direction, c is the profile along front view BB ' direction) shown in, with gate electrode 7 figures is mask, the ion implantation doping of reverse Gradient distribution (retrograde, promptly surface concentration is low, the bulk concentration height) is carried out in subregion to the monocrystalline silicon membrane 3 of soi wafer, form heavily doped region 30, this will be as the sacrifice layer in the source region and the drain region of transistor device.Implanted dopant is BF
2, the injection energy is 20-50KeV, implantation dosage is (2-8) * 10
14Cm
-2
5, (a is a front view as Fig. 5; b is the profile along front view AA ' direction; c is the profile along front view BB ' direction) shown in; then deposit one deck silicon nitride and use back quarter (etch-back) technology be the silicon nitride side wall of 25-150nm at gate electrode 7 both sides formation width again; this side wall is formed gate electrode protective layer 6 with the top silicon nitride of previous growth, is the exposed part that mask corrosion falls silicon dioxide gate dielectric layer 5 with this protective layer.
6, (a is a front view as Fig. 6, b is the profile along front view AA ' direction, c is the profile along front view BB ' direction) shown in, be mask with the silicon nitride protective layer, adopt reactive ion etching (RIE) method corrosion monocrystalline silicon membrane 3 to heavily doped region 30 to form silicon groove 8; Corrosion depth is 30-100nm.
7, shown in Fig. 7 (a is a front view, and b is the profile along front view AA ' direction, and c is the profile along front view BB ' direction), adopt the selective etching technology to corrode the heavily doped region 30 of the monocrystalline silicon membrane 3 that manifests.Etchant solution is hydrofluoric acid, nitric acid and acetate mixture, fills a prescription to be 40%HF:70%HNO
3: 100%CH
3COOH mixes with volume ratio 1:3:8.Because the high selectivity of corrosive liquid, corrosion will stop at the light doping section of monocrystalline silicon membrane 3 automatically, form the silicon groove cavity 9 up to gate electrode 7 boundaries.
8, shown in Fig. 8 (a is a front view, and b is the profile along front view AA ' direction, and c is the profile along front view BB ' direction), adopt CVD method deposit layer of silicon dioxide, in order to fill the silicon groove cavity 9 that corrosion produces, form insulating barrier 10, return again and carve the silicon dioxide of removing the surface.
9, (a is a front view as Fig. 9; b is the profile along front view AA ' direction; c is the profile along front view BB ' direction) shown in; fall the silicon nitride protective layer 6 of all gate electrode tops and both sides with hot phosphoric acid corrosion; and be the silica dioxide medium layer of 5-20nm with CVD another thickness of growing; and as resilient coating; the silicon layer part of twice ion implantation doping gate electrode 7 and gate electrode 7 both sides; form the source region 12 and the drain region 13 of dope gate electrode 7 and device; dopant is an arsenic; inject energy and be respectively 33 and 60KeV, implantation dosage is (1-5) * 10
15Cm
-2Then, with angle-tilt ion injection technique doped channel regions, the bottom 3 ' that makes channel region is for highly doped from gate electrode 7 both sides, and implanted dopant is BF
2, the angle of inclination of injection is 15-60 °, and the injection energy is 45-70KeV, and implantation dosage is (1-8) * 10
14Cm
-2At last, the anisotropic dry etch ion injects resilient coating with formation silicon dioxide side wall 11, and the source region 12 of device and drain region 13 are exposed on the surface of gate electrode 7 both sides.According to circumstances, source region, drain region can adopt epitaxy method to form the source-drain structure of raising.Then, photoetching and etching are removed the polysilicon 7 ' part that covers tagma contact area 4, and carry out boron ion implantation doping, make the light doping section under it be transformed into heavily doped region, and implanted dopant is BF
2, inject energy 5-20KeV, implantation dosage (1-6) * 10
15Cm
-2
10, (a is a front view as Figure 10, b is the profile along front view AA ' direction, c is the profile along front view BB ' direction) shown in, enter the conventional cmos later process at last, the phosphorosilicate glass layer that comprises deposit one deck 200-500 nanometers is as passivation layer 110, by photoetching and this passivation layer of etching respectively in the source 12, leak 13 and the contact zone opening contact hole 120 of grid 7, accurate grid 4, and the aluminium film of deposit one deck 400-800 nanometers and photoetching and etching form source electrode 14, drain electrode 15 and metal electrodes such as gate electrode 16 and accurate gate electrode 17.Accurate gate electrode 17 links to each other with heavily doped tagma 3 ' by contact hole 120 and heavily doped body contact zone 4.So far, just made the accurate double gate SOI MOS transistor of a described n raceway groove.
The preparation process of p channel device, except that doping condition should be adjusted accordingly, making step was identical.Wherein in the step 4, implanted dopant is As, and the injection energy is 25-50KeV, and implantation dosage is (2-7) * 10
14Cm
-2In the step 9, the source region 12 of gate electrode 7 and device and the implanted dopant in drain region 13 are BF
2, injecting energy and be respectively 33 and 60KeV, implantation dosage is (1-5) * 10
15Cm
-2Then, with angle-tilt ion injection technique doped channel regions, the bottom 3 ' that makes channel region is for highly doped from gate electrode 7 both sides, and implanted dopant is As, and the angle of inclination of injection is 15-60 °, and the injection energy is 45-70KeV, and implantation dosage is (1-8) * 10
14Cm
-2In step 9, the implanted dopant of contact area 4 is As equally, injects energy 10-20KeV, implantation dosage (1-5) * 10
15Cm
-2
Claims (8)
1, a kind of manufacture method of accurate double gate SOI MOS transistor comprises the steps:
1) selecting soi wafer for use is backing material, and the semiconductive thin film of photoetching and etching soi wafer is formed with the source region, the gate dielectric layer of growing on this active area then;
2) deposit gate electrode layer and sacrificial dielectric layer, photoetching and etching form gate electrode figure; Gate electrode figure except that covering channel region, also nappe contact area;
3) with the gate electrode figure be mask, the ion implantation doping that concentration is reverse Gradient distribution is carried out in the subregion of the semiconductive thin film of soi wafer, form heavily doped region, as the sacrifice layer in the source region and the drain region of described accurate double gate SOI MOS transistor;
4) deposit sacrificial dielectric layer once more on gate electrode figure, Hui Kehou forms protective layer on gate electrode figure; With described protective layer is that mask corrosion falls the gate dielectric layer that described gate electrode figure both sides appear, and the semiconductive thin film surface of the soi wafer of described gate electrode figure both sides is exposed;
5) the semiconductive thin film surface portion of the described soi wafer of corrosion stops when eroding to described heavily doped region;
6) heavily doped region in the semiconductive thin film of the described soi wafer of selective etching, the corrosion nature stops when arriving light doping section, forms the cavity;
7) deposit dielectric is filled the cavity that corrosion forms, and returns and carves the dielectric of removing the surface;
8) erode behind the protective layer of gate electrode figure again at the gate electrode figure film dielectric layer of growing;
9) ion implantation doping source region, drain region and gate electrode, and with angle-tilt ion method for implanting doped channel regions; Then, return to engrave and state film dielectric layer to form the gate electrode side wall;
10) photoetching and be etched away the gate electrode part of nappe contact zone, and carry out ion implantation doping and make the light doping section under it be transformed into heavily doped region;
11) enter the conventional cmos later process, comprise silicon deposit passivation layer, opening contact hole and metallization, wherein, an additional metal electrode links to each other with the body contact zone by contact hole, and gate electrode becomes to be as the criterion; Like this, make described accurate double gate SOI MOS transistor.
2, manufacture method according to claim 1 is characterized in that: the described gate dielectric layer of step 1) is a silicon dioxide layer; Step 2) described gate electrode layer is a polysilicon layer, and described sacrificial dielectric layer is a silicon nitride layer; The described dielectric of step 7) is a silicon dioxide; The step 8) film dielectric layer is a silicon dioxide layer.
3, manufacture method according to claim 1 is characterized in that: the implanted dopant of step 3) ion implantation doping is BF
2, the injection energy is 20-50KeV, implantation dosage is (2-8) * 10
14Cm
-2
4, manufacture method according to claim 1 is characterized in that: the used corrosive liquid of step 6) selective etching is the mixture of hydrofluoric acid, nitric acid and acetate, and wherein, the volume ratio of hydrofluoric acid, nitric acid and acetate is 1:2.5-3.5:7.5-8.5.
5, manufacture method according to claim 1 is characterized in that: the volume ratio of described hydrofluoric acid, nitric acid and acetate is 1:3:8.
6, manufacture method according to claim 1 is characterized in that: the implanted dopant that the step 9) ion injects is an arsenic, and the injection energy is 33-60KeV, and implantation dosage is (1-5) * 10
15Cm
-2
7, manufacture method according to claim 1 is characterized in that: the implanted dopant that the step 9) angle-tilt ion is injected is BF
2, the angle of inclination of injection is 15-60 °, injects energy 45-70KeV, implantation dosage (1-8) * 10
14Cm
-2
8, manufacture method according to claim 1 is characterized in that: the implanted dopant that the step 10) ion injects is BF
2, inject energy 5-20KeV, implantation dosage (1-6) * 10
15Cm
-2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101762924A CN100539048C (en) | 2007-10-24 | 2007-10-24 | A kind of method of making quasi double grids MOSFET transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101762924A CN100539048C (en) | 2007-10-24 | 2007-10-24 | A kind of method of making quasi double grids MOSFET transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101140888A CN101140888A (en) | 2008-03-12 |
| CN100539048C true CN100539048C (en) | 2009-09-09 |
Family
ID=39192759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007101762924A Active CN100539048C (en) | 2007-10-24 | 2007-10-24 | A kind of method of making quasi double grids MOSFET transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100539048C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101882594B (en) * | 2009-05-05 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Forming method of conductive plug |
| CN103151292B (en) * | 2011-12-07 | 2015-04-08 | 上海华虹宏力半导体制造有限公司 | Integrated method of raise source leakage structure complementary metal-oxide-semiconductor transistor (CMOS) and Bipolar device |
| CN103378129B (en) * | 2012-04-19 | 2016-03-23 | 中国科学院微电子研究所 | A kind of semiconductor structure and manufacture method thereof |
| CN104988504A (en) * | 2015-06-29 | 2015-10-21 | 华东光电集成器件研究所 | Silicon film etching solution with high P<+>/P<-> etching selection ratio |
-
2007
- 2007-10-24 CN CNB2007101762924A patent/CN100539048C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101140888A (en) | 2008-03-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0262294B1 (en) | A fabrication method for forming a selfaligned contact window and connection in an epitaxial layer and device structures employing the method | |
| CN100356528C (en) | Method for making MOS transistor with source-drain on insulating layer | |
| CN100356527C (en) | Method for making MOS transistor with source-drain on insulating layer | |
| JP3762136B2 (en) | Semiconductor device | |
| EP0302204B1 (en) | Vertical trench transistor/capacitor memory cell structure and fabrication method therefor | |
| CN100536092C (en) | Method for manufacturing fin-shaped field effect transistor by epitaxial process | |
| CN102738179B (en) | A kind of SOI strain SiGe CMOS integrated device and preparation method | |
| WO2014177045A1 (en) | Semi-floating gate device and manufacturing method therefor | |
| CN101777499B (en) | Method for self-aligned preparation of tunneling field-effect transistors (TFETs) on basis of planar technology | |
| CN102916048A (en) | Junctionless silicon nanowire transistor based on bulk-silicon material and method for manufacturing junctionless silicon nanowire transistor | |
| CN101005038A (en) | Method for producing field effect devices | |
| CN100440537C (en) | Partial consumption SOI MOS transistor and making method | |
| CN100539048C (en) | A kind of method of making quasi double grids MOSFET transistor | |
| CN108538911A (en) | L-type tunneling field-effect transistor of optimization and preparation method thereof | |
| CN100505185C (en) | Method of manufacturing a semiconductor device | |
| CN104253048A (en) | Production method of stacked nanowire | |
| CN100550326C (en) | The transistorized method of a kind of making FinFET | |
| CN100414714C (en) | MOS transistor with partial depletion SOI structure and producing method thereof | |
| CN100561752C (en) | A kind of preparation method of quasi dual-gate MOS transistor | |
| CN100479188C (en) | Manufacturing method of a body silicon MOS transistor | |
| CN106098783B (en) | A kind of fin formula field effect transistor and preparation method thereof | |
| CN100527371C (en) | Portion exhausted SOI MOS transistor preparation method | |
| CN1328795C (en) | Source/drain sink type ultrathin SOIMOS transistor and method for preparing IC | |
| CN102738161B (en) | The two strain mixing crystal face Si base BiCMOS integrated device of a kind of two polycrystalline and preparation method | |
| CN106298936A (en) | A kind of inverted trapezoidal top gate structure fin formula field effect transistor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHA |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 100871 PEKING UNIVERSITY, NO. 5, YIHEYUAN ROAD, HAIDIAN DISTRICT, BEIJING TO: 100871 NO. 5, YIHEYUAN ROAD, HAIDIAN DISTRICT, BEIJING |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20110215 Address after: 100871 Beijing the Summer Palace Road, Haidian District, No. 5 Co-patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Peking University Address before: 100871 Haidian District the Summer Palace Road,, No. 5, Peking University Patentee before: Peking University |