CN100536340C

CN100536340C - Frequency division method and frequency division counter

Info

Publication number: CN100536340C
Application number: CNB2005100352641A
Authority: CN
Inventors: 汤艺; 李波; 赵猛; 罗琨
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2005-06-10
Filing date: 2005-06-10
Publication date: 2009-09-02
Anticipated expiration: 2025-06-10
Also published as: CN1877997A

Abstract

The invention discloses frequency division method and frequency divisions counter to trace real-time frequency division signal of outer signal in the digital signal disposal domain, which comprises the following steps: A. adjusting number placing number of frequency division counter according to the control information of outer signal; B. synchronizing the counting sequence and outer signal; C. generating the frequency division signal through counter; making the frequency of frequency division signal and outer signal the same or integral times relationship. The invention can compensate time-delaying transmission.

Description

A kind of dividing method and frequency counter

Technical field

The invention belongs to digital processing field, relate in particular to a kind of dividing method and the frequency counter that can adjust phase place in real time.

Background technology

Frequency splitting technology is used for certain given signal is carried out frequency division, to obtain needed frequency.Frequency splitting technology is used wide, relates to all electronic applications substantially.In the clock system of communication network, just applied to a large amount of frequency splitting technologies, generate the reference clock signal of various frequency and phase place.

Generally be to be undertaken from frequency division in the prior art by frequency counter, function such as frequency counter has zero clearing, reset, difference along with the different of reset values or zero clearing condition, can produce the signal of various frequencies voluntarily, output signal frequency and phase place all are independently, with the frequency and the phase-independent of outer signals.

Because the counting sequence of frequency counter and outer signals are irrelevant, the phase place of fractional frequency signal and outer signals are incoherent, therefore can only produce the signal of various frequencies voluntarily, can't realize carrying out the phase place adjustment according to outer signals, follow the tracks of the outer signals phase place.

Summary of the invention

The objective of the invention is to solve and to realize in the prior art carrying out the phase place adjustment to follow the tracks of the problem of outer signals phase place according to outer signals.

In order to realize purpose of the present invention, the invention provides a kind of dividing method, generate the fractional frequency signal of real-time tracking outer signals phase place, described method comprises the steps:

A. adjust the setting value of frequency counter according to the outer signals control information;

B. utilize the counting sequence and the outer signals edge of described setting value adjustment frequency counter synchronous;

C. utilize described counting sequence to generate fractional frequency signal, the frequency of described fractional frequency signal and outer signals is identical or become integral multiple to concern.

Described outer signals control information comprise at least according to outer signals along generate along the pulse towards control signal, and constant time lag information.

Described outer signals control information further comprises the insertion delayed data that is staggered in outer signals edge and self-clock signal edge.

In order to realize goal of the invention better, the present invention further provides a kind of frequency counter, be used to generate the fractional frequency signal of real-time tracking outer signals phase place, described frequency counter comprises:

Adjust the control device of the setting value of frequency counter according to the outer signals control information;

Utilize described setting value to adjust the counting sequence of frequency counter and outer signals along synchronous 1 counter that adds;

Utilize described counting sequence to generate the fractional frequency signal maker of fractional frequency signal, the frequency of described fractional frequency signal and outer signals is identical or become integral multiple to concern.

Described control device comprises:

Detect the outer signals edge, generate along the pulse towards control signal along detector;

Along the pulse put several setting value memories towards control signal and constant time lag information to adding 1 counter according to described.

Described control device further comprises:

Selection make outer signals along and the self-clock signal along the delay value memory of the delay value that staggers;

Described delay value is inserted into the time-delay inserter of outer signals.

The present invention becomes with extraneous frequency when necessarily concern in self frequency, makes the phase place of phase place real-time tracking outer signals of fractional frequency signal, has overcome that adjustment phase time of the prior art is grown, inefficient problem.

Description of drawings

Fig. 1 is suitable for exemplary system figure of the present invention;

Error-detecting waveform schematic diagram when Fig. 2 is the edge alignment;

Fig. 3 is the waveform schematic diagram that phase place was adjusted when among the present invention alignd in non-edge;

Fig. 4 is the waveform schematic diagram that phase place was adjusted when among the present invention alignd in non-edge;

Fig. 5 is the waveform schematic diagram that phase place is adjusted among the present invention;

Fig. 6 is the waveform schematic diagram that phase place was adjusted when among the present invention alignd in the edge;

Fig. 7 is along the pulse towards the generation schematic diagram of control signal among the present invention;

Fig. 8 is the structure chart of frequency counter among the present invention.

Embodiment

In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.

As shown in Figure 1, in communication system,, adopt the mode of backup that the operation of system is protected usually,,, provide required data and clock as mainboard or master server etc. by main equipment in order to improve reliability of system operation.Alternate device can work independently on the one hand as backup, needs to write down the state of main equipment on the other hand, switch to the main equipment pattern and use when main equipment breaks down, thereby the operation of the system of assurance is unaffected.The frequency that an importance of alternate device record master status is the alternate device clock and the frequency and the phase place of phase place and main equipment clock will be consistent, so the Clock dividers of alternate device need overcome various delay time errors and adjusts self clock phase in real time with tracking main equipment phase place.

Alternate device realizes from frequency division that by frequency counter the frequency of fractional frequency signal becomes certain relation with the frequency of outer signals, and frequency is identical or become integral multiple to concern.

Because there is certain time-delay in outer signals when arriving alternate device, when existing the outer signals of time-delay to arrive alternate device the ambiguity of phase place may cause and alternate device self-clock signal along the situation of alignment, have bigger phase error if do not handle the fractional frequency signal that will make generation this moment with the actual signal that requires.As shown in Figure 2, so-called " along alignment ", be meant that outer signals in " set up and keep window " on alternate device self-clock edge saltus step has taken place, this moment alternate device exist along the high-low level of the outer signals that collects by self-clock uncertain, thereby the time that causes detecting the outer signals edge error in a work clock cycle is arranged.

The fractional frequency signal of alternate device is controlled by the counting sequence of frequency counter, utilize outer signals along the setting value of adjusting frequency counter in real time in the present invention, thereby adjust the counting sequence of frequency counter, make counting sequence and outer signals along synchronously, like this on the fractional frequency signal real-time tracking that generates according to counting sequence the outer signals edge.

Because outer signals arrives the time-delay of alternate device and fixes, whether align when utilizing this delayed data to analyze outer signals arrival alternate device with alternate device self-clock signal edge, as one embodiment of the present of invention, detect outer signals along with system self-clock signal along under the situation of not aliging, frequency counter detects the outer signals edge, and is inner along the pulse towards control signal along generating with outer signals, the setting value of control counting, adjust counting sequence, the generation of control fractional frequency signal.When no outer signals, the set and the reset operation of frequency counter are same as the prior art, can operate as normal to guarantee circuit self.

When outer signals, outer signals is put number along the set end of control frequency counter to frequency counter, and frequency counter interrupts original counting, continues counting from new setting value basis, thereby make fractional frequency signal follow the tracks of the phase place that goes up outer signals, finish the phase place adjustment.Wherein, the rising edge of outer signals different numerical value that counting sequence is adjusted to are decided according to delay time and system clock cycle that outer signals arrives alternate device.

See Fig. 3, the rolling counters forward value is the high level (fractional frequency signal) in 5 o'clock one 2 cycles of output.When needs are followed the tracks of the outer signals phase place, the outer signals rising edge, promptly inner " edge " pulse control signal control counting situation that generates has been carried out the counting sequence adjustment, the sequential relationship of counting sequence and outer signals is changed and and finished after the Phase Tracking the same, after finishing Phase Tracking among the figure, next bat count value along control wave is 1, the counting sequence adjusted value is 1 when then adjusting phase place, still be to produce the high level in one 2 cycle at 5 o'clock in the rolling counters forward value, on the adjusted fractional frequency signal real-time tracking phase place of outer signals.

Fig. 4 shows the waveform schematic diagram that above-mentioned phase place is adjusted, and 1,2 represents outer signals, the fractional frequency signal delay time with respect to same rising edge clock respectively among the figure, and 1 and 2 difference is little, illustrate that the fractional frequency signal tracking gone up the phase place of outer signals.

Detect outer signals along with system self-clock signal along under the situation of aliging, frequency counter inserts time-delay, makes outer signals edge after the time-delay and self-clock signal along staggering.Outer signals edge after detecting constant time lag then and inserting time-delay, with outer signals along and constant time lag, insertion delayed data control the setting value of frequency counter simultaneously, the generation of frequency counter control fractional frequency signal, thereby finished transmission delay is compensated and follow the tracks of phase place, realized the phase place adjustment.

See Fig. 5, the rolling counters forward value is the high level (fractional frequency signal) in 5 o'clock one 2 cycles of output.When needs were followed the tracks of the outer signals phase place, the rising edge control counting situation of outer signals had been carried out counting sequence and has been adjusted to 2, still is the high level in 5 o'clock one 2 cycles of generation in the rolling counters forward value.As can be seen from the figure, on the adjusted fractional frequency signal real-time tracking phase place of outer signals, Fig. 6 shows the waveform schematic diagram of above-mentioned adjustment.

Fig. 7 shows along the pulse the generation schematic diagram towards control signal, and alternate device high frequency clock clk deposits one to outer signals signal and claps and obtain signal_ff, obtains along the pulse towards control signal ctrl when signal=1 and signal_ff=0.When along alignment, outer signals signal herein is meant the outer signals of inserting after delaying time (be with constant time lag and insert time-delay), when align in non-edge, refers to the outer signals with constant time lag.

Fig. 8 shows the formation structure of the frequency counter 100 among the present invention.

Delay value memory 101 receive extraneous input whether along aligned signal, outer signals along with the self-clock signal when aliging, select delay value, make outer signals edge and self-clock signal edge stagger, and delay value is input to time-delay inserter 102 and setting value memory 103.

Time-delay inserter 102 receives outer signals, and whether whether the outer signals insertion of input is delayed time according to external world's input along the aligned signal decision, when outer signals along with the self-clock signal during along aligned signal, time-delay inserter 102 receives the delay value of delay value memory 101 inputs, signal inserts time-delay to external world, and the outer signals that will insert after the time-delay is input to along detector 104.

Detect the signal edge of the outer signals after not having time-delay or inserting time-delay along detector 104, produce along the pulse towards control signal, to be input to setting value memory 103 respectively and add 1 counter 105 towards control signal along the pulse, setting value memory 103 is according to the constant time lag (for example walking wire delay) of outer signals, the delay value of delay value memory 101 input and along detector 104 inputs along the pulse towards control signal, adjust setting value, setting value is input to adds 1 counter 105.

Add 1 counter 105 according to along detector 104 input along the pulse towards the setting value of control signal and 103 inputs of setting value memory, adjust counting sequence, make counting sequence and outer signals along synchronously, and export the counting sequence signal to fractional frequency signal maker 106, fractional frequency signal maker 106 generates fractional frequency signal according to the counting sequence signal controlling, and the fractional frequency signal that generate this moment can real-time tracking outer signals phase place.

From as can be known above-mentioned, the present invention adopts frequency counter to follow the tracks of the method on outer signals edge, follows the tracks of outer signals for the first time along the setting value of determining frequency counter, and the counting rule of frequency counter is just decided, thereby the phase place of fractional frequency signal is determined immediately, is finished the real-time adjustment of phase place.

The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims

1, a kind of dividing method, the fractional frequency signal of generation real-time tracking outer signals phase place is characterized in that described method comprises the steps:

C. utilize described counting sequence to generate fractional frequency signal, the frequency of described fractional frequency signal and outer signals is identical or become integral multiple to concern,

Wherein, described outer signals control information comprise the constant time lag of described outer signals and make outer signals along and the self-clock signal along the insertion delayed data that staggers.

2, dividing method as claimed in claim 1 is characterized in that, described outer signals control information also comprise according to outer signals along generate along the pulse towards control signal.

3, a kind of frequency counter is used to generate the fractional frequency signal of real-time tracking outer signals phase place, it is characterized in that described frequency counter comprises:

Adjust the control device of the setting value of frequency counter according to the outer signals control information, wherein said outer signals control information comprise the constant time lag of outer signals and make outer signals along and the self-clock signal along the insertion delayed data that staggers;

4, frequency counter as claimed in claim 3 is characterized in that, described control device comprises:

5, frequency counter as claimed in claim 4 is characterized in that, described control device further comprises: select to make outer signals along and the self-clock signal along the delay value memory of the delay value that staggers; Described delay value is inserted into the time-delay inserter of outer signals.