CN100533703C - Technique for evaluating a fabrication of a semiconductor component and wafer - Google Patents

Abstract

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Description

Be used to assess the technology of semiconductor element and wafer manufacturing

Related application

The application requires the exercise question submitted on August 25th, 2003 to be the priority in No. the 60/497th, 945, the interim U.S. Patent application of " Apparatus andMethodfor Fabric ationProcess Characterization "; And propose on April 15th, 2004, exercise question is the priority in No. the 60/563rd, 168, the interim United States Patent (USP) of " System and Method for Evaluating A Fabrication of aSemiconductor Component and Wafer ".The full content of above-mentioned priority application is hereby expressly incorporated by reference.

Technical field

The present invention relates to the manufacturing of semiconductor element, and more specifically, relate to the method that the assessment element is made.

Background technology

Semiconductor element, for example microprocessor is all formed by height integrated circuit (IC).Usually, these elements are manufactured by processing semiconductor wafer (for example silicon or GaAs).Wafer can be manufactured, makes transistor, switch element and other elements (for example resistor, capacitor, wiring layer etc.) be printed and form preset pattern, configuration and position.In case wafer is by processing and passivation (preventing the infringement of environment) fully, it can be cut into independently crystal grain, is bundled on the carrier, and stands final test and characterization.

The semiconductor device manufacturing is the rapid and complicated process of multistep.A plurality of steps are performed.The manufacture process that is used for wafer (and so independent semiconductor element) comprises that execution carries out such step with named order and with ad hoc fashion, makes the transistor of the independent semiconductor element (for example chip) that is formed for comprising wafer and expectation pattern, form and the structure of other integrated circuit components.Each procedure of processing requires to use overdelicate instrument and technology.Therefore, expect the quality of continuous monitoring manufacture process usually.If encounter problems in the mill (for example flaw and/or process skew), and detect problem very soon, the producer can adopt remedial measures.

In general, in the front and back that wafer is exposed fully, there is the technology of two kinds can detect the problem that is caused by design and/or manufacturing.One kind is to take place after finishing the semiconductor element manufacturing sequence, this under the scheduled operation condition to entire wafer (or chip) functional test and/or execution performance test on the critical circuit of device (at wafer scale or packaged chip).Another kind occurs in the manufacture process order, relies on some parameter of measuring on the testing wafer in these some technology.These parameter lists reveal or are indicating in addition in manufacture process the result of may problem or never expecting.These parameters can be determined that light and electron beam technology for example comprise draws together spectrum ellipsometry, bounce technique and critical dimension scanning electron microscopy (CD-SEM) by light and electron beam technology.In one approach, measure with verification certain physical parameter, for example grid width, gate oxide thickness, interconnect width and dielectric height.Under this method, generally the test structure in the wafer scribe district to be measured, said drawn area is near the active area of chip.

Currently used other technologies rely on measures physics flaw on the semiconductor wafer that is produced by manufacture process.The example of these technology comprises piecemeal etching, residue test (via residue), grid stringer (gate stringer), chemico-mechanical polishing is corroded and other handle the method for flaw.These measurements can detect by light detection or observation, electron beam detection and light or electron beam and finish.By carrying out after these measure, the defective and the flaw that form in the wafer manufacturing can be examined out, are isolated and are classified, perhaps otherwise detected and analyze.These measurements can cover entire wafer usually, and the drawn area of adjacent chips active area is foreclosed.

In addition, currently used additive method makes wafer stand the electrical testing of special test structure, special test structure is arranged on the drawn area or part and part to the wafer that is not used to final products of wafer, or to not being used or being used for final products and the wafer handled is fully tested crystal grain.This detection all is that the Mechanical Contact of online by using (in the manufacturing) test probes realizes usually.

Existing method has a lot of shortcomings.In these shortcomings, some technology may need to destroy semiconductor element, perhaps what some failure to have less value in the indication manufacture process in, perhaps have unexpected consequence.In addition, traditional inspection and detection technique have very high error rate, and this high error rate is because the real defective of electric mark occurred not staying, and noise occurs, and these are that relatively poor signal to noise ratio by very little defective causes.Also has can not the calculate to a nicety real final electrical feature of device under test or chip of these technology.And existing electrical inspection technology is lost time very much, and therefore cost costliness, and can not use these technology to study the large area region of wafer in the mode of routine.

In addition, the use test structure provides less information for the element in the active area chip area of wafer in drawn area.For example, known dividing regions departs from the micro-loading that is caused by the variation of the pattern density in the active area of wafer, and similarly, dividing regions is unsuitable for forecasting the variation in the chip that is caused by the Local treatment variation.And in chip incision process, the drawn area of wafer is removed, and the manufacturing that therefore is unsuitable for being used for measuring the back.

Exist many electronics on-line testing methods to come the quality and the integrality of monitoring ic manufacture process.These methods are used the measurement that obtains from the wafer of part processing based on the performance of the complete integrated circuit of prediction.For example, the thickness of oxide-film can be determined by the elliptical polarized light mensuration on the wafer.In addition, the method for measurement of above-mentioned parameter also can be used in the specific critical device parameters of determining directly to be embedded into manufacture process.For instance, can use threshold voltage to determine the doping grade of diffusion.Measurement to these parameters is all carried out in each stage of part processed wafer.In typical method, especially physics relevant with process and electrical quantity execution parameter are measured, and in being positioned at the wafer dividing regions, carried out on the structure.The example of parameter measurement comprises the measurement that transistor threshold voltage and no current leak.In measuring process, electricity and procedural test constant voltage (DC) or small signal (AC) also are applied on the precalculated position on the wafer with activation and pass device architecture on a plurality of discrete locations of wafer in the score layer.In a particular technology, contrast by DC circuit parameter value and desired value group test, come the integrality of checking procedure.

Except more above-described shortcomings, the result of electric on-line testing method is not suitable for the characterization parameter.For example any specific deviation that observes all may be that deviation by a plurality of machined parameters causes in the parameter of integrated circuit.In addition, traditional DC mensuration is not the indicating device of fireballing circuit performance well.The more important thing is that as mentioned above, the measurement of these parameters is limited in the drawn area of wafer, this also is a problem.

Rely on large tracts of land test structure electrical testing technology, being normally used for understanding can not be from the definite whole grain effect of wafer scribe test structure.The all crystal grains or the patent (US6 of patent (US6,281,696 and US6,507,942); 449,749, US6,475; 871 and US6,507,942) the most of crystal grain in all is devoted to measured test structure, to detect and the isolated manufacturing deficiency that causes low yield or difference performance.These crystal grain substitute products chip crystal grain are manufactured and physically surveyed to produce machining control information.The manufacturing deficiency class is useful at random though these technology are to isolating, and they are the replacement method of directly measuring in the chip.Be integrated into the active area of chip, these methods are all had any problem or may not, this is because they require the physics contact to be electrically connected so that set up, and because need the big area in school to be defined for the circuit of isolate defects, perhaps in some cases, need the bigger real situation of area to obtain the fabricating low-defect-density defective.Alternatively, also have certain methods to depend on that still similarly structure is arranged (US6,553,545) for crystal grain after encapsulating in the layout of active die region inside similar structures.In this is used, structure or tested by encapsulation, perhaps the destructive malfunction analytical technology is used with the crystal grain that postpones encapsulation to understand device.When crystal grain is positioned on the wafer, can realize measuring, the system defect of being engaged in for current application changes, and the processing module with excessive chip internal variation can be determined, and does not need the physics contact, and enough I are to be integrated into the inside of chip.At last, other application (US6,686,755) after deliberation use little activation signal and detect and be used for the detection chip function, chip places traditional carrier and provides power and excitation by tradition contact Detection Techniques.

Description of drawings

Figure 1A is the simplification calcspar that obtains the system of the appreciation information made about wafer in the embodiments of the invention.

Figure 1B shows the position on the wafer that can carry out the performance parameter measurement.

Fig. 1 C shows thereon and can carry out the chip that performance parameter is measured for the purpose of the manufacturing of assessing wafer and/or chip.

Fig. 2 shows in the embodiments of the invention, the method that the procedure of processing in the assessment chip manufacturing is carried out.

Fig. 3 shows corresponding to the manufacturing characteristic relevant with the measurement of performance parameter in the chip, procedure of processing that can be evaluated.

Fig. 4 shows and processes the calcspar how responsive test structure can be used to assess the wafer manufacturing in an embodiment.

Fig. 5 shows and is used to use the responsive test structure of processing to determine a kind of method about the appreciation information of wafer manufacturing among the embodiment.

Fig. 6 shows and is used to use the responsive test structure of processing to determine the another kind of method about the appreciation information of wafer manufacturing among the embodiment.

Fig. 7 A shows among the embodiment, is used for the schematic diagram of aspect of the suitable member circuit element of CMOS technology.

Fig. 7 B shows the responsive test structure of the processing of being made up of identical components, and wherein member can be formed on the active part of semiconductor element.

Fig. 7 C and Fig. 7 D show the use of the delay-sensitive element in comprising the circuit of one or more phase convertors.

Fig. 8 is the representative instance how method shown in Fig. 6 is performed.

Fig. 9 A to Fig. 9 E shows the different circuit elements on the active area that can be formed on semiconductor element, is used for time of delay or phase shift, to amplify the performance sensitivity of these circuit elements to procedure of processing.

Figure 10 shows the responsive test structure of processing on the active area that can be formed on semiconductor element, and is used for time of delay or phase shift, with the deviation between amplification and related CD SEM measurement and the electric CD measurement.

Figure 11 shows the chip of assembled part manufacturing and the scheme of test structure, and wherein test structure can be used to measure the performance parameter relevant with manufacturing step.

Figure 12 shows a kind of when being used in test signal that is used for test structure and power producing in the chip from wafer, the method for use test structure.

Figure 13 A shows the circuit that is used to regulate the input voltage that is produced by external power source.

Figure 13 B shows and is used to regulate the input voltage that is produced by external power source, feeds back to the circuit of lasing light emitter simultaneously.

Figure 14 A and Figure 14 B show an embodiment, and wherein thermoelectric mechanism and laser or the coupling of other energy sources produce power or test signal to cause in the chip.

Figure 15 shows and is used to detect and measure electroactive system from assigned address on the wafer according to embodiment.

Figure 16 provides and has been used to according to an embodiment of the invention to cause and measures other details from the electroactive device of the assigned address of chip.

Figure 17 shows the chip that is set up according to embodiments of the invention.

Figure 18 has described a kind of method that is used for the device of operational example such as Figure 15 to 16 description according to one embodiment of present invention.

In the accompanying drawings, identical drawing reference numeral is represented identical or similar substantially element or technology.In order easily to discern the discussion of any particular element or technology, top digit refers to the number of the accompanying drawing of element when being introduced for the first time in drawing reference numeral.Based on the detailed description that provides at this, those skilled in the art can make necessary modifications to accompanying drawing.

Embodiment

General introduction

Embodiment described here is provided for analyzing system, method, structure and the other technologies that wafer is made.Especially, embodiment described here provides from having the power (power of colocated, energy), a plurality of positions on the wafer of test and detection architecture, comprise in the active area of the individual dies of forming wafer, obtain information about the manufacturing implementation status of wafer.Information with a kind ofly do not influence the availability of the wafer that is used for subsequent wafer processing and/or the noncontact of applicability, non-invasive mode obtains.The result and the attribute of manufacturing step or order are included in other the local machining deviations that take place in the active area of crystal grain or in the wafer, can detected, assessment and/or analyzed.

Serviceability parameter evaluation and the manufacturing of analysis wafer

In order to assess the manufacturing of chip or wafer, embodiments of the invention provide the interior method of measurement of chip of certain performance relevant parameter (performance parameter) for the manufacturing of assessment chip or wafer.Chip is equivalent to the product of formation when the individual dies at the wafer of making the later stage wafer is cut or separates.Most of chip all comes from the wafer of cutting.Crystal grain is equivalent to the zone between the line of wafer.The active area of crystal grain is the place at active, discrete and integrated circuit element place, and these elements are the resident places of chip partial function.

In one embodiment, from or based on the intragranular precalculated position at the chip of wafer or wafer observe electroactive, explain the specific performance properties parameter.The certain electric activity may be excited to these appointed positions and performance parameter or itself and just have this activity, and wherein performance parameter is interpreted as or based on the activity relevant with the characteristic of chip, crystal grain or wafer.The measurement variation of a plurality of method of measurement is known as " variation ".In an embodiment, determine that the performance parameter of assigned address has showed the characteristic of crystal grain.The measurement of a plurality of method of measurement changes, and wherein measure the position that is collected and be called as " variation in space ", and very useful to identification or fingerprint, particular process step usually.Under special circumstances, the one or more processing during the characteristic of performance parameter performance device, crystal grain, drawn area or chip, these characteristics are made owing to wafer.

Because performance parameter has described the attribute of high-quality performance chip in detail or has given the credit to the characteristic of one or more steps in the manufacturing sequence, so the measurement performance parameter provides effective information for the assessment chip manufacturing.For example, according to embodiment, the measurement of performance parameter can join with the part correlation of crystal grain, and the part of this crystal grain has the specific unnecessary or unexpected result by the performance generation of manufacturing step or order.Other character of this result and chip are fully isolated, thereby, can be identified owing to the specific manufacturing step of performance parameter value or order.In addition, can determine about how to carry out the step of identification or the information of order by one or more performance parameter values in the chip.

According to an embodiment, electroactive from the wafer appointed positions be excited.Electroactive can being excited makes the performance parameter of being explained have the value that is exaggerated when the attribute that is produced by one or more specific manufacturing steps exists or lacks.As what will be described, be used to excite electroactive a kind of mode to be to use test structure special, the processing sensitivity to handle test signal.Multiple class electroactive can be excited and/or measure and assess manufacturing, for example comprises light signal, photosignal and radiofrequency signal.In an embodiment, adopt this test structure can produce performance parameter value, these parameter values almost must depend on one or more manufacturing steps without exception, or depend at least manufacturing step not on the same group.Other embodiment can use known non-test structure (for example, the product device), produces, sends or show result's particular community as certain the physics attribute that is presented on the chip active area.

According to another embodiment, electroactive assigned address on wafer may be intrinsic, and performance parameter can be determined that wherein intrinsic activity is relevant with the manufacturing of wafer by this intrinsic activity.For example, the sensitive measurement device can be used for from the circuit element measurement performance parameter of using in the general operation of chip, and wherein the spatial variations of these tested performance parameters is associated with particular step or order.In these cases, that be associated with measurement or identical specific manufacturing step or order can be the results who is caused or influenced by the mode that particular process step in making or execution are made.

Figure 1A shows the calcspar of embodiments of the invention.In Figure 1A, sniffer 102 will encourage 101 to be used for the assigned address of wafer 110, and in response to excitation 101, detect and measure from electroactive 105 of assigned address.Wafer 110 can be the part manufacturing or make fully.Electroactive available following one or more methods detect: photoelectricity photon effect and signal are (for example, hot electron photo emissions, electric charge induction-electric absorption or electric rectification), voltage-contrast phenomenon, electromagnetic signal (for example radio frequency or induced signal etc.), and/or other are by still less contacting signal or the effect that medium detects.As will be described, electroactive 105 corresponding to one or more chips-characteristic property parameter 106.The performance parameter 106 that can detect and measure can be examined, analyzes and assess, so that determine result, variation or the characteristic performance of the quality of chip, crystal grain and/or wafer, or make one or more particular procedures, step or the procedure of processing order of wafer 110.The performance parameter 106 of testing and measuring also can detect by the design crystal grain that causes of variable density or the variation on the wafer diverse location.According to an embodiment, performance parameter detect electroactive before, performance parameter produces about some but the information of not all manufacture process.Therefore, such embodiment makes that impelling process to change the specific fabrication process that can be identified and assess becomes possibility.

In one embodiment, sniffer 102 produces electroactive 105 by the assigned address with signal or energy beam sensing wafer 110.In response to the excitation 101 of using, the element of appointment can produce or show electroactive 105 on the wafer 110.Resulting electroactive 105 are interpreted as one or more performance parameters 106 by sniffer 102.Be included in measurement of grid conversion speed, propagation delay, phase shift and/or conversion speed that the assigned address of wafer 110 measures etc. from the example of electroactive 105 performance parameters that can explain.

Can analyze so that performance parameter 106 is associated in proper order with particular procedure, manufacturing step and manufacturing step, comprise the instrument or the module that are used to carry out processing and step.This can relate to specific manufacturing step or the attribute of order or result's change in location or the spatial variations of analyzing on the wafer area (active area that comprises individual dies).In an embodiment, performance parameter can be used to obtain to be used to assess the appreciation information 107 of result, execution, effect or the performance of manufacturing step, order or process, comprises how approaching the result of the manufacturing step of prediction or process is.Appreciation information 107 can be with the performance parameter value on the diverse location of wafer 110 relatively, determine that the variation of the space of performance parameter values or other classes is gone up in wafer 110 zones and other are changed to the basis.More specifically, the analysis of appreciation information 107 and other performance parameter values can relate to the comparison at the performance parameter value of diverse location, between the position of these diverse locations in identical chips, on the interior location of different chips, in drawn area and the one or more chip, and other comparison point on the wafer 110.

Instrument 109 such as computer system, module or software/system's programming/module can be used to analyze, and determines appreciation information 107 from performance parameter 106.Instrument 109 is parts of data acquisition system.Especially, the characteristic of analyzing performance parameter 106 and one or more manufacturing step 108 or process is associated.For example, instrument 109 can be associated performance parameter 106 with manufacturing step, and wherein manufacturing step produces and cause the existence of the variation of the existence of resistance coefficient and capacitance variations in the metal or grid length and channel shape.In addition, the identification of manufacturing step 108 also can relate to employed module of manufacturing step or the instrument carried out.Equally, other appreciation information 107 are indicated or are produced in the identification of the manufacturing step 108 consistent with the performance parameter analysis, and these information can be used to determine the each side of whole manufacturing process.Appreciation information 107 comprises any data, or data itself or combine with other data or information, and these data provide the information that how to be performed about one or more manufacturing steps.Therefore for example, appreciation information 107 can have statistical in itself, changes or before how certain manufacturing step or process to be performed, a plurality of wafers were manufactured in the process that shown by the Distribution Statistics that appreciation information produced.Cite an actual example again, can determine from the appreciation information 107 in a zone of a wafer how special manufacturing step or order are performed.Appreciation information 107 also comprises calibration information, can be used to obtain the observation of other appreciation information.Because appreciation information 107 can be from wafer 110 any position (be included in Figure 1B to be described, be positioned at the active layer of crystal grain) obtain, provide process to change and the embodiment that influence shortcoming of the interior device of chip can more easily be identified.Yet appreciation information 107 can also be used to discern the manufacturing step that is executed correctly, so that isolate problematic manufacturing step by getting rid of.

According to embodiment, how Figure 1B shows the analysis manufacturing in the zones of different of wafer 110.In Figure 1B, suppose that wafer 110 is in part and makes state.Wafer 110 comprises a plurality of drawn area 121 that define a plurality of crystal grain 127.A cutting groove 125 can form in the drawn area between the row and column of crystal grain 127 121.Each crystal grain 127 can comprise active layer 128 (for example chip) and passive region 129.Line 123 is as the boundary line between the adjacent grain 127.

According to embodiment, electroactive can being observed at the assigned address of wafer 110.These assigned addresses comprise scribing position 134, crystal grain raceway groove position 135, active crystal grain position 136 and passive crystal grain position 138.Scribing position 134 can be fully near the active layer 128 of corresponding crystal grain, and after wafer 110 was cut, these scribing position 134 fell into the residue grain material of chip.In an embodiment, appointed positions can also comprise the active crystal grain position 148 of peripheral silicon crystal grain element 146.Periphery die element 146 normally " abandons " element, because they have stoped repertoire operation as the crystal grain of chip in the existence of Waffer edge.Yet, use peripheral die element 146 to come the measurement performance parameter at this embodiment that describes, and assess manufacturing, be particularly useful for position near the wafer 110 of wafer perimeter.

In an embodiment, electroactive 105 is detected and explain as the performance parameter of locational Special Category of the active crystal grain position 148 that comprises scribing position 134, crystal grain raceway groove position 135, active crystal grain position 136, passive crystal grain position 138 and/or peripheral crystal grain 146.More different performance parameter values is to determine appreciation information.For example, between the active crystal grain 136 of same die 127, compare performance parameter value, to determine this regional process variation at wafer 110.Between the active crystal grain position 136 of different crystal grain, between the passive crystal grain position 138 of identical or different crystal grain and the active crystal grain position 136 and between the scribing position 134, can compare performance parameter value.In addition, for evaluation of alignment information or for other purposes, between scribing position 134 and adjacent active crystal grain position 136, also can carry out certain comparison of performance parameter value.The active crystal grain position 158 of periphery crystal grain 146 has shown at wafer 110 peripheral specific manufacturing steps how to be performed.Sometimes, process changes more serious in wafer perimeter.

In an embodiment, electroactive 105 is sensed so that (for example be exaggerated from the electroactive performance parameter that obtains, amplify or filtering) mode occur in the level that is detected and detects, the one or more steps during the specific position place wafer 110 that depends primarily on the measurement performance parameter is made.Therefore, the potential manufacturing characteristic of representing single crystal grain 150 and/or wafer 110 by electroactive 105 performance parameters of determining.On particular wafer 110, have hundreds and thousands of even more such measurement.In addition, this measurement is also reusable after finishing one or more manufacture processes.Also can be in identical definite position duplicate measurements performance parameter.Further, compare with the method in past, performance parameter is determined that by the electroactive measurement at 138 places, active crystal grain position of wafer 110 physical measurement and/or the electrical testing implemented in the non-active area of this/crystal grain outer with line chips or chip are different.Present technique allows direct measurement performance parameter in the active area of single crystal grain, and under the contrast, the physical measurement in active layer has indirect relation with the final performance of device and chip at most, thereby makes that processing is loaded down with trivial details.Embodiment is associated performance parameter and variation thereof with treatment step of isolating and/or order.

Assessment and analytical performance parameter having deferent value, information, sign or the identification of making the particular procedure of wafer 110 with acquisition.These processes may produce, for example, and a kind of special physics or electric attribute, and this attribute that is present in specific position can be reflected by performance parameter value.In one embodiment, each performance parameter value of having determined depends primarily on the performance of manufacturing step or process.Alternatively, make between performance parameter and the known manufacturing characteristic relevant and be associated with specific manufacturing step, process or technology.The performance parameter value at diverse location place on the wafer is analyzed to determine to understand how the manufacturing characteristic exists on certain chip.This understanding just can be used for assessing relevant manufacture process, comprising how deterministic process is carried out, its produces result how, being complementary etc. of also having whether these results expect.

Fig. 1 C shows how performance parameter value is used to assess the manufacturing of crystal grain and/or its wafer in the scope of crystal grain.In Fig. 1 C, crystal grain 150 includes source region 152 and passive region 154.Different types of performance parameter can especially be identified and measure in the active area 152 on crystal grain 150.These are different with some conventional methods, and conventional method is measurement performance parameter in line just.In an embodiment, each class performance parameter is corresponding to one or more manufacturing steps, process or characteristic.Certain kinds by induction crystal grain specified location electroactive, inhomogeneous performance parameter can be measured from wafer crystal grain 150.

By determining to come the analytical performance parameter from the variation between a plurality of performance parameter values of crystal grain 150 diverse locations measurement.In one embodiment, determine spatial variations for the performance parameter that is arranged in the certain kinds in the active area 152.In another embodiment, analyze and to relate to more inhomogeneous performance parameter, for example produce electroactive and have the situation of different designs and/or configuration by being arranged in structure on the crystal grain 150.For example, the spatial variations of the value of a class performance parameter is used to determine the information about the manufacture process that is used to form crystal grain 150.

Further, inhomogeneous performance parameter measurement can be used to set forth the performance map of crystal grain 150.Value or existence that this figure can be the difference manufacturing characteristic on the crystal grain 150 provide indication.Equally, this figure can be before or after its each manufacturing be finished, for a plurality of processes of crystal grain 150 or wafer manufacturing provide appreciation information.

In the position of the measured crystal grain 150 of performance parameter value or its wafer 110, can be provided with mechanism, structure and/or integrated circuit component, be used for coming the amplification performance parameter measurement based on one or more characteristics of manufacturing step or process.In one embodiment, the value of a performance parameter mainly is manufacturing step or the particular subset from manufacturing step.

In the embodiment as shown in Fig. 1 C,, select the assigned address of crystal grain 150 for measurement performance-relevant parameter.Assigned address all is labeled in set (A ₁-A _n, B ₁-B _N... D ₁-D _NDeng) in.(grain is as A in each set ₁-A _n), measure the property parameter, wherein each performance parameter in the set is based on the electroactive of certain kinds.Because to having common design and characteristic, and/or the structure that produces identical manufacturing step correlation measures, so each set of performance parameter is corresponding to a class.Especially, every class performance parameter can be measured from electroactive, electroactive sensed and be designed to other steps the order on emphasize a manufacturing step or the order.In fact, electroactive sensed or be designed to be independent of other manufacturing steps, therefore almost depend on (if possible, an a plurality of in addition) manufacturing step or order exclusively from the electroactive performance parameter of explaining of this kind.In a simple example, common test structure can be arranged in the active area 152 of crystal grain 150, and is energized and/or other signal activations.What produce is electroactive as set A ₁-A _nIn one of performance parameter detected and measure.In one embodiment, if the manufacturing of wafer is unified, the value between the performance parameter in set does not have recognizable difference so.Yet,, between performance parameter value, may have the recognizable difference form of gradient or trend (perhaps with) so if exist spatial manipulation to change.Performance parameter value from the passive region 154 of crystal grain 150 can be used, and in particular for other purpose, for example is provided for the baseline or the calibration value set of the performance parameter value in the active area 152.

In an embodiment, each performance parameter value electroactive explanation that can produce by induction and/or the specific test organization of emulation.This structure can be designed as show with crystal grain 150 on one or more manufacturing steps or directly related in proper order performance parameter.In addition, the design of ad hoc structure can be not have other manufacturing steps or dependence in proper order in the pair set in the value of shown performance parameter.

For example, a class formation that produces specific activation signal can be used to determine the specific performance properties parameter value, and this value is known to be exaggerated or outside the scope of the value that specific manufacturing characteristic exists (for example, electric capacity or the grid length above specific quantity changes).In identical example, structure Design can minimize or filter the influence of the characteristic of other manufacturing steps or order, because characteristic may have the less relatively or negligible influence of performance parameter value.Another example for example, when have on the chip extra metal or too much metal cause electric capacity the time, performance parameter corresponding to the device of the high value that is used to measure from generation measure electroactive.

Relation between the manufacturing step of performance parameter and identification or the order is to be based upon on the basis of changes of performance parameters of measurement.This variation can influence the variable of the performance of specific die 150 based on space, speed or other.

Can provide many advantages as the described embodiment of Figure 1A-1C.In these advantages, determine that the performance parameter that is closely related with manufacturing step can make engineer, designer and production management personnel identify those problematic manufacturing steps (comprising instrument used in the step and module) before manufacturing is finished.Used process and technology was studied and improves based on effective and efficient manner during this just made and makes.For example, the flaw in one manufacture process can be detected and be modified between the manufacturing of single wafer.Each next wafer may become better.For example, in the past, some chips on the wafer that design defect causes putting goods on the market usually are the low performance product, rather than are put goods on the market with the performance rate of expectation.This has reduced the value of single chip considerably.In conventional method, the assessment of wafer manufacturing is that cost is big, the process of length consuming time, also often requires a plurality of samples to be used for statistical analysis.Compare, the chance that embodiments of the invention make " in the air " of manufacturing issue detect and proofread and correct specific fabrication process before making another wafer becomes possibility.Although still need to use statistical analysis, embodiments of the invention to make that statistics will be to isolate specific fabrication process than former method faster speed.In addition, specified data from the crystal grain of wafer, therefore the problem in manufacture process can be detected and be understood better.Equally, monitoring, detect, isolate and analyze all online finishing, and in the process of correction, measurement and suitable adjustment, finish.

Fig. 2 shows the method for the manufacturing that is used for assessing in an embodiment of the present invention wafer, crystal grain or chip.The method of describing in conjunction with Fig. 2 can combine execution with the use of the performance parameter of measuring (as described in Figure 1A-Fig. 1 C).Similarly, be used to describe the suitable relation that is used to carry out this method with reference to the label among figure 1A-Fig. 1 C.

Beginning, in step 200, wafer is finished one or more manufacturing steps or process.Next, step 210 is provided at a plurality of position measurement performance parameters of wafer 110, comprises in the active area 152 of crystal grain 150.For example, sniffer 102 can be used at diverse location electroactive carrying out being measured in the chip.Such as the mechanism of test structure be designed or known displaying electroactive, can be placed on selectively in the crystal grain 150 from the confirmable performance parameter of this mechanism.Preassigned position in the liner of each element and/or output signal, performance parameter can by activate with energy, excitation and/or test signal such mechanism,, and in addition by noncontact electricity, photoelectricity and/or calutron from the precalculated position in each element and/or the output signal liner (pad) detect (measurements) electroactive come definite.

Step 220 is provided at the variable quantity of determining measured performance parameter value in the step 210.In one embodiment, this variation is a spatial variations, and can be applied to wafer 110 and crystal grain 150, comprises the active area 152 of crystal grain.The spatial variations of this value represent the universal performance parameter (such as, the output of common test structure, or from the detected emission of element on the certain chip) value is how from a position to another change in location, and no matter specified position be crystal grain inside or be distributed in a plurality of crystal grain and drawn area 121 between.Alternatively, variable quantity can be based on some other parameter, for example conversion speed or switching rate.

In an embodiment, the spatial variations of the performance parameter of measurement specific provides analysis tool with making relevant characteristic for isolating, and these parameter characteristics are unfavorable for and/or unexpected the chip performance that influences.About the intragranular analysis, the performance of each crystal grain can show as the function of a plurality of independent factors, and wherein each factor is based on the physical attribute of this crystal grain.The performance of manufacture process or order is the example that process changes, and the spatial variations physical attribute of crystal grain 150 or its wafer 110 is passed in its generation.

According to an embodiment, in the step 230, it is how manufactured that the process variation causes the space variable of certain physical properties on wafer 110 and/or the crystal grain 150 to be used to assess wafer 110.Performance parameter can be measured from being excited or being designed to amplify the electroactive of effect that particular procedure changes, and main the analysis provides as follows.Supposing has function F, the circuit performance P of outlines device.Performance P depends on a plurality of physical parameters, these parametric descriptions the geometry and the electrical properties of the material that in manufacturing sequence, uses.

(1) P＝F(L，W，T _OX，I _SDE，...)

Wherein, for example, L and W are respectively the grid length and the width of device, T _OXBe gate oxide thicknesses, and I _SDEIt is source electrode-drain epitaxial implantation dosage.P also depends on other parameters, and for example interconnect-parameter at this for simplicity, is omitted this parameter here.Manufacture process changes, and is equivalent to the variation of the physical characteristic that produced by this process or step, and this variation has caused the measurable variation among the P, after particular procedure step s and ad-hoc location 1 assess by single order:

(2) $\mathrm{\ΔP}{|}_{\mathrm{sl}}\≈\∂F/\∂L\·\mathrm{\ΔL}{|}_{\mathrm{sl}}+\∂F/\∂W\·\mathrm{\ΔW}{|}_{\mathrm{sl}}+\∂F/\∂T_{\mathrm{ox}}\·\mathrm{\Δ}{T}_{\mathrm{ox}}{|}_{\mathrm{sl}}+$

...

Wherein Be that F is to changing the response of X (L, W etc.) influence.

This equation shows, the variation of the device performance on crystal grain or chip can be expressed as the function of some attribute in the step of the process that wafer makes or result's variation, wherein changes after process steps or position or both evaluated.Cause the electroactive wafer 110 of measured performance parameter or the feature on the crystal grain 150, each can be selected and structure, and therefore the variation sensitivity of one of them parameter to particular procedure only arranged at every turn.This is balanced with regard to the variation that means the universal performance parameter, and perhaps changing with corresponding process at least has some direct relations.For example, process changes may be based on the position, because process can not be finished on the part of wafer or entire wafer equably.How execution in step also can change in one or more wafer manufacturings.

In an embodiment, step 230 comprises the attribute of manufacturing step or the spatial variations of characteristic and performance parameter is connected.This step is carried out before or after measuring.

In an embodiment, determine in step 240 whether the process variation of pointing out can be accepted.If process changes and can accept, in step 250, continue the manufacturing of wafer 110 so, and other manufacturing steps or process are performed.Can not be accepted if process changes, in step 260, take corrective action so.Corrective action can be the form of the process steps of repeating step 200.Alternatively, corrective action can be equivalent to stop to make or revising one or more execution that are used for the manufacturing step of subsequent wafer.Alternatively, corrective action can allow make to continue, but under monitor state, and the data that wherein are used to proofread and correct manufacturing are collected and analyze.Also have a kind of situation, wherein can be not detected up to the last manufacturing characteristic of flow process.Operating personnel can understand manufacturing step or the process that requires less modification, rather than are recycled and reused for the skew of next flow process, so this skew can be removed in advancing or reduce.

As the replacement of determining spatial variations, the class of the intragranular deviation of other classes can be identified.For example, embodiments of the invention can detect unacceptable result or the characteristic at the manufacturing step of entire wafer or uniform crystal particles distribution.

Fig. 3 is a calcspar, shows performance parameter that chip from wafer or intragranular measure and how to be used to be evaluated at some basic steps that semiconductor wafer uses in making or the realization of process.Although there are a plurality of other process classes of usually carrying out in the mill, Fig. 3 show photoetching treatment 310, etch processes 320, deposition processes 330, polishing 340 (for example, chemico-mechanical polishing) and in connect and handle 350.These handle a part that forms whole processing of using in the semiconductor wafer manufacturing.Processing as shown in Figure 3 can be performed and repeat with multiple different order according to specific manufacturing agreement or method.

According to embodiment, one or more manufacture processes or step can be associated with one or more characteristic 314-318 set.The manufacturing characteristic 314-318 that combines with two or more processes comprises from the result and/or the characteristic of the performance of one or more manufacturing steps, can overlap.No matter be consider separately or and other make characteristics and unite consideration, manufacturing process 314-318 can be corresponding to the characteristic or the aspect of wafer or crystal grain, wherein how the identification of characteristic or aspect is carried out with process or step that these manufacturing characteristics are associated, especially considers other manufacture processes.Measure definite characteristic 314-318 that makes from performance parameter.It is after assessing each process shown in Figure 3 by measurement from the electroactive performance parameter of the assigned address observation of wafer 110 (comprising crystal grain or scribe area).The assessment or analyze these performance parameter values with relevant with specific manufacturing characteristic.Making characteristic then just can be relevant with process or next process shown in Figure 3.

Measurement can perhaps be carried out after manufacturing is finished in the mill.In some cases, performance parameter can be measured after the ground floor layer metal deposition is to wafer 110.In one embodiment, the measurement of performance parameter is from finishing the ground floor metal level, and certain process is repeated to carry out after finishing.The process of iteration can obtain better output and performance so that operating personnel observation and monitoring in the changes of performance parameters of whole or each step of same position place process, and adopt remedial measures to adjust according to desired result in an embodiment.

In the example that Fig. 3 provided, the function of the set A of the single intragranular performance parameter (seeing Figure 1B) of wafer can be used to assess photoetching process 310 and the etching process 320 in the manufacturing.For example, the function of set A can produce a variable, value or other make the indication of characteristics, wherein makes characteristic and be the result of known photoetching process 310 and etching process 320.Similarly, the function of the set B of performance parameter also can be used to assess deposition process 330, and the function of the set C of performance parameter also can be used to assess polishing process 340, and the function of the set D of performance parameter also can be used to assess interconnection process 350.This description is an exemplary example, also has a lot of changes.For instance, a kind of performance parameter function might be used in combination one or more steps of assessing in the manufacturing with another function of another kind of performance parameter.How the result of specific function is correlated with and how provides the information of relevant specific fabrication process can be in the interior variation of scope from simple (value of specific manufacturing characteristic is exceeded or parameter changes not in the scope in appointment) to more complicated (consider the variation in another chip of making characteristic, a variation of making in the chip of characteristic is unacceptable).

Similarly, a plurality of functions also can be carried out on one group of performance parameter.In all embodiment as shown in Figure 3, be used in the measured value of the particular characteristic parameter at the intragranular diverse location place of wafer, such as the mathematical function of equation 2 so that the physical attribute (perhaps other manufacturing features) of a kind is separated from other kinds.Manufacturing feature also is separated with one of process shown in the corresponding diagram 3.The function of other classes also can.For example, function requires that tested performance parameter compares mutually on single crystal grain, and with wafer on the highest performance parameter value relatively.Another function requires one or more tested performance parameter sets (for example, A in the set A ₁) compare with known, a desired or desirable constant.If more undesirable (for example, having surpassed desired and/or acceptable scope), can determine appreciation information about corresponding step.

Two functions might be performed on a parameter sets to discern the appreciation information of similar and different process.For example, use algorithm to determine the composition of intragranular A, can assess photoetching process 310 with the parameter of set A.In addition, each performance parameter value is compared with the constant value of appointment and is used for favourable comparison.In this example, each appreciation information that can provide relevant specific fabrication process how to carry out in two functions.

Again for example, each changes of performance parameters in the class can be compared with the variation of baseline class.The baseline class is based on performance parameter, and these performance parameters do not show the variation of any specific manufacturing step or position.

The performed function of different performance parameter may be used on the analysis of crystal grain in the manufacture process or wafer scale (wafer-level).In order to be applied to the analysis of wafer scale, different crystal grain comes the measurement performance parameter value from the wafer 110.

How provide some special cases of performance parameter and they below is associated with process during wafer 110 is made.A performance parameter can be equivalent to the measurement of resistance coefficient.Chip performance may be by negative effect, for example, when wafer 110 is implemented polishings 340, causes the extra or disunity polishing in the high density area of crystal grain or prunes, and increases the effective resistivity of these intra-zone lines.In an embodiment, inner connection resistances rate is changed (especially high or low) responsive circuit element can be placed into or be positioned on the crystal grain, with the change in resistance of determining that chip or wafer be whether harmful.Can be observed to determine resistivity is how to produce output delay from the output of these circuit elements.More particularly, these elements can be placed into or be positioned at the zone that has high density and low-density circuit element, and more likely occur the variation of resistivity here.The output of the circuit element by measure increasing resistivity, can be then according to the electrical resistivity properties of chip or wafer, at least can the position of this circuit element or near isolate this element.Illustrate, one or more functions can be expressed with formula, function merge resistance coefficient spatial variations and/or the resistivity value of measuring compared with known or desired value.Emphasize to exist the fexible unit of unnecessary resistance to can be used to assess in the resistance how many unacceptable variations on active area, yet when being arranged on the crystal grain, should have conversion speed much at one.In this mode, show that the parameter of the resistivity of specific region on the crystal grain can provide about for example appreciation information of polishing process 340.

Another example of performance parameter is time delay and/or a conversion speed of measuring the circuit element with limit capacitance.The existence of harmful electric capacity has excessive influence to such circuit element.Be subjected to the conversion speed of circuit element of the very big influence of harmful electric capacity by measurement, can set up the composite value or the formula that are used to assess a process steps.For example, the metal deposition in the process 330 can be evaluated based on the conversion speed of the circuit element that is used to detect electric capacity.

Be used to assess the responsive test structure of process of manufacture process

The test structure of process sensitivity (PSTS) refers under the situation of in actuated wafer is made particular step and/or sequence of steps the structure to the electrical property sensitivity.In an embodiment, PSTS has very high sensitiveness to the performance or the result of a certain group of manufacturing step, and the performance or the result of any other manufacturing step seldom had sensitiveness.The sensitiveness of PSTS can expand to the electrical effect that is derived from one or more manufacturing steps, comprising but be not limited to resistance or electric capacity on the zone of wafer or crystal grain.The sensitiveness of PSTS also can expand to physical attribute, and such as grid width or grid length, this all stems from manufacturing step or by its influence.PSTS is configured, and it is electroactive to make that the existence of particular community in the chip come from manufacturing step or the wafer causes that PSTS output or displaying be associated with step or attribute.As described in the above-described embodiments, measured by measuring the electroactive performance parameter that can be used as, performance parameter can be analyzed to obtain the information of relevant manufacturing step, order or process.

Prior art provides the test structure in the drawn area that is placed on wafer, is measured with the testing apparatus of its Mechanical Contact, to produce and the relevant process relevant parameter of variable in the drawn area.Because known drawn area usually with interior the local of the active die region (the wafer outside of drawn area) of wafer change do not have much related, so the process that records in line variation follows the variation of the process in the active die region of wafer also not have great contact.The test structure that the crystal grain inside of attempting the use wafer was arranged in the past.Yet these methods depend on only could the use test structure after the wafer manufacturing is finished.Therefore, testing equipment can only change from the wafer measuring process of making fully.

Compare with the method in past, embodiment described here provides and can be placed on the active area that is in the crystal grain during make handling and the test structure in the key area.This test structure is energized in non-contacting mode, and shows or produce measurable electrical characteristics.When manufacture process is carried out, measure electroactive that test structure produced, with the manufacture process of assessment wafer.Equally, this structure also provides a kind of mechanism that is used for directly measuring the information of the effect of determining relevant intragranular processing variation.Embodiment described here also is provided as the process variation that the manufactured wafer of part is measured.This has greatly quickened the validity of particular step change information, and therefore when the utilization corrective action, these information also are available in manufacture process.

In one embodiment, some PSTS that are placed on the wafer are responsive for specific manufacturing step or order.Identical PSTS also may be insensitive to other steps in manufacture process.This negative effect is in order to isolate the electroactive manufacturing step that relies on of PSTS, so the electroactive of PSTS provides a mark clearly for manufacturing step or order.

Fig. 4 is the basic calcspar that PSTS 410 is shown according to embodiment.PSTS 410 can be designed as and make that to the manufacturing step of expectation or the certain sensitive of order be intrinsic attribute in this structure.In an embodiment, power 412 and test signal 414 are transfused to PSTS 410.Power signal 412 excitation PSTS 410, test signal 414 triggers PSTS simultaneously.In an embodiment, when power 412 and test signal 414 were provided, PSTS 410 was activated to produce output 422.In some cases, only depend on excitation or triggering PSTS also can activate PSTS 410.In an embodiment, when PSTS 410 is activated, can detect PSTS 410 inner subsidiary signal or the serial point-to-point signals 424 that produce.For example, signal 424 can be regarded the PSTS conducting as and disconnect element corresponding to the photon that is produced by the transistor of PSTS 410, and signal 422 is corresponding to the signal of telecommunication that adds up to from a plurality of nodes, and these nodes have reflected how retrofit testing signal 414 of PSTS.In output 422 and the point-to-point signal 424 one or two can be used to determine one or more performance parameters.The example of performance parameter comprises the conversion speed of transistor switch speed, circuit timing and interior transistor of PSTS and switch.Because the structure of PSTS 410, directly depend on the specific attribute relevant with performance parameter that point-to-point signal 424 is explained with manufacturing feature from exporting 422.For example, circuit element can be used to determine that how many subsidiary resistance are arranged on the wafer in the high density area dirt of metal deposition (for example, from) produces.Therefore, the output of circuit element also can be subjected to the influence of the harmful resistance of smallest number.

The output 422 of PSTS 410 and subsidiary signal 424 are used for obtaining or formulistic appreciation information 432, are used to assess the manufacturing of wafer or crystal grain.For example, if export 422 physical attributes that depend on the specific fabrication process result, can determine the correlation between a plurality of output valves and specific manufacturing step in the chip so.The variation that this correlation requires to determine output is maybe compared the centrifugal pump of output with expectation or known value.The variation of output can be used for deterministic process variation or skew.

As described below, a plurality of circuit and structure can be used for PSTS 410.The specific PSTS structure of one class can be corresponding to the PSTS structure with universal design.Other variations can be used to formulate a class PSTS structure.For example, a class PSTS structure is equivalent to assemble all settings, or specific manufacturing step, process or a result.The active area of many group PSTS structure distribution inside, especially crystal grain of crystal grain on a wafer and in the wafer.The interior several PSTS structures of particular group are used in the active area of crystal grain.

Fig. 5 shows a kind of method that the use test structure obtains relevant chip or wafer manufacturing information that is used for.This information can be used to determine whether specific manufacturing step or order just are performed, and desired result is provided.

Step 510 provides the position that is used for test structure to be identified.These positions can be corresponding on the wafer, on the crystal grain and the position in the discrete location in the active area of crystal grain, and also can be placed in the line that is used for comparison electrical testing structure, and wherein the electrical testing structure is generally used for the online test that electrically contacts.According to test structure and needs, a plurality of test structures can be distributed on the single crystal grain.

The initialization that step 520 provides wafer to make.This comprises the performance of processing, for example photoetching or etching.After ground floor metal (often being a kind of metal) deposition, conductivity is established to allow test structure to be energized and to test.

In step 530, the test structure of selection can be activated in specific manufacturing.Therefore, can be distributed in the test structure of selected activation in the different manufacturing steps.In this mode, test structure just can be analyzed certain process before manufacturing is finished and before certain step, order or the process repetition.Therefore, for instance, the problem that the flaw of some crystal grain on the wafer if first step metal deposition exerts an influence, some test structures can be activated and exist in first rather than second metal level to determine.

In step 540, the electroactive detected and explanation of the test structure of activation.In one embodiment, the electroactive performance parameter that is equivalent to, for example switching characteristic of single gate or structure as a whole (for example, time delay, conversion speed or walk time).Specific transistor and grid can be observed, or the output of structure as a whole can detected or measurement.

In the step 550, be used for assessing of the electroactive acquisition of the information of one or more steps that wafer makes or process from test structure.Appreciation information has various ways.For example, information can comprise a plurality of wafers make during statistics and formulism.Alternatively, these information can be used immediately.For example, not under the situation at tolerance interval, manufacturing can be stopped or subsequent wafer be regulated in the output of fc-specific test FC structure.In any case appreciation information can be used for adjustment and the correction to specific fabrication process, step or order.

According to embodiment described here, test structure is made up of electric activator switch structure and other devices.Under certain conditions, test structure can be showed electroactive, and electroactive measurement can be associated with the information about chip, crystal grain or wafer.Especially, electroactive can measured and usually being used based on a rule, it is relevant with the variation of discrete machine component in the design process of switch element that this rule is above-mentioned electric activator switch structure.Electroactive can be used as adds up to the output 422 of PSTS measured, perhaps is that each element of PSTS is measured point-to-pointly.

In one embodiment, test structure can be developed to the influence of amplifying grid length, but reduces the influence of other manufacturing steps.In the example that grid length changes, along with the increase of grid length, time-delay increases, and formula (2) is reduced to,

(3) $\mathrm{\ΔP}\≈\∂F/\∂L\·\mathrm{\ΔL}$

And the changes delta P that measures from this switching circuit, proportional with the process changes delta L relevant with grid length.

Fig. 6 shows and is used for the more detailed method how PSTS is developed and uses according to an embodiment of the invention.For given manufacturing class (for example MOS, CMOS, Bipolar, BiCMOS or the like), step 610 provides simple standarized component circuit element selected and/or design.Fig. 7 A shows the aspect of the suitable standarized component circuit element that is used for the CMOS technology, indication channel width (W) and length (L).It is apparent to those skilled in the art that simple elements also can be other manufacture process definition.This aspect can comprise: (i) one or more grids 702 (being made by n type that is used for CMOS and p transistor npn npn), can handle (for example length or width) from different dimensions, (ii) Guan Lian series resistance (R) 706 and electric capacity (C) 708, the (iii) tunable load of standarized component 709, or output, they can be regarded as the input of next device in the chain tape.One class suitable components circuit is the CMOS chain of inverters, and shown in Fig. 7 B, it shows the use of the CMOS inverter in the basic standard component circuitry.

Fig. 7 B shows PSTS, and it comprises and can be formed on the active area of crystal grain with relative power/excitation and output weld pad (pad), and is set to carry out Time delay measurement, and Time delay measurement is to the attribute of manufacturing step and sensitivity as a result.PSTS can be included in the circuit element with two or more inverters that are connected in series 710 in the realization shown in Fig. 7 B, and it is the cmos switch element.In an embodiment, each inverter 712 comprises a pair of complementary cmos transistor.More specifically, each inverter 712 comprises P channel transistor (PMOS) 722 and n channel transistor (NMOS) 724.In each inverter 712, nmos pass transistor 724 links together their grids separately as input with PMOS transistor 722, and drain electrode links together as output.The source electrode of PMOS transistor 722 is connected to the forward supply voltage, and the source electrode of nmos pass transistor 724 is connected to reverse electrical source voltage.The substrate forward bias of PMOS transistor 722 (especially at the forward supply voltage), and the substrate of nmos pass transistor 724 contact reverse biased (especially when reverse electrical source voltage).Technical function circuit (consult the U.S. patent No. 5,936,477 and disclose the ForwardBiased Source-Tab Junction that is used for low supply voltage) when can be implemented in the voltage that provides less.

Circuit element shown in Fig. 7 B be last form can be operated the example of electroactive structure that relates to the attribute of the manufacturing step of wafer or order with displaying.In addition, a series of inverter can be set up or be combined in than in the macrostructure with building process-sensitive structure.Such structure can provide the output of indication performance parameter.In an illustrated embodiment, this performance parameter can be the input of structure and the time-delay between the output, or some other the sign of transistor switch speed in this structure.For example, if come physics to change the transistor 722 of some reversers 712 in this structure by manufacturing step or order artificially, 724 switching speed, then this structure can be placed on different positions and/or different switch environment, make the different table of the time-delay between such two structures reveal the machining deviation of wafer in making.

In an embodiment, PSTS can comprise three root phases: input buffering 711, test phase 713 and output buffering 715.Test phase 713 includes exercisable circuit element.Input buffering 711 and output buffering 715 are controlled the transistorized conducting speed of test phase 713 by power controlling input.In case power is offered test structure, the transistor of test phase 713 shows design baseline and amplification characteristic, and these characteristics are relevant with the result of its manufacturing step measured or order.In an embodiment, for the test structure that describes below, input and output buffering 711,715th is identical.

In step 615, selected the attribute of manufacturing step or order.This attribute and particular characteristic relating to parameters, wherein this performance parameter is can be from the electroactive measurement of test structure.

The class that provides one or more test circuit modules to form in the step 620, wherein the test circuit module at least some classes is designed to provide performance parameter value, and this parameter value is exaggerated in order to illustrate how relevant with the existence of selected manufacturing step or order it is.Especially, the change list during the performance parameter of each test circuit module in special class is measured reveals the variation of making in the attribute corresponding.In one embodiment, with the measured change of the performance parameter of each test circuit module in the class and compare from the similar variation of the identical measurement of baseline structure class (seeing step 635).Select the physical Design of each module, make the most sensitive of switching circuit corresponding to the particular procedure parameter of in this step, carrying out.Device-circuit analysis program, for example Spice of different editions or Spectre or steadily method for numerical simulation can be used to realize these.

Step 625 provides, and in the switch element in different test module classes is arranged in and surveys the topography, makes switch element obey test in wafer processing procedure.The example how to be employed of surveying the topography comprises the measurement based on delay that is used for frequency and phase shift.In Fig. 7 C, one or more delay-sensitive elements 731 are placed between a series of inverters 734 or are embedded in its inside, and through controlled 730, or trigger, connect back itself through feedback 740 then, formed ring oscillator (RO).In Fig. 7 D, increased with reference to output 750 with the negative circuit of indication phase shift generation based on phase place.Delay-senser 731 corresponding to shown in Fig. 7 A can operated structure.The test module of placing during complete test structure can be included in and survey the topography.The class of manufacturing-association attributes that can evaluated by each the measurement of performance parameter (for example based on the measurement that postpones) comprises L _Eff, interconnection resistance and electric capacity, grid capacitance, sew and other performance parameters.In one embodiment; independent PSTS for the sensitiveness design of amplifying in the difference of same position; or has an identical PSTS of a certain sensitive degree; or the combination of above-mentioned two kinds of situations can be disperseed by crystal grain or wafer; and design have each position or susceptibility class or both different output " sign " (as; frequency or phase shift), and therefore can be by simultaneously but detected respectively.In this embodiment, probe card comprise with wafer on the detector and the excitation of precalculated position coupling, it can be used to survey simultaneously the crystal grain on the wafer, and increases throughput.

A class testing structure be can make up, attribute and baseline are used for making separately.The process of setting up PSTS or organizing PSTS more for each procedure of processing or a plurality of step is repeated, and is comprised up to the procedure of processing of all expectations.

In step 635, formed the baseline class of structure.In an embodiment, the baseline class is made of the module identical with one or more test structure classes.These baseline structures are designed to or are insensitive to the sensitivity of the procedure of processing of the amplification of PSTS, perhaps be designed to when the PSTS with the sensitiveness with amplification coexists a position, the result's of two structures difference has the sensitiveness of amplification to procedure of processing.When the baseline class of structure was unnecessary, the use of this test structure was more useful.

Step 640 provides, and each comprises that the PSTS class of baseline PSTS is distributed in intragranular.In step 645, electroactive measurement is undertaken by each testing element.Shown in Fig. 7 C and 7D, electroactive example comprises device performance measurement (for example frequency and phase shift), the response of its indication process sensitive structure.How electroactive each PSTS that can comprise handles and exports test signal, and how the discrete component of PSTS carries out (for example, the timing of single gate switch and conversion speed and shape).As other places in this article mentioning that electroactive class can comprise electroactive output signal and photon signal.Photoelectron signal can detected and decomposition from the photon signal that is produced by test structure.In addition, structure can be designed as electromagnetism and/or the photoelectron signal (element 130 for example shown in Figure 11) that electroactive generation arrives detection pad.In addition, structure can be designed as allow electron beam and ion beam technology detect detection pad present electroactive.

In step 650, analyzed in step 645 measured change.Analysis can be between the PSTS in special defects, or between the class of PSTS (separately or in groups), or be compared to each other, or " simply " tachometric survey of non-PSTS device, or non-sensitive structure.Especially, each PSTS class can be compared with the baseline class of PSTS, is in special defects or surpasses the variation of the appointment relevant with the baseline measure of the change determine to change.

Fig. 8 is the representative instance how method described among Fig. 6 is performed.Fig. 8 shows the PSTS collection on the different position 812 that is distributed in chip 810 that comprises baseline PSTS (by the output of label 802 expression), and it is by physically with each other next-door neighbour and power, signal and testing circuit and weld pad colocated and be positioned at wherein.Suppose that baseline PSTS comprises the similar switch element of switch element to the design standard assembly that is used for one or more PSTS classes.With reference to figure 8, the PSTS collection may comprise different PSTS classes, and wherein each PSTS class is to one or one group of procedure parameter sensitivity.Because in each position, its layout is approaching, all structure set all will be experienced identical processing variation, and these change by the variation of local pattern density and/or the control of other partial operation conditions.In the course of processing, the measurement of control structure will determine that Local treatment changes the influence to this structure, and be used to the data point that standardization and calibration are measured with respect to other processes and/or position sensing, with and each measure and change and will be compared and calculate as its indication.Variation will prove successively from the corresponding PSTS of contiguous control structure.Local treatment changes and to cause mixing or both variation the physical size of switch circuit devcie or device.These change the performance relevant parameter (for example, frequency or phase response) of the measurement that influences PSTS successively.In one embodiment, the electrical measurement of baseline structure and other structures is relatively to change a maximally related isolation of making characteristic favourable with process, process is changed responsive switching circuit will show marked change in its performance parameter because have only.This just allows one group to measure at grid module problem (L _Eff) and interconnection resistance in baseline criteria change between the interconnection depression cause and distinguish, distinguish.Previous technology is devoted to load with the simulation local process physically near placing different test structures in the chip design part.On the contrary, test structure produces adjacently with the structure of regulating with being used for power, and the input generation is arranged in position adjacent one another are, and co is at the active area of chip near the inner and pattern density wave zone.

Fig. 9 A shows test phase circuit element 920, the buffer that it can be associated with it, power/excitation and output weld pad and circuit are formed on the active area of crystal grain together, and in order to produce about the baseline circuit or about each other time delay or phase shift, p mixes or n doping grid length (is respectively L to amplify _p, L _n) influence of Whole Response of 910,912 pairs of circuit 920.This can revise switch element, series resistance (R) and series capacitance (C) and realize by according to the principle shown in Fig. 7 A.In addition, by especially with L _pAnd L _nBe designed to minimum permission, approximate minimum or inferior minimum grid length, and keep p doping and n doping grid width (to be respectively W simultaneously _p, W _n) be higher value.In order to make the variation that causes by local pattern density have identical change in size, Δ L=Δ W, therefore, variation is part or the Δ L/L of whole grid length greater than whole grid width〉Δ W/W.The measurement of these device frequency or phase place changes will be extremely sensitive to grid length successively.Identical interconnection element 920 is nested in electric active area or the passive component 924, to duplicate (simulation) local circuit detail of design density.As what those skilled in the art approved, can pass through L to the independent n device or the p device of the sensitivity of channel length _pOr L _nRealize, wherein L _pOr L _nBe designed to amplify L _EffTo the circuit speed Effect on Performance.

Fig. 9 B shows test phase circuit element 930, the buffer that it can be associated with it, power/excitation and output weld pad and circuit are formed on the active area of crystal grain together, and in order to produce the purpose of time delay or phase-shift measurement, to amplify the influence of interconnection resistance to the Whole Response of circuit.This can realize by special length of revising interconnection 934, makes by the change in size that local pattern density induction changes or varied in thickness causes, will change exerting an influence to the measurement of the frequency of these devices or phase place.Revise interconnection, make its width remain on minimum dimension, and select length to construct enough big series resistance with in can be from Fig. 9 B adjacent inverter, tell the time delay of collecting structure 930, and the localized variation on thickness and width will produce bigger influence to the adjacent elements among Fig. 9 B to the retardation ratio of element 930 like this.Broach characteristic 936 and interconnection 934 are adjacent rather than is electrically connected and will guarantees that PSTS can not change and influence near its pattern density.Above-mentioned device can be placed in one or more interconnection grades, is used for isolating the influence of the interconnection resistance that comes from different interconnection grades.

Fig. 9 C shows on the active area of crystal grain, the circuit element 940 that forms with relative buffer, power and detecting element and circuit, and be set to produce the purpose of time delay or phase-shift measurement, to amplify the influence of interconnection capacitance to the over-all properties response of circuit.This can realize that by the length of special modification interconnection 944 RC can separate with adjacent elements among Fig. 9 C the contribution of integrated circuit component 940 time-delays like this.Therefore the line that local pattern density induction changes or Thickness Variation causes to the change in size of line to the frequency of element 940 or the influence of phase place output measured change greater than to other element among Fig. 9 C.Adjacent and then will not guarantee that with interconnection 946 bells and whistleses that are electrically connected 946 PSTS can not change near the pattern density it.Above-mentioned device can be placed in one or more interconnection grades, is used for isolating the influence of the different brackets of the interconnection capacitance that comes from different interconnection grades.

From Fig. 9 A, the measurement of the device shown in 9B and the 9C replenishes will describe whole and independent physics change sign, these signs provide the great information of the control that is used to control the interconnection processing that is used for critical adjacent devices, the time that this adjacent devices is used in the chip distributes, clock skew, and other performance impacts of any interconnection structure.

Fig. 9 D shows on the active area of crystal grain, the circuit element 950,960,970 that forms with relative buffer, power/excitation and output weld pad and circuit, and be set to produce the purpose of time delay or phase-shift measurement, with of the influence of amplifying gate electrode capacitance to whole timing responses of circuit.This can on purpose revise the area (L * W) 952,954 and 956 realize of the grid of set of devices by in known area incremental range.Each recruitment all will influence these and have the measurement variation of different area to the frequency or the phase place of the device of perimeter value, and this is relevant to gate perimeter zone (source-leakage is injected and light/etching) with grid membrane stack variation (area).Other devices and circuit element 920 are similar, and be adjacent and the device among the electrical connection graph 9D not as Fig. 9 A, shown in 9B and the 9C, will guarantee that the device density of PSTS pattern density and the active device around its is similar.

Fig. 9 E shows on the active area of crystal grain, the circuit element 980 and 990 that forms with relative buffer, power/excitation and output weld pad and circuit, and be set to produce the purpose of time delay or phase-shift measurement, with of the influence of amplifying gate electrode capacitance to whole responses of circuit.The selection label is 982 and 984 device, and device is had respectively and circuit element 960 and 970 identical performances.Frequency among comparison diagram 9D and the 9E between the device or phase delay result, the boundary effect of release etch (Fig. 9 E) and source-leakage expanded capacitor (Fig. 9 D).Other devices and circuit element 920 are similar, the contiguous and device among the electrical connection graph 9B not, and as Fig. 9 A, shown in 9B and the 9C, they will guarantee that the PSTS pattern density is similar with the device density of its active device on every side.The source that is used for the variation of these devices can comprise that also there is impurity in gate dielectric materials, and gate electrode mixes and isolates or the like.

Figure 10 shows on the active area of crystal grain, the PSTA that forms with relative buffer, power/excitation and output weld pad and circuit, and be set to produce the purpose of time delay or phase-shift measurement, with amplify and related critical dimension scanning electron microscopy (CD-SEM mensuration) and electric critical dimension (CD) measurement between deviation.The CD-SEM mensuration usually with rule in the relevant process window of electric active device-be that CD satisfies the electric treatment standard with " well " of guaranteeing to be used for CD, in the course of processing, be determined.Because CD-SEM leaks the electrical effect that expansion is injected to the source, or the channel doping characteristic is insensitive, should be relevant so just carry out routinely, with the electric CD that determines to be equal to the physics CD that measures in critical field.The signal delay of structure as shown in the figure between can the measuring switch circuit element, and CD SEM can measure near in being used for timing architecture independence and the CD of intensive structure changes.Data from both all are used to determine photoetching and etch processes window.In Figure 10, created the isolated area 1010 and the intensive encapsulation region 1050 of device of device.Designed repeat circuit element 1030, made that the grid length 1042 of element 1040 is identical with shielding wire 1020 on how much.Similarly, the grid length 1082 of the device 1080 in intensive line 1060 and the intensive packaging area has identical design.The electrical measurement of area of isolation 1010 and close quarters 1050, and the CD-SEM of shielding wire 1020 and grid length 1042 measurement together with intensive line 1060 and grid length 1082, are used for setting up physics grid length (L) and electric grid length (L _Eff) correlation.When the frequency change of measuring or phase change are compared with CD-SEM result, can directly determine deviation.

According to another embodiment, chain of inverters (seeing Fig. 7 B) is set to the partial test structure, measuring n raceway groove and p channel device switching speed, and when this chain is provided power with the clock pulse speed of product processing original design and encourages, the whole time delays that are associated with whole chain.The placement of these structures and measurement, and therefore the liner (see figure 8) in the power/excitation that is associated with them and data collection circuit and the active area chip region allows the built-in chip variation of these structures is assessed.The layout of these structures in the chip active area also can provide a simple yield rate sieve on the first estate of metallising, be used for isolating the wafer of (for example, speed is slower) beyond the specification that drops on expectation, makes it no longer continue manufacture process.

In another embodiment, the simple inverter chain of test structure (being similar to Fig. 7 B) can be designed as a plurality of elements that make in the chain and has design defect to the process variation sensitivity.For example, can add extra serif, make it more may " scum silica frost " at the grid belt-like zone, weaken intrinsic etching characteristic and cause gate strip and the adjacent metal band between finedraw shorten.The placement of these structures and measurement in the active area of crystal grain (chip), segmentation fixedly photoetching defocuses step and in the past known pinpointed focus, therefore the assessment of the variation of built-in chip will be allowed, these variations are tended to be reduced, and allow to readjust and correct the setting of photoetching pinpointed focus, and compensation is corresponding to because local pattern changes the process etching to the sensitiveness of " scum silica frost " that causes changes.

Further, another embodiment provides, and makes up the simple chain of inverters of test structure, makes circuit speed handle not normal and interconnect at device and is isolated between the processing.These circuit will be designed to add the interconnection capacitance of fixed qty, and these electric capacity have typical distribution length.Metal 1 sedimentation measurement can provide the measure of the change of the built-in chip of circuit speed.Because invention technology disclosed here is noncontact, non-invasion, and the measurement that only needs sight line just can realize, same structure on metal 2 or metal 3 depositions or the metal grade on the purpose in office, comprise the follow-up measurement of the deposition on the most last metal, isolate changing in the chip that postpones to cause by the interconnection RC that after metal 1, causes in the built-in chip with any amount of process and/or design problem on metal 2, metal 2 etc. with allowing.In other advantages, such design does not focus on and produces engineering resource on the metal interconnected order in expectation measurement tolerance scope.In case metal interconnected processing is modified, the similarly effect that measurement can deterministic process " mixing method ".

In another example, can in existing ripe chip, add the circuit subclass of premium customers design.In the active area of chip area, arrange and measure these structures, change in the chip of these novel circuits of assessment in local pattern changes therefore allowing.The layout of this structure also provides a quick quantum of output sieve at the first estate of plating, with the slow and fast circuit of isolation ratio expectation circuit, generation feeds back to the designer fast, with before should designing a large amount of productions of input, circuit is further optimized.

Various other the circuit design of embodiments of the invention plan are used as test structure.In other advantage, embodiment described here can easily adapt to nowadays known manufactured n raceway groove and p channel device, and the more complex devices that is considered in the manufacture process in future.

Can use various computer based circuit and industry physical Design known to the skilled and analysis tool, above-mentioned special test structure is designed.The example of such design tool is by " PROPHET " of the integrated system center exploitation of the Stanford University of California.Because PROPHET and similar design instrument can be predicted the circuit characteristic that is used for the various process parameter value, structure Design only can be optimized to provide to the sensitiveness of the procedure parameter of selecting and not to other parameter sensitivities.

According to test structure shown in Figure 8 and relative power/excitation and testing circuit and the layout of liner on wafer or chip is a kind of selectable design.According to an embodiment, such structure is arranged in product chips inside along leading diagonal.Alternatively, structure can be arranged by the domino pattern, for example, comprises the upper left of chip, and is upper right, center, lower-left and lower right area.Alternatively, for example, at microprocessor (MPU), in CPU (CPU) and the ASIC device, test structure can be arranged in logic core near the border, or the inside of SRAM module etc.It should be noted that the exact position of test structure is dispensable for the present invention on the chip.Other suitable choice of location also are fine, and comprise untapped part on the wafer, special test chip, drawn area and on testing wafer.

The chip internal power and signal that is used for test structure produces

The method that has many use test structures that manufacturing is assessed.For use test structure before finishing in manufacturing, must overcome certain difficulty.In these difficulties, test structure is activated before need being completed at the integrated circuit on the remaining chips.In addition, expectation is tested chip as much as possible on the wafer, and does not damage or damage chip.

Embodiment described here provides the test structure of inside on the wafer.Test structure is provided with from the manufacturing with the assessment wafer of the power of the colocated structure in crystal grain active area or the drawn area and test signal.For a purpose of inventing, with non-destruction, noncontact and non-invasion mode will offer the intragranular pumping signal of test structure, the power and the test/triggering signal of requirement offers chip.In addition, after conductive material is deposited on the wafer (for example, after local connection or the metal 1), test structure can be activated in the arbitrfary point.Therefore, an embodiment shows: test structure is distributed to many (if not all) and is positioned at (the not use zone that comprises scriber and wafer or the test chip) chip on the wafer, and test structure can be triggered, excitation or be activated in different manufacturings (online) stage.Each test structure can be reused, and can not influence the follow-up use of chip, also can not cause the interruption of the course of processing stream of manufacturing.Use and test test structure by this way, can determine about how controlling and/or improve the valuable information of manufacturing, particularly in the active area of chip/crystal grain.This information may be on wafer (for example corner of wafer), crystal grain or certain chip, or have region characteristic on the wafer scale, thus can be applied to be formed on a plurality of chips on the same wafer, and can carry out wafer to wafer, the further comparison of group.And according to the description of front to other embodiment, test structure can be by proprietaryization to provide the information about processing variation and/or one or more wafer fabrication steps.

Figure 11 is typical square frame; show the schematic diagram in the assembling district of the manufactured wafer crystal grain of part; comprise the crystal grain interior zone; have and to measure and treatment step of making or the relevant in proper order performance parameter of treatment step, or be used for the relevant test structure that monitors the same area in crystal grain or the wafer of performance (for example speed).Test structure can be used the manufacturing with the assessment wafer in one or more manufacturing steps.In embodiment as shown in figure 11, test structure 1120, power receiver 1112, test/triggering receiver 1110 and detection pad 1130 can colocated in chip 1102, and can be repeated test and not be damaged.In addition, chip 1102 can be tested under the state of finishing manufacture process or partly finishing.For example, according to the embodiment that Figure 11 describes, test structure can be also tested being activated in early days of wafer manufacturing, is used for assessing one or more initial manufacture processes; Activate making the later stage then, be used for the manufacture process of evaluate subsequent.Finish in case make, test structure can be energized/activate and be tested, assesses with whole manufacturings and/or performance to chip.

According to embodiment, chip 1102 has test/triggering receiver 1110, power receiver 1112, one or more test structure 1120 (may be inhomogeneity or design) and relevant detection liner 1130.All these elements can be formed on the active area more than one the crystal grain that is used for the position that intragranular measures.Power receiver 1112 can be energized or excite, and thinks that test structure 1120 produces power signal.In an embodiment, power receiver can be made with one or more photodiodes.Power signal activates independent test structure with combining of test/triggering signal.Test/triggering receiver 1110 can be energized or excite the triggering signal that is used for test structure 1120 with generation.In an embodiment, test/triggering receiver is made up of one or more photoelectric diodes with fast transient response.Test/triggering receiver 1110 and power receiver 1112 all can or excite by the external energy source forcing.Especially, test/triggering signal and power signal can activate test structure 1120, and it is detectable electroactive that it is shown.Electroactive comprising, but be not limited thereto: the emission of hot electron induced photon (can be detected, because the time photo emissions of decomposing be with active junction in the switch events time correlation), the output of one or more signals of telecommunication, time correlation in the class of one or more electro-optic properties (for example changes, electric charge induction, electric rectification and/or electric absorption), and/or other of interconnection junction are electroactive.

In order the availability of chip 1102 not to be caused breaking-up machinery or electricity, damage or interference, and prevent or interrupt more step in the manufacture process stream, embodiment shows that the test of active area colocated/triggering receiver 1110 is excited by lacking the energy media that contacts with non-invasion with power receiver 1112.Among other embodiment, the inner crystal grain of test structure is only activated by power signal.In any case, the inside chip energy source (power/test) that has a test structure by colocated (in the identical active area of same die) can be finished the activation of test structure.In the embodiment shown in fig. 11, energy source and the triggering/test source (for example light beam) that goes out from the wafer external discrete can be used for activating test/triggering receiver 1110 and power receiver 1112.In one embodiment, first energy source 1108 can guide and continue energy beam ingoing power receiver 1112, and the power signal as a result that therefore is used for test structure 1120 continues.Second energy source 1106 can enter test/triggering receiver 1110 by boot time (and/or amplitude) modulated beam of light.The light beam of modulation causes that modulated test signal is transfused to test structure 1120.The follow-up electroactive of test structure 1120 can be based on the modulation input that comes self-test/triggering source 1106.Test/triggering receiver 1110 can be activated simultaneously with power receiver 1112.According to an embodiment, first energy source 1106 is produce to continue the laser beam of energy source as power, and second energy source is the laser that produces pulsation (as, gating on time) modulated beam of light.

Alternatively, identical energy source 1108 can be cut apart, and a part is used for power receiver 1112, and another part can be modulated and be sent to test/triggering receiver 1110.

By test structure 1120 be triggered and cause electroactive, can be measured as performance parameter.Switching speed for example, phase place or signal delay, or conversion speed.In one embodiment, switching speed can be by point-to-point measurement (independent grid level), and for example single transistor also has end-to-end on the test structure 1120.Test structure 1120 can be by customizations, make that performance parameter can be relevant with the information of specific manufacturing step or order, and more specifically, and be chip or crystal grain, wafer, or the variation of the step from a wafer to another wafer is correlated with.Appreciation information can comprise the information that the resolving that causes to the direct energy measurement of predicting the device speed that final workmanship is useful and/or by certain manufacturing step changes, and the information that process changes comprises the result of particular procedure and the information how process is performed.

In one embodiment, some test structures that are triggered 1120 electroactive can be the node signal output of photoelectron effect form.For example, the core of the thermionic emission of devices switch is no probe measurement technology, can use by the photon detector 1142 that use designs.In another example, other photoelectron effects, for example electric charge induction electric absorption and electric rectification need to use probe/detector 1142.In another example, electron-beam probe/detector can be used for surveying point-to-point switch events.

Detection/triggering signal also can be used to time-based measurement that " timing edge " of a repeatability is provided, and wherein time-based measurement can produce point-to-point information, and as test vector, can be used for the response of point measurement test structure one by one.Analyzing the output signal of each point (basically in output point/detection pad), is how to influence test signal with internal electrode, transistor or other nodes of determining test structure 1120.Point-to-point output signal can be reflected in that single transistor transforms or the information when changing its state, also can reflect active circuit to test signal how in time and the change of point-to-point and the influence of evolution in shape.Therefore, the node signal from transistor and other assembly outputs of test structure provides information how to handle test signal about other nodes in special transistor, grid or test structure.Because be observed from the electroactive of single transistor, about test signal how processed information can be described as " node-node ".In this embodiment, the timing " border " that provides time-based measurement required also can be provided test signal.Equally, for those skilled in the art, test vector can be used for complicated diagnosis/purpose of design, and about the analysis of wafer in the manufacture process or crystal grain.The task that Here it is carries out based on encapsulation usually (crystal grain that quickens passivation and handle fully).

As replacement to electroactive node-node detection, the embodiment of the structural test of use test/triggering vector can be from set test structure detect electroactively, this means the electroactive how development between the input of test structure and output of power or test signal (and be not at test structure single gate and node place) that reflects.This electroactive can be aggregate signal output.In order to detect in non-contactless and nondestructive mode, can use detector liner 1130 from the aggregate signal of detection architecture 1120 outputs.The detector liner 1130 in the future electrical output signal of self-testing structure 1120 is converted into that other are electroactive, and it can detect by contactless method and medium.Follow discussed the same, electrical output signal has reflected how to handle test signal between the input of test structure and output stage.

In an embodiment, the overall delay of test structure/circuit can be significantly on frequency, and detector liner 1130 with based on the signal electromagnet of the signal of telecommunication of test structure 1120 (such as capacitively or inductively) coupling.Receiver 1140 can be placed on above the detector liner 1130, to detect and to measure the signal from liner.For the node-node detection of test structure 1120, suitable probe/detector 1142 is in conjunction with can be used to detect/detect the signal of the single gate of self-testing structure.For example, laser microprobe and photodetector are used for electronic rectifier or electric adsorption effect; The electron-beam probe that perhaps has appropriate time gating detector; Perhaps the time resolution detector is used for the no probe measurement of the photon of hot electron induction.

Can for providing, performance parameter value determine class and/or scope from the information of output signal identification.And test structure 1120 can be designed as, no matter with the form of time-based node-node, still (I/O) inhibit signal of set, its activity in the manufacture process of wafer to special manufacturing step sensitivity.Mention as other places in this application, performance parameter value can be analyzed by a variety of modes, with the manufacturing of assessment wafer.For example, the variation of performance parameter value changes may use common test structure to be defined, and this test structure is arranged on a plurality of positions of a crystal grain, or crosses over a lot of crystal grain and other positions of wafer.Because performance parameter value may depend on the test structure design, so an embodiment provides, performance parameter value identification comprises process deviation about the information of special manufacturing step or order.

For example the embodiment described in Figure 11 may eliminate the use of following the tracks of row and other mechanical detection devices, and it is present in the line of chip 1102, is used to provide detection and/or power signal and excitation.The elimination of this Mechanical Contact make to be satisfied by wafer and is formed independent chip sealed key and essential requirement when manufacture process finishes.According to current chip design, the seal request chip is to moist and insensitive from other pollutions of surrounding environment, for the requirement of great majority (if not all) semiconductor element.Therefore, scheme can be discerned or determine the performance number of multiple class and a large amount of positions on chip 1102 or its wafer just as shown in Figure 11, and does not influence the availability of chip 1102.Be activated when in addition, scheme allows each selection step of test structure 1120 in manufacture process and trigger.Can use the substantive test structure of multiclass.Equally, in the different phase of manufacture process, can repeat test to wafer 1102.

Figure 12 shows the method that is used for the use test structure when intragranular produces at the power that is used for test structure and test/triggering signal according to embodiment.With reference to the element of Figure 11, purpose is suitable element or the context that is used to implement described method in order to illustrate.

In step 1210, power signal is comprised in the crystal grain active area, and in manufacture process or after it is finished, is applied to test structure 1120 particular bond point.

In step 1220, test/triggering signal (in active area) in chip produces, and is applied to one or more test structures 1120.Test/triggering signal may be produced by the noncontact energy (as first energy 1106) of outside, and this energy provides energy to the appointed area on the chip, and makes this zone produce test/triggering signal (or its equivalent amount).According to embodiment, power and test/triggering signal are applied to one or more test structures, make the test structure activation electroactive for performance.Step 1210 may be carried out simultaneously with step 1210.Especially, the application of power and test/triggering signal should be simultaneously.Power signal may produce in the same manner with test/triggering signal, and wherein the Wai Bu noncontact energy can provide energy to the appointed area on the chip.With reference to Figure 11, the appointed area of chip that is provided energy is corresponding to power receiver 1112.In one embodiment, the single area on the chip 1102 may be distributed power by a plurality of test structures that one or many is used on this chip at one or more test phases.

In step 1230, detect by the independent test structure 1120 that is activated cause electroactive.The electroactive form of test structure (himself may to the manufacturing step sensitivity) may be node-node output, aggregate signal, with and combination.Survey the electroactive probe (if desired) and relevant detector that may need to use particular design of any class, as other positions in this application are described.In the embodiment of (I/O) signal of gathering, signal is launched in the interpolation of detection pad 1130, the set output signal (separate nodes that comprises test structure) of the corresponding one or more test structures of signal.As what discuss in other place, the set output signal can be provided signature, with the effective test structure of identification pair set signal.

Step 1240 provides detected electroactive the explanation as performance parameter variations to change, and it is relevant with the quality metric relevant with output, or relevant with the processing step in the process sequence.The example of performance parameter may have corresponding relation with following these: (i) on the whole or in gate circuit independently, and the conversion speed of test structure; (ii) about to the how different frequency of the output signal of test structure 1120 and input signal or the delay of phase place; And (iii) measure one or more transistorized switching rates and shape (in time), or measure the aggregate signal of test structure on the whole.

According to embodiment, step 1250 provides, and the variation of performance parameter variations or baseline is analyzed, purpose be for the order that makes they and one or more special steps, step or the technology in wafer is made relevant.In one embodiment, performance parameter is worth variation to be determined, with the identification process deviation.The example of other analytic functions comprises the comparison between the execution performance parameter, and it is by at the diverse location of crystal grain or have the measurement that the independent test structure of different designs carries out.This analysis can comprise that to make performance parameter value (or its variation) and special manufacturing characteristic interrelated, this special manufacturing characteristic be activated at test structure before the special process in the manufacturing process, carried out relevant.

As described method can do not influence or the prerequisite of defective chip under implement.The use of power and test/triggering signal also has the detection to the signal that comes self-testing structure, can not influence the needs of sealing (or passivation) crystal grain/wafer and carry out, and it can reuse all its elements after the wafer manufacturing is finished.

Power produces and adjusts

As the test structure described in Figure 11 may be responsive for the variation of input signal.Especially, any fluctuation that offers the input power of test structure may make the output of test structure amplify or crooked, causes process deviation or make the output that characteristic works to change not obvious.In addition, because the energy that is used for producing power signal at the receiver end with test structure configuration is in the outside of chip and separates, be that power signal may have unsteadiness and fluctuating with power conversion.The result may need suitable buffering, adjustment (for example rectification) and/or stabilisation by the power signal in the chip of the outer energy generation of chip.

Figure 13 A illustrates the circuit that is used to adjust the input voltage that is produced by external power source, and this external power source can be placed in the crystal grain active area jointly with power receiver, test/triggering receiver, test structure and detection pad.Circuit 1305 comprises photodiode 1304, adjuster 1310, chip internal reference voltage mechanism 1316 (being used to provide reference voltage) and PSTS 1318 (as shown in Figure 4).In an illustrated embodiment, external power source is continuous wave (CW) laser 1302, its light is mapped on the photodiode 1304 and reference voltage circuit 1316 (as band gap voltage reference) on.In optional embodiment, photodiode 1304 is with the operation of certain pattern, with the voltage of regulating and be fixed to PSTS 1318 in a close limit.Photodiode 1304 produces voltage, and it is regulated by adjuster 1310 and stablizes.Externally power supply is among the embodiment of CW laser 1302, and demodulator 1310 is PSTS 1318 regulation voltages, so that its voltage is in narrow wide and scope.Externally power supply changes under the situation of (as pulse amplitude, time, gating modulation), and adjuster 1310 also can be with the input voltage rectification.Adjuster 1310 can comprise comparator 1312, and the voltage level of PSTS1318 and the reference voltage that is provided by band gap Voltage Reference 1316 relatively are provided for it.The output of comparator 1316 can offer demodulator 1310, so that the voltage to the input of PSTS 1318 is regulated.In one embodiment, adjuster 1310 comprises voltage multiplier circuit (such as the switched capacitor voltage multiplie), is used to comprise the adjusting of voltage multiplier, is used for the test structure of voltage that need be higher than the voltage that is produced by power receiver.

The sensitivity of PSTS 1318 may need input voltage very stable, or in the excursion of an arrowband.Surpass at the voltage that is provided by photodiode 1304 under the situation of the upper limit of band, adjuster 1310 can be reduced to the voltage on the incoming line of PSTS 1318.When the lower limit of the voltage ratio band to the incoming line of PSTS 1318 was low, adjuster 1310 may disconnect or work in the capacity that reduces.It also may be increased to the input voltage of PSTS 1318.Alternatively, feedback mechanism can signal to laser 1302, passes to the light quantity of photodiode 1304 with increase.Provide below and how to adjust circuit 1305 to finish the feedback method of (comprising not enough power supply).

Circuit 1325 has been shown among Figure 13 B, be used for adjusting the input voltage that produces by external power source, allow the feedback of lasing light emitter 1302 simultaneously, this lasing light emitter can be placed in the crystal grain active area jointly with power receiver, test/triggering receiver, test structure and detection pad.Circuit 1325 can comprise photodiode 1304, with reference to ring oscillator 1308, PSTS1318 and feedback mechanism 1326.In an embodiment, laser 1302 is mapped to light on the photodiode 1304.In actual conditions, may use a series of photodiodes.Ring oscillator 1326 provides frequency output, and it is with directly related from the voltage of photodiode 1304 and by its change.Especially, ring oscillator 1308 is as voltage-controlled oscillator (VCO), and its frequency is fed 1326 receptions of mechanism.1328,1329 combinations of one or a pair of capacitive gasket are to be converted to feedback signal with oscillating voltage, with the output of modulated laser 1302.When on the voltage ratio PSTS that produces by laser 1302 with high the time, the output frequency of ring oscillator will exceed desired scope, and to the feedback signal of laser 1302 output of laser be reduced.When the voltage that is produced by laser 1302 was lower than the PSTS low strap, the ring oscillator output frequency was low excessively, and feedback signal makes laser 1302 increase its power.With such method, the combination of VCO 1308 and feedback mechanism 1326 can be used for monitoring and control laser 1302, to adjust under the situation of needs, to increase and reduction power.The timing of 1332 monitorings of laser controlling unit and control laser and power output.Modulator 1331 is exported as the amplitude of modulation timing and laser as acousto-optic and/or electrooptic modulator, and be can be used in noise suppressed.

Figure 13 C shows circuit 1345, be used for regulating the input voltage that produces by external power source, allow the feedback to lasing light emitter 1302 simultaneously, this lasing light emitter can be placed in the crystal grain active area jointly with power receiver, test/triggering receiver, test structure and detection pad.Circuit 1345 may need quite low power (with respect to test structure, be used for the output buffer of liner and the power demand of driving).Circuit 1345 comprises photodiode 1304, voltage multiplier 1342, feedback mechanism 1326, PSTS 1318 and adjuster 1350.In an embodiment, make voltage multiplier use the switched capacitor charge pump.Adjuster 1350 can comprise band gap voltage reference 1352, comparator 1354, pulse-width modulator 1356 and shunt regulator 1358, as the voltage offset circuit.In an embodiment, the output of the laser 1302 among Figure 13 B and the 13C can be driven by laser power control, to modulate its amplitude and/or gating (pulse mode) function.The laser that use is sent by laser 1302 can start the quite little voltage level from photodiode 1304.Voltage multiplier 1342 can increase the voltage of photodiode 1304, makes input voltage surpass to be used for the upper and lower bound voltage of PSTS1318 operate as normal.The variation of output voltage is to cause by making specific difference, changes and causes and can't help applied signal voltage.Comparator 1354 can and have the reference voltage of band gap voltage reference 1352 to compare with on the line voltage.If surpass reference voltage, voltage offset circuit 1358 is triggered to discharge electric current.Therefore this may be consistent with the transistorized threshold level of each circuit that is exceeded, and causes that each transistor changes in different (receiving) level and time.Part in the total voltage that each voltage offset circuit 1358 can only be discharged.When voltage offset circuit 1358 was converted, voltage was provided for pulse-width modulator 1358.Pulse-width modulator 1356 modulation overvoltage.The overvoltage of modulation offers feedback mechanism 1326.Described in Figure 13 B, the voltage signal of this modulation is used for increasing or reduction laser 1302.Produce under the too much voltage condition at laser 1302, the voltage of modulation causes that laser 1302 reduces power.In an embodiment, when laser 1302 can not provide the power of abundance, it is quiet that pulse-width modulator 1356 becomes.The quiet behavior that becomes is to increase the input of its power to laser 1302.When laser 1302 enough increased from voltage that photodiode 1304 provides, pulse-width modulator 1356 can restart.Laser controlling unit 1332 monitors and the timing and the power of control laser are exported.Modulator 1331 as acousto-optic and/or electrooptic modulator, is used for modulating regularly and the output of the amplitude of laser, also can be used for noise suppressed.

Embodiment has a lot of benefits as shown in Figure 13 C.In these benefits, low relatively power is consumed at the input voltage that buffering is used for PSTS1318.In addition, to the increase of feedback indication laser or the reduction power of laser 1302, needed according to the stability and the repeatability of one or more test structures that on other positions of one or more crystal grain, drawn area or wafer, distribute.

Multiple technologies can be used to produce and regulate the power in the chip, so that can operate and do not cause adverse effect to the chip availability the test structure on the chip.According to the embodiment as Figure 13 A, 13B and 13C description, the power generator in the chip is finished by using laser beam, and this laser beam provides lasing light emitter to excite or to be that energy receives liner 1304 energizes.The CW power signal may take place.Test structure on the chip of some or all may use power signal.In one embodiment, the application of power signal and other be used to test/energy beam of triggering signal uses simultaneously.The power signal that is used for the test structure on chip of some or all can produce by being energized power pad.

Optional power takes place

As described in the embodiment in Figure 13 A-13C, with at other local described embodiment of the application, power source that is used at chip internal generation power signal (and may be test signal) in chip exterior is a laser, and it is mapped to energy beam on photodiode or other receiving elements.But, optionally the power mechanism also is operable.

Figure 14 A and 14B show embodiment, wherein thermoelectric (or oppositely thermoelectric, being called Seebeck effect again) mechanism is coupled with laser or other energy, purpose is to produce power or test signal in the sheet in order to cause, its can with test/triggering receiver, test structure and detection pad are placed in the crystal grain active area jointly.Figure 14 A is the top view of p-n (doping) structure, and this structure is modified and makes with its " p " zone 1402 and " n " zone 1410 separately.Figure 14 B is the corresponding sectional view along line A-A.For CMOS, can be added by the n trap 1404 of contact pad designed 1430 electrical addressings, so that p trap 1402 is isolated with substrate 1406.(Figure 14 B) produced in the gap 1414 of gained.Conductive plate 1450 for example can be formed by metal, and " p " zone 1402 is connected to each other with " n " zone 1404, is placed on then on " p " zone 1402, " n " zone 1404 and on the gap 1405, to save the space.

Laser or other energy provide the source to can be used to add heating pad 1450.Heat input corresponding " p " zone 1402 that excites and " n " zone 1410.The result be heat respectively away from or move to " p " zone 1402 and " n " zone 1410, it produces successively respectively to contact 1440 and 1442 rightabout charge movements.Because most of charge carriers are the contrary signs that are used for " p " and " n " zone, electric charge structurally adds, to form the set voltage of crossing over liner 1140 and 1442.Feedback or modulation circuit can be used for modulating the power that is used for stability and repeatable purpose.

Other power mechanisms also can be used.Be placed on the sensing element in the crystal grain as, induced power mechanism.Another inductive means moves on sensing element, to produce electric current from sensing element crystal grain.Feedback or modulation circuit can be used for modulating the power that is used for stability and repeatable purpose.

Other power generation mechanisms also can be used.These machine-processed examples comprise that use RF signal is to produce curtage.As, the RF signal can be applied to resistive element to produce voltage derivative.Alternatively, capacitive coupling can be used to produce enough energy to produce in power signal and the test signal one or two.Feedback or modulation circuit can be used for modulation power to reach stability and repeatable purpose.

In another embodiment, first energy 1108 can be mapped to modulated energy beam on power receiver and the modulator 1112, make that the power signal of the gained be used for test structure 1120 is modulated, though comparing very short period with test structure speed, and the receiver 1112 by using suitable design and be used for the feedback of the energy and the interlock circuit of modulation can be controlled the stability and the constancy of the power that transmits and receive effectively.

The device and the circuit that are used for electroactive non-contact detecting of semiconductor device and measurement

Figure 15 shows a dynamo-electric noncontact and non-invasive system 1500, is used to excite, detect and measure the electroactive of on wafer assigned address.Appointed positions may with the position correspondence of special test structure or other elements, this structure or element can show electroactive, it can indicate the chip manufacturing quality and yield and/or how carry out relevant with manufacturing step, order or process quilt.Especially, system 1500 can be used for explaining detect electroactive from the special test structure that spreads all over wafer (comprising crystal grain inside) placement, this wafer and power and testing circuit are placed jointly, the variation of its parameter and they is directly related with circuit performance and influence circuit performance, thereby can predict final result and performance output or relevant with manufacturing step or influence in proper order in the manufacture process of element on device, integrated circuit, wafer.An embodiment contemplated system 1500 detects and measures the electroactive of the special test structure that spreads all over wafer and distribute, the common power of placing and testing circuit, comprises the active area inner and scribe area inside (shown in Figure 1B) of crystal grain.Test structure can show the electroactive of the result that amplified the existing of attribute (or lacking) and manufacturing step or order.At Fig. 4-10 example how this test structure can be realized has been described.In the mode consistent with Figure 11 and 12, the described embodiment of Figure 15 can be configured to (i) and excite test structure, and (ii) detect electroactive from the test structure that excites, make all elements all inner common layout of the active area of crystal grain, and do not need the lead of physics and relevant contacting, the non-active area from the active area to crystal grain or on line or the wafer outside crystal grain and other parts of active area.

According to an embodiment, first energy, 1510 produce power bundles 1516 are used for receiver 1512.First energy beam 1516 can comprise that wavelength is λ ₁Light radiation.First receiver 1512 can be corresponding to the lip-deep optical receiver that is arranged on crystal grain 1550 (for example photodiode).In one embodiment, first receiver 1512 is photodiode or similar device.First energy 1510 can be the device (as laser diode or gas or solid-state laser) such as continuous wave CW power laser diode, or other similarly have the device of suitable wavelength, innerly to guarantee efficient coupling at photoelectric diode structure, to absorb and sealing.When concrete execution, can be overlapping in the sensitive area of first receiver 1512 by the wave spectrum of the electromagnetic radiation of first energy 1510 emission.For receiver 1512 provides energy, be used for generation and conversion electromagnetic energy like this to power supply 1518.In one embodiment, are electromagnetic situations for first energy beam 1516, receiver 1512 can be corresponding to the electromagnetic power receiver, and similar is in transformer.

According to an embodiment, second receiver 1522, test/triggering signal is placed on crystal grain 1550 inside, suitably to be coupled with second energy 1520.Second receiver 1522 also can be respectively that photoelectricity two is taken over or similar electro-optical device, or metal wire or dielectric, is used for electron beam or the ion beam energy and beam.Second energy 1520 can be the power source of modulation, and the beam 1526 of modulation is provided.For example, second energy 1520 can be time and/or amplitude-modulated pulse laser.The beam 1526 of modulation can have wavelength X ₂, can with the wavelength X of energy beam 1516 ₁ Different.Second receiver 1522 provides energy by the beam 1526 of modulation, thereby produces the test/triggering signal 1528 that replaces or modulate.

Power signal 1518 can be regulated by power governor 1519 before the tested structure 1530 of signal receives.Signal conditioner 1529 also can be adjusted before test/triggering signal 1528 tested structures 1530 receive.These adjustings, control and buffering circuit are similar to their relevant receivers, are placed on jointly in the active crystal grain inner area with test structure.In another embodiment, described as Figure 13 B and 13C, the control in advance of energy before silicon/device and timing source and control afterwards and regulate and can realize is with the stability of the signal of further adjusting test structure.After power signal 1518 and test/triggering signal 1528 excite test structure 1530, come the output 1538 of self-testing structure to be sent to detector liner 1540.Detector liner 1540 can comprise the signal receiver mechanism that is used for receiving output 1538.In one embodiment, detector liner 1540 will be exported transmission as electromagnetism RF signal 1555, and the noncontact electromagnetism RF detector 1574 that it can appropriately be coupled then detects.An embodiment provides, and the signal receiver mechanism of detector liner was using unique identifier to carry out the electromagnetism mark to exporting 1538 before can being transmitted by the RF that RF detector 1574 detects this conversion of signals.By this method, RF signal 1555 can have the signature of electromagnetism, and the special and unique thing of each test structure 1530 is had relation.Signature allow to be differentiated the electroactive of each test structure of distributing uniquely on the wafer that is used to discern, accurately to locate by its relevant signature and to distinguish.This allows to excite simultaneously and surveys test structure on one or more crystal grain and/or entire wafer.

As the replacement of using RF liner 1540 and 1574 pairs of electromagnetic detection of RF detector, probe and detector configurations can be used for detecting in the multi beam configuration potential change at detector liner 1540.In one embodiment, three beam 1557 (can be the electron beam form) can be injected and be contained in the detector liner 1540 (for example metal gasket), to detect voltage potential.The secondary of the detection of collecting at detector 1573 from liner 1540 will change along with the electroactive modulation of the tested structure 1530 of the surface potential of liner.The surface potential of modulation will be modulated the secondary flux, and the voltage-contrast of the feasible three beam 1557 that is collected changes, and will be surveyed by detector 1573.Second beam 1516 that is used to produce test/triggering signal 1518 can also be used to improving the signal to noise ratio of three beam 1557 (may be secondary beam).

In another embodiment, three beam 1557 may be an ion beam, and it is radiated at detector liner 1540 (making with the dielectric on the silicon) and goes up to set up known electric charge or voltage potential.The capacitive coupling of this electric charge and probe in detecting device 1573 will be modulated simultaneously with the electroactive of test structure 1530 on the liner 1540.Second ion beam 1516 that is used for producing test/triggering signal 1518 can be used for improving capacity coupled signal to noise ratio.

As to for example with the additional of the electromagnetic detection shown in RF liner 1540 and the RF detector 1574 or replace, detector single or a cover node-node can be used for detecting and measuring the electroactive various forms of the different nodes of test structure 1530 when independently node responding power signal 1518 and/or test signal 1528, perhaps by relatively first and the last node that detects be used for the collector node of test structure.For example, detector 1572 detects electroactive at the first node place of the chain of structure 1530.Detector 1572 is electroactive from second and subsequently node detection of the chain of structure.Develop (as postponing conversion rate, " form " etc.) and can directly be determined to propagating again from first node to the second with the signal of posterior nodal point, or by with first, second and the comparison of the delay of incident subsequently to test/triggering signal 1528.In an embodiment, node-node detection device is suitable optical receiver (for example photodiode), its detect in test structure 1530 each transistorized grid and be connected in by changing the photoelectric effect that activity the causes light/photon (hot electron that causes as photo emissions by no probe time series analysis photon counting detection, the electronic rectifier of electric charge induction and the electricity absorption of being surveyed and detecting by the gating laser, etc.).

As optical receiver, each all may detect and write down the photosignal of the various elements of self-testing structure 1530.The suitable optical train with object lens (and/or set of lenses) is coupled to suitable connection or the connection in the test structure with each detector 1572.On the other hand, single optical receiver is to wavelength X ₁(energy) and λ ₂The sensitivity of (test/triggering energy) may be weakened or be shielded fully, to prevent interference, wherein, λ ₁And λ ₂It is feature from the beam of first and second energy 1510,1520.In an embodiment, one or more detectors 1572 can be consistent with the time resolution radiation detector, and the high-resolution timing information of the photo emissions of responding to about the hot electron of record can be provided.The optical receiver of these classes can be made up of with relevant circuit the avalanche photodide of the operation in the time resolution that is designed for single photon counting mode.Alternatively, dull and stereotyped photoelectric multiplier of multichannel and suitable detector coupling can be used as photon counter.

The detector of other classes can be used for detecting inhomogeneous electroactive from individual node.

Add or replace power and detect the embodiment that constructs

Additional embodiment will adopt the test structure that can be activated and use with the built-in crystal grain power supply of alternation (alternateintra die power source).For example, the continuous wave CW laser of suitably adjusting (conditioned) and control can use together with glow plug Bake Blast Furnace Top Gas Recovery Turbine Unit (TRT) 1522 as shown in figure 14.Electron beam source can be used to produce power signal 1518 as the replacement that laser is used as the energy 1520.For example, electron beam can be used as second light beam 1526, and be connected on second receiver 1522, second receiver can comprise for example metal wire, and this metal wire is connected to the electric charge (or voltage) that will be assembled by electron beam or respond to and is converted on the equipment of electric current.In another embodiment, can be with ion beam as second light beam 1526, and can be connected on second receiver 1522, comprise the insulating material that for example is covered on the semi-conducting material by second receiver, this semi-conducting material is connected to the electric charge (or voltage) that will be assembled by ion beam and is converted on the device of electric current.

Additional embodiment can adopt can tested/triggering signal the test structure that activates of alternative source.For example: electron beam can be used as first energy beam, 1516, the first receivers that are oriented on first receiver 1512 and comprises for example metal wire, and it is on the equipment of current impulse that this metal wire is connected to electric charge or voltage transitions.In another embodiment, first energy beam 1516 is corresponding to the ion beam that is directed on first receiver 1512, and first receiver comprises the insulating material that for example covers on the semiconductor, and this semiconductor is connected to voltage is converted on the equipment of current impulse.Replacement as the electromagnetic surveying scheme of using electromagnetic probe buffer 1540 and detector 1574, and the replacement of the detecting strategy of conduct use electron-beam probe and secondary electron detector 1573, laser beam sources can be used for the electroactive of probing test structure 1530.For example, three beam 1557 can be the laser beam that is oriented on the detector buffer (detector pad) 1540, and the detector attenuator comprises for example optical receiver, and optical receiver is in response to electroactive reflectivity or the voltage changed in the test structure 1530.Reflectivity modulation and/or voltage modulated from attenuator 1540 can be surveyed by detector 1573, and it is to the electroactive sensitivity in the test structure 1530.Alternatively, three beam 1557 can be used as ion beam and is oriented on the detector attenuator 1540, and the modulation in the electroactive capacitively coupled signal in test structure 1530 can be measured by detector 1573.

As the replacement of using photosignal to measure point-to-point exchange activity, can be used to detect at the diffusion of specific node or the electric charge of joint (electric current) induction refractive index or sink effect/signal such as the 4th beam 1556 of time gate/modulating lasering beam (for example mode locking and/or gate).This signal will be modulated in electric handoff procedure, and this electric switching is by the induction of test/triggering signal, and this signal can be detected by the optical receiver 1572 of probe and suitably coupling.

Wafer is made and evaluating system

According to one embodiment of present invention, Figure 16 provides induction and has measured subsidiary details from the electroactive device in the zone of the appointment of active area in the crystal grain, the responsive test structure of power, test/triggerings, process that this crystal grain is included in same position with and buffering, adjusting and the shaping circuit of being correlated with.Excitation and sniffer 1640 can be operated together with the processing of wafers parts, locate excitation and position sensor, and the relevant electric light coupling mechanism between device and testing wafer device (DUP).Before testing on the specific test structure, wafer 1615 is placed on the movable platform of being controlled by processing of wafers and array unit 1,611 1612.Can be (for example such as the described test structure of the foregoing description by illumination, by using floodlight or laser scanning microscope (LSM)) imaging and manifesting on wafer 1615, also can come imaging by using imaging camera such as CCD (" charge coupled device ") array or photoconduction camera 1610 or other similar imaging devices (optical receiver that for example, is used for LSM).According to embodiment, test structure can be arranged in the active area of one or more crystal grain of wafer 1615, also can be arranged in the same place of active area with power supply and test/circuits for triggering.Platform 1612 is removable, with between the test structure and energy source 1604 and 1606 that are arranged on the wafer 1615, with and/or between probe 1642 light beams and detector 1602 and 1613, form the arrangement of expection.Image in having imaging capability accurately and cutting apart its visual field and the microscope unit 1609 of area-of-interest ability (based on electronics, ion or light) can be used for imaging, separate and coupled signal to detector 1602, and with above-mentioned energy beam or detector shaping with focus on on the measured device.Alternatively, suitable connection lead (for example light) can be connected on the probe that is attached on microscope and the aperture and reach effect same.Probe and detector 1642 need utilization imaging optics (for example, electronics, ion or light, or its combination) to arrange and receive detecting light beam and detectable signal respectively.

In finishing manufacturing after the procedure of processing of appointment, can the responsive test structure of measuring process.In finishing manufacturing, after the procedure of processing of appointment or the order, can use different types of test structures at once.On the whole, testing element can be used to be evaluated at the manufacture process of the first estate connectivity (for example the first metal layer) after finishing.After as long as test structure is ready to, electric energy and/or test/triggering signal both are applied to electric energy and test/triggering signal receiver at same place by excitation and detection instrument 1640.In an embodiment, energy and test signal can be applied in the test structure by (energy modulation or noise compression) laser beam 1604 and adjustment (amplitude or the time gate) laser beam 1606 that suitably forms respectively.Energy light beam 1604 can provide lasting (DC) energy beam.Modulated beam of light 1606 can make modulated test/triggering signal produce on wafer.Conducting element can be placed in the active area of chip/crystal grain, be transported to test structures different on the chip with test signal with energy and modulation.Like this, do not need the interconnection district of Mechanical Contact or active area outside to transmit and be activated to test structure.In the test structure or near the photoelectron signal of generation can be surveyed and measure by the detector 1602 of the test structure on the wafer 1615.In one embodiment, the time-resolved mode of detector 1602 usefulness is surveyed and measuring-signal.Test signal has caused coming the output signal from each test structure equally.Output signal will be sent on RF attenuator or the antenna, and on RF attenuator or antenna, signal will be surveyed by radio frequency detectable device 1613.Detector 1602 and radio detector 1613 can be converted to available all kinds of input/data and assay format with data processing unit 1622 communication data processing units.

The whole operations of equipment as shown in figure 16 can be by control of automatic, system and/or manual operation control.In one embodiment, the chemical control system of using a computer system 1605 or other data processing units comprise that graphic user interface (GUI) 1601, system's control 1603, wafer and test structure circuit arrangement/design and location database map 1630 (for example CAD-navigation product of being produced by Knights Technology company), excitation control 1632 and data obtain and analytic unit 1622.The parts of control system 1605 can be carried out according to being stored in to instruct on any computer-readable medium.Machine shown in Figure 16 provides the example of handling resource and computer-readable medium, and storage or execution are used to implement the instruction of the embodiment of the invention on this computer-readable medium.Especially, the numerous equipment shown in the embodiment of the invention is to comprise that processor and being used for preserves the various forms of memories with deal with data and instruction.

System controller 1603 can be carried out the automation control or the sequencing control of the mechanical aspects of all devices shown in Figure 16.Sequencing control can realize by using software or other computer executable instructions.Under the situation of manually control, can adopt GUI 1601 or other interface equipments.GUI 1601 makes the operator can select manufacturing and/or the appraisal procedure of DUT.It also is delivered to system controller 1603 with user-specified parameters and explanation.System controller 1603 is guaranteed the continuous operability of system.This has comprised in the disparate modules of system makes judgement, and the process of being carried out by disparate modules is carried out timing, thereby makes system works different times ground operation effectively.Like this, system controller 1603 has guaranteed that it can wait for other modules when a module is finished the work of oneself prior to other modules in the system.

Use wafer and test structure regional database 1630 in controller system 1605 work, and each test structure of DUT is searched and encouraged to excitation controller 1632.Comprise that the appreciation information that obtains parameter value from the exciting test structure will be stored in data acquisition and the analytic unit 1622.Can obtain and analytic unit 1622 one or more algorithms of execution or other programs by data,, comprise statistics or the quantitative analysis of DUT so that the data of performance parameter value are converted to other forms of appreciation information.

Carry out thermometrically

Figure 17 shows the crystal grain that uses together with the RF output signal of being used for according to inventive embodiments.Crystal grain 1700 can be set to energy receiver 1720 and active area in a plurality of test structure classes 1732,1734,1736 and 1738 at same place.Crystal grain energy signal in energy receiver 1720 produces, in one embodiment, crystal grain energy signal is a constant in this.In an embodiment, crystal grain 1700 also is included in the test/triggering signal receiver 1710 at same place in the active area, is used for receiving and uses test signal on the test structure that distributes.By the excitation in the application of power signal, perhaps the triggering in the application of test/triggering signal can activate these test structures.When these test structures were activated, each test structure in particular type 1732-1738 (for example, A1-A14) can show electroactive with for example form of photon, photoelectron or radio frequency signals.Probe can engage with crystal grain 1700 with contactless couple state, so that activate test/triggering signal receiver 1710 and energy receiver 1720.Energy beam is to the transmission of test/triggering receiver 1710 and energy receiver 1720, or each energy beam is distributed to the transmission of test/triggering receiver 1710 and energy receiver 1720, can finish by the probe that use is loaded with one or more energy sources.

The output signal of multiple class and detector attenuator 1730 can be positioned at the same place of active area, and use together with corresponding test structure.An embodiment produces the RF signal of exporting corresponding to test structure.The RF signal with output information comprise conversion speed, rotative speed, phase delay and other performance parameter values of corresponding test structure, series of tests structure or one group of test structure.For this embodiment, use one or more RF detector attenuators 1730, so that be output as the form of RF signal.Can equip probe detection from the RF signal that is arranged on each the detector attenuator 1730 on the crystal grain 1700.In one embodiment, each RF signal can be discerned the RF signal that spreads all over the RF signal that other chips or wafer send in conjunction with signature or other recognition mechanisms.Like this, concrete performance parameter will be associated with on the known test structure.In one embodiment, all test structure 1732-1738 will send output signal to the RF attenuator, and the transmission from the RF attenuator can be discerned each output signal based on the signature of distributing to test structure specific or certain kinds, thereby realizes obtaining simultaneously replying of a plurality of devices.Alternatively, each test structure 1732-1738 can transmit its output signal by themselves RF attenuator.

Should be appreciated that to have multiple test/triggering receiver and energy receiver, but test/triggering and energy receiver can be used for the test structure of a plurality of test structures and multiclass.Pack into the single test/triggering of a plurality of test structures and energy receiver of use allows test/triggering and energy receiver to be activated simultaneously.In one embodiment, use a plurality of tests/triggering and energy receiver, so as in different treatment steps the use test structure.In one embodiment, use a plurality of tests/triggering and energy receiver, so that the diverse location use test structure on crystal grain 1700.

According to embodiment, the RF signal is loaded with the signal set that is used for all test structures or all series of tests structures.Also exist the technology that other are used to measure this type of aggregate signal, for example in test structure set, measure the point-to-point detection system of first and last node.In addition, the method for measurement of point-to-point (inner detecting structure) can realize by for example using photoelectron signal.

Figure 18 has described the method for operation of the equipment shown in Figure 15-16 according to embodiment.

Step 1810 provides the exercisable test probe on every side that is placed on detected wafer.This comprises the location of the appointed area of the crystal grain that execution is being tested.Test probe can place around wafer exercisable.This comprises the substep of grand array and microarray.Grand array obtains the locating information that will carry out test zone corresponding to the optical mark that probe reads wafer surface.Similarly microarray will be carried out in the edge of chip.The utilization array places probe around energy on the chip and test/triggering receiver exercisable.Wafer may be in manufacturing step part or that finished.

Step 1820 make test/triggering and energy receiver with fewly contact, non-invasion and the mode that can't harm be activated, this is corresponding to reference Figure 15 and the described laser beam activation receiver of using of Figure 16.

Embodiment proposes, and in step 1830, probe comes from the electroactive of each position of chip with detection, and test structure and/or detector attenuator are arranged in chip.For example, with reference to Figure 15, photon detector 1572 is surveyed the photon that comes from the test structure interior nodes.RF detector 1574 is surveyed the RF that transmits from detector attenuator 1540.Alternatively, probe and detector 1573 use that for example electron-beam voltage is electroactive to recently surveying.Probe can be measured simultaneously, or moves so that measure between a plurality of positions on the chip.

At last, in step 1840, the electroactive manufacturing that is used to assess wafer that will in test structure, survey.

Conclusion

The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (73)

1. the method for the manufacturing of at least a portion that is used to assess wafer, described method comprises:

When described wafer is in the manufactured state of part, on a plurality of positions on the active area of the crystal grain of described wafer, determine the value of the performance parameter of appointment, wherein the performance parameter of known described appointment shows the specific fabrication process in the manufacturing, and

Based on variation in the value of the described performance parameter of described a plurality of positions, obtain appreciation information, the step of wherein said acquisition appreciation information is carried out by probe and is not influenced the availability of the chip of being made by described crystal grain, and wherein said appreciation information is how the one or more processes that are used for assessing the specific fabrication process of the manufacturing that comprises described wafer are performed.

2. method according to claim 1, the step of wherein said acquisition appreciation information comprises the variation of determining the described performance parameter value on the diverse location of described a plurality of positions.

3. method according to claim 1, the step of wherein said acquisition appreciation information comprise the spatial variations of determining in the described value of the described performance parameter of described a plurality of positions.

4. method according to claim 1, the step of wherein said acquisition appreciation information comprise the variation of determining transfer characteristic from the one or more structures that are arranged in described a plurality of positions.

5. method according to claim 1 further comprises the step that the one or more steps in the manufacturing of the performance parameter that makes described appointment and described wafer are associated.

6. method according to claim 1 further comprises and uses appreciation information to assess the step how one or more steps in the described manufacturing are performed.

7. method according to claim 1 comprises that further the attribute of the device on the performance parameter that makes described appointment and the described crystal grain is associated; Wherein said attribute is the result of the one or more steps during described wafer is made.

8. method according to claim 7, wherein, the step that the attribute of the device on the performance parameter that makes described appointment and the described crystal grain is associated comprises, on the performance parameter that makes appointment and the crystal grain any one or the grid length of a plurality of switch elements or grid width change and are associated, and it is the result of the one or more steps during described wafer is made that wherein said grid length or grid width change.

9. method according to claim 7, wherein, the step that the attribute of the device on the performance parameter that makes described appointment and the described crystal grain is associated comprises, the performance parameter that makes described appointment is associated with capacitance characteristic on any part of described crystal grain; Wherein said capacitance characteristic is the result of the one or more steps during described wafer is made.

10. method according to claim 7, wherein, the step that the attribute of the device on the performance parameter that makes described appointment and the described crystal grain is associated comprises, the performance parameter that makes described appointment is associated with resistance characteristic on any part of described crystal grain, wherein said resistance characteristic be shown in the result that makes of wafer.

11. method according to claim 7, the step that the attribute of the device on the performance parameter that wherein makes described appointment and the crystal grain is associated comprises, the performance parameter that makes described appointment is associated with electrical bias characteristic on any part of described crystal grain, and wherein said electrical bias characteristic is the result that described wafer is made.

12. method according to claim 7, wherein, described attribute is the result who comprises the one or more steps that are used for the described wafer of etching of complanation.

13. method according to claim 11, wherein, described attribute is the result who is used for carrying out one or more steps of photoetching treatment on described wafer.

14. method according to claim 7, the step that the attribute of the device on the performance parameter that wherein makes described appointment and the described crystal grain is associated comprises that the change in resistance of any one or more switch elements on the performance parameter that makes described appointment and the described crystal grain is associated; Wherein said change in resistance is the result of the one or more steps during described wafer is made.

15. method according to claim 2, the step that wherein obtains appreciation information comprise, the one or more steps in the wafer manufacturing are isolated, because described step is owing to the variation of the described value of described performance parameter.

16. method according to claim 1, the step that wherein obtains appreciation information comprises, the circuit element on each of a plurality of positions on being arranged in described crystal grain is measured (i) switching speed, (ii) circuit delay and (iii) at least one the conversion speed.

17. method according to claim 2 further comprises, uses described measured change, adjusts the step how described one or more steps in the described wafer manufacturing are performed.

18. method according to claim 2 wherein obtains the step of appreciation information, comprises obtaining to be used to make described variation and specific manufacturing step or the information that is associated in proper order.

19. method according to claim 1, wherein obtaining appreciation information comprises: from the information how one group of process acquisition is performed about one or more processes the described manufacturing, described process comprises: photoetching process, etching process, deposition process, polishing process and the process that connects.

20. method according to claim 1, the step that wherein obtains appreciation information comprises: obtain appreciation information, and do not contact or electricity on the performance of the described chip of influence.

21. one kind is used to assess the test structure that wafer is made, described test structure comprises: the combination of device and interconnection element, before finishing, described wafer manufacturing is arranged on the active area of the crystal grain on the described wafer, wherein said combination is activated electroactive to cause, the described electroactive availability that is not influenced described crystal grain or wafer by probe in detecting; And

The combination of wherein said device and interconnection element is set to, make described electroactive (i) emphasize that first manufacturing step in the manufacturing sequence has precedence over other steps in the described manufacturing sequence, and (ii) be presented at the value of described first manufacturing step on the part of described at least crystal grain or the variation or the result of attribute.

22. test structure according to claim 21, the described attribute of wherein said first manufacturing step and result are corresponding to the physical characteristic that presents in the active area of described crystal grain.

23. test structure according to claim 21, the described attribute of wherein said first manufacturing step and result are corresponding to the electrical characteristics that present in the active area of described crystal grain.

24. test structure according to claim 21, the combination of wherein said device and interconnection element are set to emphasize the described attribute or the result of described first manufacturing step, have precedence over the attribute or the result of any other step in the described manufacturing.

25. test structure according to claim 21, wherein the combination of device and interconnection element is set to only show described first manufacturing step.

26. test structure according to claim 21 is wherein said electroactive corresponding to (i) output signal, (ii) photo emissions, (iii) electronics emission and (iv) one or more in the electrical effect.

27. test structure according to claim 21, wherein said test structure is partly activated by energy beam at least, and wherein, the described electroactive photon that comprises that the switch element from the described combination of device and interconnection element produces.

28. test structure according to claim 21, wherein said test structure is partly activated by energy beam at least, and wherein said electroactive at least one that comprises in electrostatic signal, electromagnetic signal, the induced signal.

29. test structure according to claim 28, wherein said electroactive at least some other test structures that have from the described crystal grain are discerned the characteristic of described test structure.

30. test structure according to claim 21, the combination of wherein said device and interconnection element comprises the inverter of interconnection.

31. test structure according to claim 30, the combination of wherein said device and interconnection element comprise one or more CMOS inverters.

32. test structure according to claim 21, the combination of wherein said device and interconnection element comprises a plurality of transistors, and wherein said combination is set to the amplifier transistor grid length transistor gate widths and other are used for the influence of described a plurality of transistorized electrical quantitys.

33. test structure according to claim 21, the combination of wherein said device and interconnection element comprises a plurality of transistors, and wherein said combination is set to the amplifier transistor grid width transistor gate length and other are used for the influence of described a plurality of transistorized electrical quantitys.

34. test structure according to claim 21, the combination of wherein said device and interconnection element comprises a plurality of transistors and interconnect devices, and wherein said combination is set to be amplified in the influence of the interconnection resistance between described a plurality of transistor and the described interconnect devices.

35. test structure according to claim 21, the combination of wherein said device and interconnection element comprises a plurality of transistors and interconnect devices, and wherein said combination is set to be amplified in the influence of the interconnection capacitance between described a plurality of transistor and the interconnect devices.

36. test structure according to claim 21, the combination of wherein said device and interconnection element comprises a plurality of transistors and interconnect devices, and wherein said combination is set to be amplified in the influence of the grid capacitance between described a plurality of transistor and the described interconnect devices.

37. test structure according to claim 36, the combination of wherein said device and interconnection element comprises a plurality of transistors and interconnect devices, and wherein said combination is set to be amplified in the influence of the grid film that piles up on described a plurality of transistorized one or more grids.

38. test structure according to claim 36, the combination of wherein said device and interconnection element comprises a plurality of transistors and interconnect devices, and wherein said combination is set to amplify the lithography step in the described manufacturing sequence and the influence of etching step.

39. test structure according to claim 36, the combination of wherein said device and interconnection element comprises a plurality of transistors and interconnect devices, and wherein said combination is set to the influence of the expansion injection of amplifying gate-source-drain electrodes.

40. test structure according to claim 21, the combination of wherein said device and interconnection element comprises a plurality of transistors and interconnect devices, and wherein said combination is set to be amplified in the influence of the contact resistance between described a plurality of transistor and the described interconnect devices.

41. test structure according to claim 21, on the combination distribution of wherein said device and interconnection element one or more in the scribe area of a plurality of crystal grain, local grain and described wafer, the combination of wherein said device and interconnection element is excited electroactive to cause, described electroactive one or more manufacturing steps of emphasizing have precedence over other manufacturing step in described wafer is made.

42. test structure according to claim 21, the combination of wherein said device and interconnection element is energized signal activation.

43. test structure according to claim 21, the combination modulated signals of wherein said device and interconnection element activates.

44. a mechanism that is used to assess the wafer manufacturing that comprises one or more crystal grain, described mechanism comprises:

A plurality of test structures are arranged on some crystal grain in described one or more crystal grain at least, and wherein said a plurality of test structures are divided into a plurality of classes, and the described test structure of wherein every class comprises:

The combination of device and interconnection element was arranged on the described crystal grain before described manufacturing is finished, wherein said combination be activated with cause can be by probe in detecting electroactive, and do not influence the availability of making the chip that forms by described crystal grain after finishing;

Each combination electroactive identification the indication attribute of one or more steps or value of result in described manufacturing of being provided so that (i) described combination wherein, and (ii) described combination electroactive can not show in described manufacturing the attribute of another step or result at least;

Wherein said wafer comprises the described test structure of a class of each manufacturing step that is used for one group of appointment manufacturing step;

Wherein the value of each manufacturing step in a described class testing structure can be used individually, perhaps combines with other value from one or more manufacturing steps of another kind of test structure, determines the information about the result of specific manufacturing step.

45. according to the described mechanism of claim 44, wherein said a plurality of test structures are triggered simultaneously.

46. according to the described mechanism of claim 45, wherein from least some described electroactive identification of described a plurality of test structures from those test structures of other test structure on the described wafer.

47. according to the described mechanism of claim 46, wherein at least some the common checkout gear of described electroactive use from described a plurality of test structures detects, described checkout gear scans at least some described wafers, and does not come in contact.

48. according to the described mechanism of claim 44, wherein by the described manufacturing step of one or more described electroactive indication of described a plurality of test structures corresponding to the physical characteristic that is presented in the described chip.

49. according to the described mechanism of claim 44, wherein by the described manufacturing step of one or more described electroactive performance of described a plurality of test structures corresponding to the electrical characteristics that are presented in the described chip.

50. according to the described mechanism of claim 44, each of wherein said a plurality of test structures excited by common energy beam at least in part.

51. according to the described mechanism of claim 50, wherein said a plurality of test structures one or more described electroactive comprises the photon that the switch element from the combination of the device of described one or more test structures and interconnection element produces.

52. according to the described mechanism of claim 44, one or more described electroactive comprising of wherein said a plurality of test structures, ring at least a in electrostatic signal, electromagnetic signal or the induced signal produce in the output that is triggered by in one or more test structures each.

53. according to the described mechanism of claim 52, each radiofrequency signal in wherein said one or more test structures has the characteristic of identification from the test structure of other test structures on the described chip.

54. according to the described mechanism of claim 44, described a plurality of test structures described electroactive detected, and do not contact with described chip manufacturing.

55. according to the described mechanism of claim 44, the combination of wherein said one or more test structures comprises a plurality of interconnection inverters.

56. according to the described mechanism of claim 55, the combination of wherein said one or more test structures comprises one or more CMOS inverters.

57. according to the described mechanism of claim 44, one or more combination of wherein said a plurality of test structures comprises a plurality of transistors, and each combination of wherein said one or more test structures is set to minimize the relation that is used between described a plurality of transistorized transistor gate length and the transistor gate widths.

58. according to the described mechanism of claim 44, the combination of wherein said device and interconnection element comprises a plurality of transistors, and wherein said combination is set to the amplifier transistor grid width to transistor gate length and the influence that is used for described a plurality of transistorized other electrical quantitys.

59. according to the described mechanism of claim 44, the combination of wherein said device and interconnection element comprises a plurality of transistors and an interconnect devices, wherein said combination is set to amplify the influence of interconnection resistance.

60. according to the described mechanism of claim 44, the combination of wherein said device and interconnection element comprises a plurality of transistors and an interconnect devices, wherein said combination is set to amplify the influence of interconnection capacitance.

61. according to the described mechanism of claim 44, the combination of wherein said device and interconnection element comprises a plurality of transistors and an interconnect devices, wherein said combination is set to the influence of amplifying gate electrode capacitance.

62. according to the described mechanism of claim 61, the combination of wherein said device and interconnection element comprises a plurality of transistors and an interconnect devices, wherein said combination is set to amplify the influence of the grid film that piles up on the grid.

63. according to the described mechanism of claim 61, the combination of wherein said device and interconnection element comprises a plurality of transistors and an interconnect devices, wherein said combination is set to amplify gate patterns and etched influence.

64. according to the described mechanism of claim 61, the combination of wherein said device and interconnection element comprises a plurality of transistors and an interconnect devices, wherein said combination is set to increase the influence that grid-source-the leakage expansion is injected.

65. according to the described mechanism of claim 44, the combination of wherein said device and interconnection element comprises a plurality of transistors and an interconnect devices, wherein said combination is set to amplify the influence of contact resistance.

66. according to the described mechanism of claim 44, the combination of wherein said device and interconnection element comprises a plurality of transistors and an interconnect devices, wherein said combination is set to amplify the influence of contact resistance.

67. according to the described mechanism of claim 44, wherein, the combination of described device and interconnection element is set to emphasize attribute and the result that attribute in the described given manufacturing step and result are better than any other step in the described manufacturing.

68. according to the described mechanism of claim 44, wherein, the combination of described device and interconnection element is set to only show given manufacturing step.

69. according to the described mechanism of claim 44, wherein, it is described electroactive corresponding to (i) output signal, (ii) photo emissions, (iii) electronics emission and (iv) one or more in the electrical effect that described combination causes.

70. according to the described mechanism of claim 44, wherein, it is described electroactive corresponding to (i) output signal, (ii) photo emissions, (iii) electronics emission and (iv) one or more in the electrical effect that described combination causes.

71. according to the described mechanism of claim 70, wherein, the one or more of described a plurality of test structures are partly activated by energy beam, and wherein, the described electroactive photon that comprises that the switch element from the described combination of device and interconnection element produces.

72. according to the described mechanism of claim 44, wherein, the one or more of described a plurality of test structures are partly activated by energy beam, and wherein, the described electroactive photon that comprises that the switch element from the described combination of device and interconnection element produces.

73., wherein, have the characteristic that at least some other test structures from the described crystal grain are discerned described test structure from described one or more test structures described electroactive according to the described mechanism of claim 72.

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