CN100531514C - 防止短路的印刷电路板结构 - Google Patents
防止短路的印刷电路板结构 Download PDFInfo
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- CN100531514C CN100531514C CNB2004100281389A CN200410028138A CN100531514C CN 100531514 C CN100531514 C CN 100531514C CN B2004100281389 A CNB2004100281389 A CN B2004100281389A CN 200410028138 A CN200410028138 A CN 200410028138A CN 100531514 C CN100531514 C CN 100531514C
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0577—Double layer of resist having the same pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0588—Second resist used as pattern over first resist
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
一种防止短路的印刷电路板结构,所述印刷电路板上具有一用于安装芯片的焊点阵列,所述芯片具有若干接脚,所述焊点阵列包括若干对应于所述接脚的焊点,所述印刷电路板上还具有一层用来防止所述接脚间短路的阻焊漆,通过在所述焊点阵列中无焊点分布的区域的阻焊漆上印刷有一层用来增加焊点的容锡量的丝网印刷面来防止芯片间的接脚短路,由于印刷丝网印刷面是制作印刷电路板过程中必不可少的工序之一,故采用上述防止短路的方法也不需要增加额外的制作工序,只需在印刷电路板布线设计过程中根据需要设定好丝网印刷面的面积大小及所在位置即可。
Description
【技术领域】
本发明涉及一种防止短路的印刷电路板结构,特别是一种能够在过锡过程中防止芯片接脚短路的印刷电路板结构。
【背景技术】
印刷电路板(Printed Circuit Board,PCB)是一般电子装置内部不可缺少的部件之一,其上分布有半导体集成电路芯片等多种与装置运作相关的电子元件,上述电子元件通过印刷电路板上的布线组成一定的应用电路,从而使电子装置得以正常运作。印刷电路板在布线时会在有电子元件存在的位置设置一个或多个焊点(PAD,也称为焊盘),通过引脚或锡珠等方式将电子元件电性连接至印刷电路板。
目前,随着电子技术的快速发展,电脑等电子装置的运算处理速度不断提高,这就要求印刷电路板上的集成电路芯片具有更高的集成度,以实现更快的运算速度和更强的处理功能。在集成电路芯片集成度提高的同时,必然使其单位面积上的接脚(PIN)数目不断增加。以当前电脑主机板常用的球栅阵列(Ball Grid Array,BGA)封装为例,其一块芯片的接脚数甚至已超过400个。由于芯片本身的面积并未发生很大变化,故接脚数的增加会使得接脚间的间距减小,而印刷电路板上焊点数与芯片的接脚数是相应的,芯片接脚数的增多使焊点间的间距随之减小。在印刷电路板的制作过程中,若阻焊漆(Solder Mask)的保护不是很好,在后续的过锡过程中芯片下压时会使锡从焊点中溢出,从而造成芯片接脚间短路。
在美国专利申请第6239383号中揭露了一种防止球栅阵列封装芯片焊接时短路的结构,其方法是在芯片底部锡珠的周围加上多个支撑垫,上述支撑垫的高度小于锡珠的高度,且是由具有比锡珠更高熔点的金属制成,当锡珠熔化时,支撑垫会将芯片支撑于一合适的高度使其不会过分下压,从而避免锡溢出造成短路。但现有各种集成电路芯片是在不增大其整体面积的基础上来尽量实现多接脚数,其底部除必要的接脚设置部位外并无太大的额外空间,故上述支撑垫的设置较为困难,且由于原有的芯片制作和安装工序中并未设置支撑垫的步骤,需增加一多余的步骤来实现上述方法,会使电子装置的制成变得更为繁琐。
【发明内容】
本发明的目的在于提供一种防止短路的印刷电路板结构,特别是指一种无需增加额外工序即可在过锡过程中防止芯片接脚短路的印刷电路板结构。
一种防止短路的印刷电路板结构,所述印刷电路板上具有一用于安装芯片的焊点阵列,所述芯片具有若干接脚,所述焊点阵列包括若干对应于所述接脚的焊点,所述印刷电路板上还具有一层用来防止所述接脚间短路的阻焊漆,通过在所述焊点阵列中无焊点分布的区域的阻焊漆上印刷有一层用来增加焊点的容锡量的丝网印刷面来防止芯片间的接脚短路,由于印刷丝网印刷面是制作印刷电路板过程中必不可少的工序之一,故采用上述防止短路的方法也不需要增加额外的制作工序,只需在印刷电路板布线设计过程中根据需要设定好丝网印刷面的面积大小及所在位置即可。
本发明与现有技术相比具有以下优点:通过调整印刷电路板自身的构造来防止安装于其上的芯片接脚短路,该方法简单易行,且无需增加额外的制作工序。
【附图说明】
下面参照附图结合实施例对本发明作进一步说明。
图1是本发明印刷电路板的焊点阵列在通常情况下的俯视图。
图2是本发明印刷电路板上的芯片接脚间发生短路时的截面图。
图3是本发明印刷电路板焊点阵列在加入一丝网印刷面后的俯视图。
图4是本发明印刷电路板在加入一丝网印刷面后的截面图。
【具体实施方式】
请参阅图1至图2。图1为一印刷电路板10上的焊点阵列30,其对应于一芯片50,该芯片50为一球栅阵列封装芯片。图中所示仅为该焊点阵列30的一部分,实际上,上述焊点阵列30包含的焊点40数目要多得多。例如在一台个人电脑中,根据英特尔(Intel)公司的奔腾4(Pentium 4)处理器架构,一块中央处理器芯片底部的接脚数可以达到478个。与之相应的,印刷电路板10也需在一较小的布线空间上形成多达478个焊点,故焊点阵列30中的焊点40分布较为密集,其各个焊点40间的相互距离非常小。
在将芯片50安装到印刷电路板10上时,通常是采用表面贴装工艺,先在芯片50的接脚与其对应的焊点40间加入锡块70,再通过回焊炉使锡块70熔化,其即可将芯片50的接脚与焊点阵列30中的焊点40一一连接,从而实现芯片50与印刷电路板10间的电性导通。此时在印刷电路板10表面印刷有一层阻焊漆80,用来防止芯片50接脚间的相互短路。但在锡块70熔化时,若该锡块70的体积较大,有时就会使锡从焊点41中溢出,虽然其溢出量较小,但由于焊点40间的距离很小,一旦溢出锡72超出阻焊漆80所能保护的限度,流到其相邻的焊点43,就会致使芯片50引脚间短路,从而影响电子装置工作。
请参阅图3至图4。在制作印刷电路板10时,其阻焊漆80上另外会印刷上一层丝网印刷面(silk screen。也称为图标面,legend)。通常在丝网印刷面上会印上文字与符号,来标示出各电子元件的名称,以获知其在印刷电路板10上的位置或者其它相关信息。在图3中,将焊点阵列30非焊点40的地方用一层丝网印刷面100覆盖住。由于丝网印刷面100具有与阻焊漆80一样的绝缘及阻焊特性,采用上述方法后,即等同于在阻焊漆80上又加入了一保护层来配合阻焊漆80起双重保护作用。如图4所示,当锡块70熔化时,如果有可能产生锡从焊点41中溢出的现象,则此时溢出的锡量一般较小。所以加入的丝网印刷面100可以使焊点41的容锡量比图2中有所增加,从而能很好地避免锡从焊点41中溢出造成短路。此外,由于印刷丝网印刷面是制作印刷电路板过程中必不可少的工序之一,故采用上述防止短路的方法也不需要增加额外的制作工序,只需在印刷电路板布线设计过程中根据需要设定好丝网印刷面100的面积大小及所在位置即可。
Claims (5)
1.一种防止短路的印刷电路板结构,所述印刷电路板上具有一用于安装芯片的焊点阵列,所述芯片具有若干接脚,所述焊点阵列包括若干对应于所述接脚的焊点,所述印刷电路板上还具有一层用来防止所述接脚间短路的阻焊漆,其特征在于:在所述焊点阵列中无焊点分布的区域的阻焊漆上印刷有一层用来增加焊点的容锡量的丝网印刷面。
2.如权利要求1所述的防止短路的印刷电路板结构,其特征在于:所述芯片为一球栅阵列封装芯片。
3.如权利要求2所述的防止短路的印刷电路板结构,其特征在于:所述芯片是通过一表面贴装工艺安装于所述印刷电路板上。
4.如权利要求1所述的防止短路的印刷电路板结构,其特征在于:所述印刷电路板是存在于一个人电脑内部。
5.如权利要求1所述的防止短路的印刷电路板结构,其特征在于:所述丝网印刷面也印刷于所述印刷电路板的其它区域以标示与所述印刷电路板相关的信息。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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CNB2004100281389A CN100531514C (zh) | 2004-07-12 | 2004-07-12 | 防止短路的印刷电路板结构 |
US11/176,054 US20060006533A1 (en) | 2004-07-12 | 2005-07-07 | Motherboard structure for preventing short circuit |
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CNB2004100281389A CN100531514C (zh) | 2004-07-12 | 2004-07-12 | 防止短路的印刷电路板结构 |
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CN1722932A CN1722932A (zh) | 2006-01-18 |
CN100531514C true CN100531514C (zh) | 2009-08-19 |
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CNB2004100281389A Expired - Fee Related CN100531514C (zh) | 2004-07-12 | 2004-07-12 | 防止短路的印刷电路板结构 |
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CN (1) | CN100531514C (zh) |
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Publication number | Priority date | Publication date | Assignee | Title |
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US20060064773A1 (en) * | 2004-06-28 | 2006-03-23 | Pioneer Hi-Bred International, Inc. | Cell cycle polynucleotides and polypeptides and methods of use |
JP5074738B2 (ja) * | 2006-10-24 | 2012-11-14 | リンテック株式会社 | 複合型半導体装置用スペーサーシート、及び複合型半導体装置の製造方法 |
CN111654981A (zh) * | 2020-07-02 | 2020-09-11 | 四川耀讯电子科技有限公司 | 一种pcba柔性电路板的smt回流焊工艺 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1113069A (zh) * | 1994-05-06 | 1995-12-06 | 索尼公司 | 印刷电路板 |
US5956843A (en) * | 1995-02-17 | 1999-09-28 | International Business Machines | Multilayer printed wiring board and method of making same |
Family Cites Families (15)
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US5531020A (en) * | 1989-11-14 | 1996-07-02 | Poly Flex Circuits, Inc. | Method of making subsurface electronic circuits |
US5156997A (en) * | 1991-02-11 | 1992-10-20 | Microelectronics And Computer Technology Corporation | Method of making semiconductor bonding bumps using metal cluster ion deposition |
JP3152834B2 (ja) * | 1993-06-24 | 2001-04-03 | 株式会社東芝 | 電子回路装置 |
FR2728392A1 (fr) * | 1994-12-16 | 1996-06-21 | Bull Sa | Procede et support de connexion d'un circuit integre a un autre support par l'intermediaire de boules |
FR2734983B1 (fr) * | 1995-05-29 | 1997-07-04 | Sgs Thomson Microelectronics | Utilisation d'un micromodule comme boitier de montage en surface et procede correspondant |
US6008071A (en) * | 1995-09-20 | 1999-12-28 | Fujitsu Limited | Method of forming solder bumps onto an integrated circuit device |
JPH11220234A (ja) * | 1998-01-29 | 1999-08-10 | Smk Corp | 回路基板 |
US6329712B1 (en) * | 1998-03-25 | 2001-12-11 | Micron Technology, Inc. | High density flip chip memory arrays |
TW434767B (en) * | 1998-09-05 | 2001-05-16 | Via Tech Inc | Package architecture of ball grid array integrated circuit device |
US6657313B1 (en) * | 1999-01-19 | 2003-12-02 | International Business Machines Corporation | Dielectric interposer for chip to substrate soldering |
US6271107B1 (en) * | 1999-03-31 | 2001-08-07 | Fujitsu Limited | Semiconductor with polymeric layer |
JP2001305570A (ja) * | 2000-04-24 | 2001-10-31 | Nec Corp | 表示パネルモジュール及びその製造方法 |
JP2003264256A (ja) * | 2002-03-08 | 2003-09-19 | Hitachi Ltd | 半導体装置 |
JP3780996B2 (ja) * | 2002-10-11 | 2006-05-31 | セイコーエプソン株式会社 | 回路基板、バンプ付き半導体素子の実装構造、バンプ付き半導体素子の実装方法、電気光学装置、並びに電子機器 |
JP2005026316A (ja) * | 2003-06-30 | 2005-01-27 | Tohoku Pioneer Corp | プリント基板及び電子機器 |
-
2004
- 2004-07-12 CN CNB2004100281389A patent/CN100531514C/zh not_active Expired - Fee Related
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2005
- 2005-07-07 US US11/176,054 patent/US20060006533A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1113069A (zh) * | 1994-05-06 | 1995-12-06 | 索尼公司 | 印刷电路板 |
US5956843A (en) * | 1995-02-17 | 1999-09-28 | International Business Machines | Multilayer printed wiring board and method of making same |
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CN1722932A (zh) | 2006-01-18 |
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