CN100531107C - Method and system for seamless dual switching in a port bypass controller - Google Patents
Method and system for seamless dual switching in a port bypass controller Download PDFInfo
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- CN100531107C CN100531107C CNB2004101040680A CN200410104068A CN100531107C CN 100531107 C CN100531107 C CN 100531107C CN B2004101040680 A CNB2004101040680 A CN B2004101040680A CN 200410104068 A CN200410104068 A CN 200410104068A CN 100531107 C CN100531107 C CN 100531107C
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Abstract
The invention relates to operation of a seamless port bypass controller in a memory system. For example, the invention can comprise a first port of the port bypass controller used for receiving input signals; the invention also comprises at least one controller from a plurality of controllers, and the controller is used for selecting at least one second port which is then linked with the first port; at least one controller can convert at least one part of received input signals from the first port to at least one second port, and the second port is unnecessary to be initialized or rearranged. Moreover, a repeater can be used for repeating at least one part of the received input signals to the second port, and the second port is unnecessary to be initialized or rearranged. Furthermore, a retiming machine can be used for generating a retiming signal corresponding to at least one part of the received input signals and converting the retiming signals to at least the second port, and the second port is unnecessary to be initialized or rearranged.
Description
Technical field
The present invention relates to port bypass controller.More particularly, some embodiments of the invention relate to the method and system that carries out seamless two conversions in a port bypass controller.
Background technology
Fig. 1 a is the block diagram of a legacy network environment, wherein shows the deployment scenarios of various communications and storage entity.With reference to figure 1a, it has provided a Wide Area Network (WAN) 110, and it comprises 102,104,106,108 and router ones 32 of a plurality of LAN (LAN).LAN 102,104,106,108 connects by router one 32.Comprise personal computer (PC) 112,116,120 among the LAN 102, server 126,128 and data storage cell 114,118,122,124 and 130.
Data storage cell 114 can be connected to PC 112, and data storage cell 118 can be connected to PC 116, and data storage cell 122 can be connected to PC 120.Data storage cell 124 can be connected to server 126, and data storage cell 130 can be connected to server 128.Also can comprise a plurality of PC among the LAN 104,106,108, data storage cell and server, they can be by being configured with LAN 102 similar modes.
Be in operation, PC 112,116,120 can communicate each other by LAN 102, and communicates with server 126,128.PC 112,116,120 can communicate with communication entity, and these communication entities are connected to LAN 104,106,108 by router one 32.In addition, the communication entity that is connected to LAN 104,106,108 also can be by router one 32 and PC 112,116,120, and server 126,128 and data storage cell 114,118,122,124,130 communicate.
The legacy network environment configurations major defect shown in Fig. 1 a, be PC connection or with being connected and the connection of server or may seriously influence the performance of a communication network of LAN with the bandwidth that is connected of LAN.And the processing bandwidth of PC and server may be introduced time delay and further reduce systematic function, will cause the increase of system wait time like this.For example, for from data storage cell 122 acquired informations, PC 112 will communicate with PC 120.Thereby slower if the network of connection PC 112 and PC 120 is connected, these connections will limit the communication between PC 112 and the PC 120 so.Under the low situation of the processing bandwidth of PC 112 and PC 120, the communication performance between PC 112 and the PC 120 may be restricted or reduce more.And at run duration, for from data storage cell 122 acquired informations, multiple pc can be attempted to communicate with PC 120, and PC 112 is also communicating with PC120 simultaneously.At this moment, because attempt to increase from the communication entity number of data storage cell 122 acquired informations, the limited processing bandwidth of PC 112 and PC 120 and communication bandwidth can cause further time delay and increase the stand-by period.Therefore, PC 112,116,120 just becomes bottleneck.
Another example, for from data storage cell 124 acquired informations, PC 120 will communicate with server 126.Thereby, being connected slowly if connect the network of PC 120 and server 126, these connections will limit communicating by letter between PC 120 and the server 126 so.Under the low situation of the processing bandwidth of PC 120 and server 126, the communication between PC 120 and the server 126 may be restricted or reduce more.And at run duration, for from data storage cell 124 acquired informations, multiple pc can be attempted to communicate with server 126 such as PC 112,116, and PC 120 is also communicating with server 126 simultaneously.At this moment, because attempt to increase from the number of data storage cell 124 acquired informations, the limited processing bandwidth of PC120 and server 126 and communication bandwidth can cause further time delay and increase the stand-by period.Although being connected bandwidth and can increasing along with the connection that increases high bandwidth more between PC and server and the LAN, this can cause cost to increase.Similarly, handling bandwidth also can increase along with increasing faster processor, but its cost may be unacceptable.
Fig. 1 b is square frame Figure 130 of a legacy network environment after the improvement, wherein shows the deployment scenarios of various communications and storage entity, and it still has some defectives of network environment shown in Fig. 1 a.With reference to figure 1b, it has provided a Wide Area Network (WAN) 110, and it has comprised 102,104,106,108 and router ones 32 of a plurality of LAN (LAN).LAN 102,104,106,108 connects by router one 32.LAN 102 comprises personal computer (PC) 112,116,120, server 126,128 and data storage cell 132 and 134.
Data storage cell 134 can comprise a plurality of storage devices, and such as a disk array, it can be connected with server 126.Data storage cell 136 also can comprise a plurality of storage devices, and such as a disk array, it can be connected with server 128.LAN 104,106,108 also can comprise a plurality of PC, data storage cell and server they can be by being configured with LAN 102 similar modes.
At run duration, PC 112,116,120 can communicate each other by LAN 102, and communicates with server 126,128.PC 112,116,120 also can communicate with communication entity, and these communication entities are connected to LAN 104,106,108 by router one 32.In addition, be connected to LAN104,106,108 communication entity also can with PC 112,116,120, server 126,128 and data storage cell 134,136 communicate.
When comparing, server 126,128 can be disposed to such an extent that make it to have and handle bandwidth than the bigger communication of PC 112,116,120 with the network environment of Fig. 1 a.Although the configuration of the network environment of Fig. 1 b can have more performance than the network environment of Fig. 1 a, a defective of Fig. 1 b configuration is that server 126,128 becomes present bottleneck.In this respect, because be connected to server, the number that requires information to connect from storage entity 134,136 increases, and server oneself will become bottleneck and cause the reduction of systematic function.For example, the network communications entity that is connected to LAN 104,106,108 when PC 112,116,120 and other is simultaneously from server 126 and/or 128 acquired informations the time, because server 126 can not have the ability to handle all connections, some connections just may be stopped up.
Fig. 1 c is square frame Figure 140 of an improved legacy network environment, wherein shows the deployment scenarios of various communications and storage entity, and it still has some defectives of network environment shown in Fig. 1 a and Fig. 1 b.With reference to figure 1c, wherein provided a Wide Area Network (WAN) 110, it has comprised 102,104,106,108, one router ones 32 of a plurality of LAN (LAN) and storage area networks (SAN) 142.LAN 102,104,106,108 connects by router one 32.Comprise PC 112,116,120 and server 126,128 among the LAN 102.Comprise data storage cell 144,146 and 148 in the storage area networks (SAN) 142.
Data storage cell 144,146,148 can comprise a plurality of storage devices, and such as a disk array, they can be connected with server 126,128 by storage area networks 142.Among the LAN 104,106,108 each also can comprise a plurality of PC and server, and they can be by being configured with LAN 102 similar modes.Be connected with LAN 104,106,108 one or more service device also can be connected with storage area networks 142, perhaps communicate by storage area networks 142 and data storage cell 144,146,148.Because any one among the LAN 102,104,106,108 can be communicated by letter with storage area networks 142 directly or indirectly, so the information that is stored in the data storage cell 144,146,148 can be acquired easilier, and the said bottleneck relevant with Fig. 1 b network environment with Fig. 1 a before can not suffering from.
Fig. 2 is the block diagram of a typical LAN (LAN), and it is connected with storage area networks (SAN).With reference to figure 2, LAN 202,204,206,208 and storage area networks (SAN) 240 are arranged wherein.LAN 202 can comprise PC 210,212,214 and server 216,218.Storage area networks 240 can comprise a Fibre Channel (FC) transducer 224, file server (FS) 226,228,230, and a plurality of data storage cell 232,234,236.In the data storage cell 232,234,236 each can comprise a plurality of Fibre Channel hard disks.
Storage area networks 240 is by being connected with LAN 202 with the host bus adaptor (HBA) 220,222 of server by the interface combination.At this moment, host bus adaptor 220 is configured to such an extent that can combine by interface with Fibre Channel transducer 224 and server 216, and host bus adaptor 222 is configured to such an extent that can combine by interface with Fibre Channel transducer 224 and server 218.File server 226 can be connected with data storage cell 232, and file server 228 can be connected with data storage cell 234, and file server 230 can be connected with data storage cell 236.
Server 216,218 can comprise a plurality of ports, this port can with a data storage device, for example a hard disk is connected.In a plurality of ports of described file server, each all can with single memory cell, for example hard disk electricity and/or light connect.At this moment, each in the file server 226,228,230 is all supported to be connected with the point-to-point of a specific hard disk.
Connection between Fibre Channel transducer 224 convertible servers and the file server.For example, in order to distinguish access data storage unit 232,234,236, Fibre Channel transducer 224 can be transformed into the file server 226,228,230 any one connecting from server 216.Similarly, in order to distinguish any one or the more data memory cell in the access data storage unit 232,234,236, Fibre Channel transducer 224 can be transformed into the file server 226,228,230 any one connecting from server 218.
Be in operation, PC 214 can utilize any one in the server 216,218, and any one from file server 232,234,236 recaptured information.For example, in order to recapture information from file server 236, PC 214 can set up one with server 216 and be connected, and Fibre Channel transducer 224 can be transformed into file server 236 from server 216 connecting then.In another example, in order to recapture information from file server 234, a communicator that is connected with LAN 204 can connect with server 218.Fibre Channel transducer 224 can be transformed into file server 234 from server 218 connecting.
Although the network environment of Fig. 2 is compared with the legacy network environment among Fig. 1 a, Fig. 1 b and Fig. 1 c, increased performance effectively, be present between each hard disk and each the plural groups file server port but a major defect of Fig. 2 network environment is its point-to-point communication chain.Especially, be present in the operation of the point-to-point communication chain between each hard disk and the file server port and safeguard it all is very expensive.
Because the availability of the data professional lifeline that is each, data degradation are not only and can not be tolerated, and its loss may interrupt day-to-day operation, and causes the remarkable loss of operating income.In order to improve the availability of data, need have the higher MTBF parts of (mean free error time), and require system will obey the program groups or the battery of tests that also can pass through a strictness.For example, in order to prevent data degradation, use the storage system of Fibre Channel (FC) driver to be designed to have a double loop structure, such structure helps to realize data access by second loop that it is redundant that described second loop can be used for providing.
Fig. 3 is a block diagram that traditional fibre pipeline arbitration loop is arranged, it can be used for connecting a plurality of hard disks, and these hard disks may be present in the storage entity of Fig. 1 a, Fig. 1 b, Fig. 1 c and Fig. 2.With reference to figure 3, it has provided a server 302, host bus adaptor 304 and a plurality of hard disk, called after 306a, 306b, 306c, 306d, 306e, 306f, 306g, 306h, 306i, 306j and 306k.Among these hard disks 306a-306k each can comprise a port bypass controller and repeater (PBC/R) piece.For providing redundant, each port bypass controller and each repeater piece can comprise a dual-port structure.
On Fibre Channel arbitration loop, or be called between each hard disk on the loop and can share the bandwidth that distribute to this loop.Communication on the loop is based on point-to-point, betides between an initial hard disk and the order ground hard disk.In between any one given period that in the loop, takes place to communicate by letter, only there are two ports to enliven simultaneously.These two active ports comprise the port and the port of communicating by letter with these end product that wins the loop arbitration.The port that wins the loop arbitration can be called initial port, then can be called order ground port with that port that wins the port communication of arbitrating in the loop.Because between initial port and order ground port, have point-to-point communication, thus the traffic according to the rules route between initial port and order ground port, send.In communication period, except initial port in the loop and order ground port, but also received frame of other ports, and the frame of receiving is forwarded to next port in the loop.Received frame can be Frame and control frame, such as confirming and ready frame.A major defect of the reception and the scheme of forwarding is the negative consequence that has increased the stand-by period like this, and this consequence can be introduced and bring to each subsequent port in the loop all.
The enforcement in some Fibre Channel arbitration loop is all based on analog port bypass controller (PBC) and repeater (R), such as the example of having set forth in Fig. 3.Because a hard disk may influence the operation of all other hard disks in the loop potentially,, thereby usually can cause catastrophic loop fault so the combination of port bypass controller and loop structure just is easy to the generation problem.For the physical location of definite and/or separating circuit fault or faulty hard disk, the operator of port bypass controller or maintenance personnel need one by one insert and/or remove each hard disk.And the overwhelming majority in these faults is associated with signal integrity.
The present invention is further illustrated below in conjunction with the drawings and specific embodiments, and by contrasting with the present invention, those of ordinary skill in the art can find out other limitations and the shortcoming of tradition and prior art scheme significantly.
Summary of the invention
Some embodiments of the invention relate to the method and system that carries out seamless two conversions in a port bypass controller.The method that is used for seamless port bypass controller operation can comprise from first port of a port bypass controller receiving an input signal, selects at least one second port, makes it and described first port link.At least a portion in the described input signal that receives can by from described first port translation to described at least second port, and without initialization or reconfigure described second port.Also at least a portion in the described input signal that receives is relayed to described second port in this method, and without initialization or reconfigure the step of described second port.Also can produce an again timing signal corresponding, and it is transformed into described at least second port with at least a portion in the described input signal that receives, and without initialization or reconfigure described second port.
Can obtain timing data from the described input signal that receives, at least one transmit path in described second port can be driven by at least a portion in the timing data that is obtained from the described input signal that receives.At least one port can be by bypass, and at least a portion in the described input signal that receives can be from first port translation at least one the 3rd port link, and without initialization or reconfigure the 3rd port.At least one of the described input signal that receives can be sent back to described at least second port from first port.
Another feature of the present invention, when one the 3rd port at least a portion in the described input signal that receives being relayed in the link, can be simultaneously for described second port produces an again timing signal corresponding with at least a portion in the described input signal that receives, and without initialization or reconfigure second port and/or the 3rd port.In the method, also further be all ports of first FC-core bypass in the link, and at least a portion in the described input signal that receives is transformed at least one port in one the 2nd FC-core in the link.The speed of the described input signal that receives can be detected, and can the word boundary in the described input signal that receives be done alignment handle based on the detection rates of the described input signal that receives.
Another specific embodiment of the present invention provides a kind of machine readable memory, wherein there is computer program, has the coded portion that to be carried out by machine in the described computer program at least, thereby make described machine can carry out above-mentioned step, to realize described seamless port bypass controller operation.
The system that is used for the operation of seamless port bypass controller of the present invention can comprise one first port of port bypass controller, and it is used to receive an input signal; At least one selector, it is used to select at least one second port, makes it and described first port link.At least one selector can be with at least a portion in the described input signal that receives from described first port translation to described at least second port, and without initialization or reconfigure described second port.Also can at least a portion in the described input signal that receives be relayed to described second port by a repeater, and without initialization or reconfigure described second port.Also can by one again time clock produce an again timing signal corresponding with at least a portion in the described input signal that receives, and it is transformed into described at least second port, and without initialization or reconfigure described second port.CDR and/or an interpolater can obtain timing data from the described input signal that receives, and utilize at least a portion of the timing data that is obtained to remove to drive at least one transmit path of second port.
This system may further include a bypass selector, it can bypass at least one port in the link.The bypass selector can be at least one the 3rd port from first port translation to link of at least a portion in the described input signal that receives, and without initialization or reconfigure the 3rd port.The bypass selector also can be first FC-core bypass all of the port in the link, and at least a portion in the described input signal that receives is transformed at least one port of one the 2nd FC-core in the link.
A loopback selector can be transmitted back to described at least second port at least a portion in the described input signal that receives from first port.When repeater is relayed at least a portion in the described input signal that receives one the 3rd port in the link, one again time clock can be simultaneously for described second port produces an again timing signal corresponding with at least a portion in the described input signal that receives, and without initialization or reconfigure second port and/or the 3rd port.This system can comprise further that a speed detector and a word adorn device synchronously.Speed detector can detect the speed of the described input signal that receives, and word is adorned device synchronously and can be adjusted at the word boundary in the described input signal that receives based on the speed by the described input signal that receives that speed detector detected.
According to a feature of the present invention, a kind of method that is used for seamless port bypass controller operation is provided, may further comprise the steps in this method:
First port at a port bypass controller receives an input signal;
Select at least one second port, make it and described first port link; And
With at least a portion in the described input signal that receives from described first port translation to described at least second port, and without initialization or reconfigure described second port.
In preferred version of the present invention, this method also comprises at least a portion in the described input signal that receives is relayed to described second port, and without initialization or reconfigure the step of described second port.
In preferred version of the present invention, the method also comprises again timing signal corresponding with at least a portion in the described input signal that receives of generation, and it is transformed into described at least second port, and without initialization or reconfigure the step of described second port.
In preferred version of the present invention, the method also comprises the step that obtains timing data from the described input signal that receives.
In preferred version of the present invention, the method further comprises at least a portion of utilizing the above-mentioned timing data that obtains, drives the step of at least one transmit path of described second port, and this timing data is from the described input signal that receives.
In preferred version of the present invention, the method has further comprised:
At least one port in the described link of bypass;
With at least one the 3rd port from described first port translation to link of at least a portion in the described input signal that receives, and without initialization or reconfigure described the 3rd port.
In preferred version of the present invention, the method has further comprised the step that at least a portion in the described input signal that receives is transmitted back to described at least second port from described first port.
In preferred version of the present invention, the method further comprises, when at least a portion in the described input signal that receives being relayed in the described link one the 3rd port, be the step that described second port produces an again timing signal corresponding with at least a portion in the described input signal that receives.
In preferred version of the present invention, the method further comprises, is the step of a FC-core bypass all of the port in the described link, and at least a portion in the described input signal that receives is transformed at least one port of the 2nd FC-core in the link.
In preferred version of the present invention, the method further comprises:
Detect a speed of the described input signal that receives; And
Based on the speed of the described input signal that receives that detects, the word boundary in the described input signal that receives is carried out registration process.
On the other hand, the invention provides a kind of machine readable memory, wherein have computer program, have a coded portion that is used for seamless port bypass controller operation in the described computer program at least, described at least one coded portion can be finished following steps by a machine execution:
First port at a port bypass controller receives an input signal;
Select at least one second port, make it and described first port link; And
With at least a portion in the described input signal that receives from described first port translation to described at least second port, and without initialization or reconfigure described second port.
In preferred version of the present invention, further comprise in the described machine readable memory at least a portion in the described input signal that receives being relayed to described at least second port, and without initialization or reconfigure the coding of described second port.
In preferred version of the present invention, further comprise in the described machine readable memory and can produce an again timing signal corresponding with at least a portion in the described input signal that receives, and it is transformed into described at least second port, and without initialization or reconfigure described second port coding.
In preferred version of the present invention, further comprise the coding of the timing data that can from the described input signal that receives, obtain in the described machine readable memory.
In preferred version of the present invention, comprise further in the described machine readable memory that at least a portion that can utilize the described timing data that obtains from the described input signal that receives drives the coding of at least one transmit path of described second port.
In preferred version of the present invention, further comprise in the described machine readable memory:
The coding that is used for described at least one port of link of bypass; And
With at least a portion in the described input signal that receives from described first port translation to described link at least one the 3rd port, and at least without initialization or reconfigure the coding of described the 3rd port.
In preferred version of the present invention, further comprise the coding that at least a portion in the described input signal that receives can be transmitted back to described at least second port from described first port in the described machine readable memory.
In preferred version of the present invention, further in the described machine readable memory, when at least a portion in the described input signal that receives being relayed in the described link one the 3rd port, be the coding that described second port produces an again timing signal corresponding with at least a portion in the described input signal that receives.
In preferred version of the present invention, further comprise in the described machine readable memory can be a FC-core bypass all of the port in the described link, and at least a portion in the described input signal that receives is transformed into the coding of at least one port of the 2nd FC-core in the link.
In preferred version of the present invention, further comprise in the described machine readable memory:
Be used to detect the coding of a speed of the described input signal that receives; And
Based on the speed of the described input signal that receives that detects, the word boundary in the described input signal that receives is carried out the coding of registration process.
On the other hand, the invention provides a kind of system that is used for seamless port bypass controller operation, comprising:
One first port of port bypass controller, it is used to receive an input signal;
At least one selector, it is used to select at least one second port, makes it and described first port link; And
Described at least one selector with at least a portion in the described input signal that receives from described first port translation to described at least second port, and without initialization or reconfigure described second port.
In preferred version of the present invention, this system also comprises a repeater, and it is relayed to described second port with at least a portion in the described input signal that receives, and without initialization or reconfigure described second port.
In preferred version of the present invention, this system also comprises a time clock again, it produces an again timing signal corresponding with at least a portion in the described input signal that receives, and it is transformed into described at least second port, and without initialization or reconfigure described second port.
In preferred version of the present invention, this system has further comprised at least one in CDR and the interpolater, and can obtain timing data from the described input signal that receives.
In preferred version of the present invention, at least one in described CDR and the interpolater utilized at least a portion of the timing data that obtains from the described input signal place that receives, drives at least one transmit path of described second port.
In preferred version of the present invention, this system further comprises:
A bypass selector, this bypass selector at least can the described link of bypass in a port; And
Described bypass selector at least a portion to the described input signal that receives of major general from described first port translation to described link at least one the 3rd port, and without initialization or reconfigure described the 3rd port.
In preferred version of the present invention, this system has further comprised a loopback selector, and it can be transmitted back to described at least second port at least a portion in the described input signal that receives from first port.
In preferred version of the present invention, this system further comprises a time clock again, when repeater is relayed at least a portion in the described input signal that receives one the 3rd port in the link, described time clock again can be simultaneously for described second port produces an again timing signal corresponding with at least a portion in the described input signal that receives, and without initialization or reconfigure second port and the 3rd port
In preferred version of the present invention, this system has further comprised a bypass selector, this bypass selector also can be first FC-core bypass all of the port in the link, and at least a portion in the described input signal that receives is transformed at least one port of one the 2nd FC-core in the link.
In preferred version of the present invention, this system has further comprised;
A speed detector, it can detect the speed of the described input signal that receives; And
Device adorned synchronously in a word, and it can be adjusted at the word boundary in the described input signal that receives based on the speed by the described input signal that receives that speed detector detected.
Below in conjunction with drawings and Examples, further specify advantage of the present invention, feature and novelty, understand the present invention is had more fully.
Description of drawings
Fig. 1 a is the block diagram of a legacy network environment, wherein shows the deployment scenarios of various communications and storage entity.
Fig. 1 b is the block diagram of a legacy network environment after the improvement, wherein shows the deployment scenarios of various communications and storage entity, and it still has some defectives of network environment shown in Fig. 1 a.
Fig. 1 c is the block diagram of a legacy network environment after the improvement, wherein shows the deployment scenarios of various communications and storage entity, and it still has some defectives of network environment shown in Fig. 1 a and Fig. 1 b.
Fig. 2 is the block diagram of a LAN (LAN) that typically is connected with storage area networks (SAN).
Fig. 3 is a block diagram that traditional fibre pipeline arbitration loop is arranged, it can be used for connecting a plurality of hard disks, can find these hard disks in the storage entity of Fig. 1 a, Fig. 1 b, Fig. 1 c and Fig. 2.
Fig. 4 a is the block diagram of a typical IBOD device, and according to a specific embodiment of the present invention, it is used in and realizes seamless pair of transfer process in the port bypass controller.
Fig. 4 b is ordinary magnetic disc heap (JBOD), intelligent disc heap (IBOD
TM), entiredisk heap (SBOD) and optical fiber disk packs (FBOD
TM) between the comparison schematic diagram, concrete an enforcement according to the present invention is asked, they are used in and realize seamless pair of transfer process in the port bypass controller.
Fig. 5 is the block diagram of time clock port translation of a typical FC-core repeater/again, and it can be used for the IBOD device among Fig. 4 a, for example carries out seamless two conversion in a port bypass controller.
Fig. 6 is the example block diagram of a FC-core repeater port conversion, it is used for the FC-core repeater of Fig. 5/again a transmitter side and a receiver side of time clock port translation, for example be used for IBOD device shown in Figure 4, in a port bypass controller, to carry out seamless two conversion.
Fig. 7 is an exemplary configurations block diagram of time clock port translation again, it can be used for Fig. 4 a in the relevant business of IBOD device, for example in a port bypass controller, carry out seamless two conversion.
Fig. 8 is the block diagram of the part of time clock port translation again shown in Fig. 7, and it can handle an independent FC-core, and the utilization of FC-core is relevant with the IBOD device of Fig. 4 a, for example, carries out seamless two conversion in a port bypass controller.
Fig. 9 is another time clock port translation exemplary configurations block diagram again, and its utilization is relevant with the IBOD device of Fig. 4 a, for example, can carry out seamless two conversion in a port bypass controller.
Figure 10 is the block diagram of the part of the port translation of time clock again structure shown in Figure 9, and it can handle an independent FC-core, and the utilization of FC-core is relevant with the IBOD device of Fig. 4 a, for example, carries out seamless two conversion in a port bypass controller.
Figure 11 is the application block diagram of a dual new time clock/repeater of typical case, and its utilization is with to carry out seamless two conversion in a port bypass controller relevant.
Figure 12 is the block diagram that typical 12 port PBC IBOD use, its utilization with in a port bypass controller, carry out seamless two change relevant.
Embodiment
For the seamless two conversions in a port bypass controller, one first port that present invention resides in a port bypass controller receives an input signal, and selects at least one second port to make it and described first port link.At least a portion in the described input signal that receives can be from described first port translation to described at least second port, and without initialization or reconfigure described second port.In this method, also at least a portion in the described input signal that receives can be relayed to described second port, and without initialization or reconfigure described second port.Can produce an again timing signal corresponding, and it is transformed into described at least second port with at least a portion in the described input signal that receives, and without initialization or reconfigure described second port.Also can from the described input signal that receives, obtain timing data.At least one transmit path in described second port can be driven by at least a portion in the timing data that is obtained from the described input signal that receives.Wherein have one or more ports can be by bypass, at least a portion in the described input signal that receives can be from first port translation at least one the 3rd port link, and without initialization or reconfigure the 3rd port.At least one of the described input signal that receives can be sent back to described at least second port from first port.Two conversions among the present invention refer to the repeater port conversion, time clock port translation again, the repeater port of perhaps carrying out simultaneously conversion and time clock port translation again.
The BROADCOM of California, USA (Botong) the active signal integrity that company developed is (active-SI
TM) and active circuit integrality (active-LI) technology, the reliability that connects for network, availability and easily maintainability (RAS) various improvement are provided.For example, Huo Yue signal integrity is (active-SI
TM) and active circuit integrality (active-LI) technology can be a bit error rate (BER) tester (BERT), an oscilloscope, and the equivalent function of a protocol analyzer merges in some or all of the port of a comprehensive communication device.Enliven-SI/LI can improve the reliability, availability of system and maintainability (RAS) easily from chip-scale, and can help to realize as system's improvement, system combination, system allocates and startup etc.Therefore, active-SI/LI can provide improved Time To Market, also can help discriminated union to be separated in the underproof system element or the entity in this field.All these conversions can reduce expense and reduce maintenance cost significantly.
For example, for storage system or array, active signal integrity (Acitive-SI) and active circuit integrality (Acitive-LI) technology can be used in each Fibre Channel (FC) port, to create new intelligent port bypass controller (PCB) classification, can be referred to as intelligent disc heap (IBOD) herein.Comprise intelligent conversion in the IBOD device, but communication is transparent to data.Therefore, can eliminate issuable any agreement interoperability problems.For example, each IBOD port can by common stand-by period as all again timing move, to finish 2-4 Fibre Channel word, perhaps (circulation pattern of the stand-by period of＜1=Fibre Channel word moves for example to be less than 1.Communication is transparent because the IBOD device is to data, so can change any traditional or other base plates with the redesign work of minimum, improve reliability, availability and maintainability (RAS) easily to utilize active signal integrity (Acitive-SI) and active circuit integrality (Acitive-LI) technology.
Though active-SI and active-LI can merge to example port bypass controller disclosed herein, the present invention is not limited to this.Can also need not enliven-SI and active-LI technology, and realize the method and system that in a port bypass controller, carries out seamless two conversions of the present invention.
Fig. 4 a is the block diagram of an exemplary IBOD device, and according to a specific embodiment of the present invention, it is used in and realizes seamless pair of transfer process in the port bypass controller.With reference to figure 4, can comprise a plurality of FC-cores in this IBOD device 400, comprise FC-core 0 (406), FC-core (408), FC-core 2 (404), controll block 438, one starts configuration block 440 and a bus interface block 442
In the FC-core 404,406,408 each all has the controll block of an association, and this controll block comprises a FC-core bypass block, a port bypass block, a local echoing piece and an EFIFO piece.Go up in this respect, the controll block of FC-core 2 (404) comprises FC-core bypass block 410, port bypass block 412, local echoing piece 414 and an EFIFO piece 416.The controll block of FC-core 0 (406) comprises FC-core bypass block 418, port bypass block 420, local echoing piece 422 and EFIFO piece 424.The controll block of FC-core 1 (408) comprises FC-core bypass block 428, port bypass block 430, local echoing piece 432 and EFIFO434.
IBOD device 402 also can comprise a bypass and auto by pass controll block 444, speed control piece 446, auto by pass controll block 448, time clock/repeater controll block 450, and loopback controll block 452 again.Bypass and auto by pass controll block 444, speed control piece 446 and again time clock/repeater controll block 450 can be connected in the FC-core 404,406,408 each.Bypass and auto by pass controll block 444 and auto by pass controll block 448 can be connected to each in the port Bypass Control piece 412,420,430.Loopback controll block 452 can be connected in each of FC-core 404,406, the 408 local echoing piece 414,422,432 in each respectively.
In the FC-core bypass block 410,418,428 related with FC-core 404,406,408 each can comprise a multiplexer or other suitable selectors, when multiplexer or selector were activated, it can corresponding FC-core of bypass.For example, when FC-core bypass block 410 was activated, FC-core bypass block 410 can be used to bypass FC-core 404.Similar ground, when FC-core bypass block 418 was activated, FC-core bypass block 418 can bypass FC-core 406.Finally, when FC-core bypass block 428 was activated, FC-core bypass block 428 can bypass FC-core 408.When a FC-core during by bypass, all of the port of this FC-core is also by bypass.
In each of related with FC-core 404,406,408 respectively port bypass block 412,420,430, can comprise suitable logic, circuit and/or coding, to finish the port bypass.
In related with FC-core 404,406, the 408 respectively local echoing piece 412,420,430 each can comprise suitable logic, circuit and/or coding, thereby the FC-core port of a correspondence can be placed in the local echoing.Go up in this respect, a special local echoing piece can inner be provided with a special FC-core port, and the transmission of this particular port (Tx) and acceptance (Rx) circuit are by interconnection.For example, local echoing piece 414 can inner be provided with the port 454 of FC-core 404, so its transmission (Tx) and acceptance (Rx) circuit are by interconnection.Loopback controll block 452 can comprise suitable logic, circuit and/or coding, to control the local echoing piece 414,422,432 in each of FC-core 404,406,408 respectively.For example, loopback controll block 452 can be with the relevant port 456 of a kind of local echoing pattern configurations and FC-core 406.With the local echoing pattern, the transmission of a special ports (Tx) circuit and acceptance (Rx) circuit can be by interconnections from corresponding FC-core.
Can comprise suitable logic and/or circuit in related with FC-core 404,406,408 respectively elasticity FIFO (EFIFO) piece 416,424,434 each, to introduce and to change the speed and/or the phase place of the data of handling by FC-core 404,406,408 reception and/or that send.
Bypass and auto by pass controll block 444 and auto by pass controll block 448 can comprise suitable logic, circuit and/or coding, with the bypass of the port at least of controlling a special FC-core.Correspondingly, one or more ports that bypass and auto by pass controll block 444 and/or the auto by pass controll block 448 that combines with a corresponding ports bypass block can special FC-cores of bypass.For example, port bypass and auto by pass controll block 444 and/or the auto by pass controll block 448 that combines with a port bypass block 420 can be configured at least one port of enabling or stop using, such as the port 456 of FC-core 406.
Speed control piece 446 can comprise suitable logic, circuit and/or coding, runs on a plurality of different data rates with control and adjusting FC-core 404,406,408.In addition, the speed control piece also can adapt to automatic speed negotiation.
Repeater/time clock piece 450 can comprise suitable logic, circuit and/or coding again, to control timing again and the relaying at the signal of each port of FC-core in IBOD device 402.
Start configuration block 440 can comprise suitable logic, circuit and/or coding, with initialization IBOD device 402.Suitable logic can include but not limited to be suitable for storing the register and/or the memory of start-up parameter and/or value.For example, start configuration block 440 can comprise a plurality of control storages
Controll block 438 can comprise suitable logic, circuit and/or coding, with the operation of configuration and control IBOD device 402.Described suitable logic can comprise the one or more registers and/or the memory of the various operations that are suitable for disposing IBOD device 402.Controll block 438 can also comprise a plurality of status registers, in order to determine the running status of an IBOD device, can read this status register.
Bus interface block 442 can be the interface bus of serial or parallel, and is suitable for providing communication between IBOD 402 and master processor or CPU.In a model's of the present invention specific embodiment, bus interface block 442 can be a standardized I
2The C bus.
Fig. 4 b is ordinary magnetic disc heap (JBOD), intelligent disc heap (IBOD
TM), entiredisk heap (SBOD) and optical fiber disk packs (FBOD
TM) between the comparison schematic diagram, these technology can be applied to seamless pair of transfer process in a port bypass controller.With reference to figure 4, the longitudinal axis in its left side refers to diagnosis capability, and the longitudinal axis on right side refers to complexity, and transverse axis refers to relative cost.Curve be JBOD bottom, that higher is IBOD, that higher again is SBOD, that the highest is FBOD.Serializer/de-serializers (SerDes or the SERDES) technology of a kind of technology that drives and enable IBOD active-SI that has been advanced merging and active-LI.Though FBOD and SBOD have the highest relative cost and maximum complexity, and the mixing of IBOD and FBOD can be provided, so that improved calibration and the performance with the equal cost of SBOD to be provided.
Fig. 5 is the block diagram of time clock port translation of a typical FC-core repeater/again, and it can be used for the IBOD device among Fig. 4 a, for example carries out seamless two conversion in a port bypass controller.With reference to figure 5, FC-core repeater/the time clock port translation can comprise an active signal integrity piece 518 again, interpolater 520, auto-speed detects piece 526, word is (WS) piece 532 synchronously, active circuit whole blocks 518530,8B/10B decoder block 528,8B/10B coder block 534 and mode generator 536.
Also comprised a repeater function piece 514 and one time clock functional block 516 again among Fig. 5.Repeater function piece 514 can comprise suitable logic and/or circuit, carries out repeater function to wait each FC-core such as FC-core 512.Repeater function piece 516 shows the typical logic that can be used for again the timing function.
FC-core repeater/the time clock port translation also can comprise a plurality of clock and data recoveries (CDR) circuit block again, such as CDR524 and 522.Can arrange these CDR in couples, and make first CDR handle reception (Rx) side of particular port, second CDR handles transmission (Tx) side of particular port.For example, CDR522 is configured to one and receives CDR, and CDR524 is configured to one and sends CDR.A combination that receives a CDR and a transmission CDR can be called a port.Described FC-core comprises 4 ports.Yet this invention is not restricted in this point, and each FC-core can comprise greater or less than 4 ports.Each port is suitable for handling an independent FC hard disk.A plurality of FC ports can link together, and merge in the independent chip or integrated circuit.For example, can will there be 3 FC-cores of 4 ports to link together respectively, and merge in the independent chip that to handle 12 ports.In this, in theory, 12 ports can be handled maximum 12 hard disks.Though the interpolater piece 520 shown in the figure separates with CDR piece 522, interpolater piece 520 can be the part of CDR piece 522.From view of function, CDR piece 522 can be regarded the simulation part of CDR as, and interpolater piece 520 can be regarded the numerical portion of CDR as.
The 518 usefulness initialization of signal integrity piece are also carried out measuring signal integrality.Similarly, Huo Yue circuit piece 530 is used to carry out the circuit integrity test.At application number be _ _ _ _ United States Patent (USP) of (proxy number 15366US02) in, the function and the operation of active signal integrity and active circuit integrality are disclosed.This sentence as a reference.
8B/10B decoder block 528 can be that a standardized 8B/10B belongs to from decoder, and this decoder can be used for 10 bit data are decoded as 8 bit data.8B/10B coder block 528 can be that a standardized 8B/10B belongs to from encoder, and this encoder can be used for 8 bit data are encoded to 10 bit data.Mode generator 536 is suitable for producing control word or bit pattern or can be used for the order of bit error rate test.Go up in this respect, one or more ports can be placed and by sending for example control word with the loopback method, ordered set and/or from the bit pattern of mode generator 536.Auto-speed detects piece 526 and is suitable for detecting data speed and suitable clock signal is set, and for example sends and receive clock, so that correct time to be provided.
Fig. 6 is the example block diagram of a FC-core repeater port conversion, it is used for the FC-core repeater of Fig. 5/again a transmission equipment side and a receiver side of time clock port translation, for example be used for IBOD device shown in Figure 4, in a port bypass controller, to carry out seamless two conversion.Fig. 6 shows the transmitter side of one first port 602 of time clock port translation of FC-core repeater among Fig. 5/again and the receiver side of one second contiguous port 622.Correspondingly, Fig. 6 can be used for being set forth in the operation of the repeater function piece 514 of setting forth among Fig. 5.
With reference to figure 6, wherein shown a receiving unit 604 of port 602.For the sake of simplicity, be not presented at the CDR522 and the interpolater 520 of setting forth among Fig. 5.Even so, receiver side can comprise an active signal integrity (SI) piece 634, a selector 606, bypass selector 608, auto-speed detects piece 612, word synchronizer piece 614, active circuit integrality (LI) piece 632,8B/10B decoder 630, selector 618 and selector 620.
In the selector 606,608,618 and 620 each can comprise suitable logic and/or circuit, can be incorporated into one or more signals there to enable and/or to stop using.Correspondingly, when receiving a signal at port 604, CDR (among Fig. 6 not show) and interpolater can recovered clock, and this clock recovered can be used for demultiplex signal.The signal that multichannel is decomposed can be passed to active signal integrity piece 634 handling, and/or it is delivered to selector 606.The output signal that is delivered to selector 606 can be transmit port Tx
(n+1)624 provide selection of time.
Output signal from selector or MUX 606 can be passed in multiplexer or the selector 608, and/or auto-speed detects the data rate that piece can be measured the signal of multichannel decomposition.In case measured the data rate of signal, the timing information that causes thus can be used to be aligned on the word boundary in the signal that receives that multichannel decomposes by word synchronization blocks (WS) 614.About port translation, can not need the circuit integrality piece 632 and the active signal integrity piece 634 that enliven.
The consequential signal that obtains from word synchronization blocks (WS) 614 can perhaps be handled by active circuit integrality piece 632 by 630 decodings of 8B/10B decoder.Selector or multiplexer 620 are suitable for making one's options between the multichannel decomposition received signal of the output of word synchronization blocks (WS) 614 and non-word synchronous version.Selector or multiplexer 618 are suitable for making one's options between the output of 8B/10B decoder and selector 620.
Generally speaking, with Repeater-mode, when the received signal of previous port from link on the front port can be relayed on the next port in the link.The CDR of current receiving port can recover clock signal from the signal from previous port the link.This recovered clock signal can be passed to the next port in the link.It can be used for driving the transmitter side of subsequent port in this link.Go up in this respect, can be passed to bypass selector or multiplexer from the output signal of selector or MUX 606, by the selection of bypass selector 608, this signal can be relayed to port 632.With bypass mode, can bypass ports 602 and be delivered to port 624 and/or Tx (n+2) from the signal 610 of port Rx (n-1), bypass selector or multiplexer 608 also can be considered to a repeater selector or multiplexer.Port 550 by the situation of bypass under, can by signal 610 from one the preceding port obtain regularly.For example, signal 610 can obtain from another FC-core the link.
At receiver side, signal 640 can be directly delivered to selector or multiplexer 632, and signal 640 can be encoded by 8B/10B coder block 626 8B/10B.For example, signal 640 can be a timing signal again.Signal behind the 8B/10B coding can be delivered to selector 632.Signal after selector or multiplexer 632 can be selected to encode, or select to be passed to the signal 640 of time clock selector 626 of heavy transmitter/again.Heavy transmitter/time clock selector 626 can be selected the output of selector 632 again, makes it to be passed to transmit port 624.The test pattern generator can be used for test, and produces test coding and/or model, such as Fibre Channel coding, frame and/or ordered set.Correspondingly, when using, need not to reconfigure or this port of initialization, or use expensive external testing machine, just can test any port at an easy rate with port bypass or conversion.
Fig. 7 is an exemplary configurations block diagram of time clock port translation again, it can be used for Fig. 4 a in the relevant business of IBOD device, for example in a port bypass controller, carry out seamless two conversion.With reference to figure 7, wherein show FC-core 702,704,706 and their pieces of time clock again 708,710,712 separately, control circuit piece 714, start configuration block 716 and a bus interface block 718 are such as I
2The C bus interface.
Fig. 8 is the block diagram of the part of time clock port translation again shown in Fig. 7, and it can handle an independent FC-core, and the utilization of FC-core is relevant with the IBOD device of Fig. 4 a, for example, carries out seamless two conversion in a port bypass controller.With reference to figure 8, wherein show FC-core 802, EFIFO806,808,810,812, selector or multiplexer 822,824,826,828 are enabled in loopback, selector or multiplexer 804 are enabled in bypass selector 814,816,818,820 and the bypass of FC-core, and Fig. 8 further comprises loop-back path 830,832,834 and 836.
The bypass of FC-core enables that selector or multiplexer 804 can be used for enabling or the port of inactive FC-core.For example, be activated if selector 804 is enabled in the bypass of FC-core, then port 0, port one, and port 2, port 3, any one in the port 4 can be enlivened.Yet, if enabling selector 804, the bypass of FC-core is deactivated, port 0, and port one, port 2, port 3, any one in the port 4 do not enlivened.In fact, after the bypass of FC-core was enabled selector 804 and is deactivated, FC-core 802 also was deactivated.Even so, enable under the situation that selector 804 is activated in the bypass of FC-core, any one of the port of FC-core 802 or a plurality of can be by bypass.At this moment, selector 814 is enabled in bypass can be used for bypass ports 0, and bypass is enabled selector 816 and can be used to bypass ports 1.Similarly, selector 818 is enabled in bypass can be used for bypass ports 2, and selector 820 is enabled in bypass can be used for bypass ports 3.
Loopback is enabled selector 822 and can be used for by path 830 port 0 being placed playback, and loopback is enabled selector 824 and can be used for by path 832 port one being placed playback.Similarly, loopback is enabled selector 826 and can be used for by path 834 port 2 being placed playback, and loopback is enabled selector 828 and can be used for by path 836 port 3 being placed playback.The signal that receives from port 3 can and pass through path 836 by loopback by EFIFO812.Similarly, the signal that receives from port one can and pass through path 832 by loopback by EFIFO808.
Fig. 9 is another time clock port translation exemplary configurations block diagram again, and its utilization is relevant with the IBOD device of Fig. 4 a, for example, can carry out seamless two conversion in a port bypass controller.With reference to figure 9, wherein show FC-core 902,904,906 and their pieces of time clock again 908,910,912 separately, control circuit piece 914, start configuration block 916 and a bus interface block 918 are such as the IC bus interface
Figure 10 is the block diagram of the part of the port translation of time clock again structure shown in Figure 9, and it can handle an independent FC-core, and the utilization of FC-core is relevant with the IBOD device of Fig. 4 a, for example, carries out seamless two conversion in a port bypass controller.With reference to Figure 10, wherein show FC-core 1002, selector or multiplexer 1022,1024,1026,1028 are enabled in loopback, selector or multiplexer 1004 are enabled in bypass selector 1014,1016,1018,1020 and the bypass of FC-core, in Figure 10, the rear portion or the output of selector enabled in EFIFO 1006,1008,1010,1012 position loopbacks, this is opposite with Fig. 8, in Fig. 8, EFIFO 806,808,810,812 position bypass selectors 814,816,818,820 before or its input.
Selector is enabled in the bypass of FC-core or multiplexer 1004 can be used for enabling or stopping using at the port of FC-core.For example,, the bypass of FC-core is activated if enabling selector 1004, port 0, and port one, port 2, port 3, any one in the port 4 can be enlivened.Yet, if enabling selector 1004, the bypass of FC-core has been deactivated, port 0, and port one, port 2, port 3, any one in the port 4 do not enlivened.In fact, enable selector 1004 when the bypass of FC-core and be deactivated, FC-core 1002 also is deactivated.Even so, enable under the situation that selector 1004 is activated in the bypass of FC-core, any one of the port of FC-core 802 or a plurality of can be by bypass.Go up in this respect, selector 1014 is enabled in bypass can be used for bypass ports 0, and bypass is enabled selector 1016 and can be used to bypass ports 1.Similarly, selector 1018 is enabled in bypass can be used for bypass ports 2, and selector 1020 is enabled in bypass can be used for bypass ports 3.
Loopback is enabled selector 1022 and can be used for by path 1030 port 0 being placed playback, and loopback is enabled selector 1024 and can be used for by path 1032 port one being placed playback.Similarly, loopback is enabled selector 1026 and can be used for by path 103.4 port 2 being placed playback, and loopback is enabled selector 1028 and can be used for by path 1036 port 3 being placed playback.For example, the signal that receives from port 3 can and pass through path 1036 by loopback by EFIFO1012.Similarly, the signal that receives from port one can and pass through path 1032 by loopback by EFIFO1008.
When the bypass of FC-core was enabled selector 1004 and is activated, timing signal 1040 can be connected to any one port of FC-core 1002 again.For example, enable selector 1004 and bypass in the bypass of FC-core and enable under the situation that selector 1014 is activated, the timing signal can be connected to the EFIFO1008 of port 2 again.Yet, in this case,, can offer port from the clock that is resumed of port 2 if bypass selector 1016 is deactivated.
Figure 11 is the application block diagram of a dual new time clock/repeater of typical case, and its utilization is with to carry out seamless two conversion in a port bypass controller relevant.With reference to Figure 11, it has provided 1102, one dual new time clock/repeater conversion blocks 1104 of a loop card/controller block and a cable/optical interface piece 1106.Can comprise port bypass controller piece 1108,1114 in dual new time clock/repeater conversion block 1104, the time clock piece 1110,1112 of repeater/again, active-S1 and active-L1 piece 1116 and bus interface block 1118.Loop card/controller block 1102 can be a CPU and other control device, and it can handle a plurality of dual new time clocks/repeater conversion block, and is connected with a backplane bus.Cable/optical interface 1106 can comprise light and/or electrical interface, and these interfaces can be connected with a transmission medium.
In dual new time clock/repeater configurations of Figure 11, port bypass controller 1108 and repeater/time clock 1110 can be handled transmitter side again, and this transmitter side is from loop card/controller 1102 to cable/optical interface 1106.Similarly, port bypass controller 1114 and repeater/time clock 1112 can be handled receiver side again, this receiver side from cable/optical interface 1106 to loop card/controller 1102.The PBC1108 of transmitter side can with receiver side repeater/time clock piece 1112 is connected again, it helps repeater and the running of time clock again.Aspect this, can regain clock signal from the port of receiver side, and this signal can drive the port of transmitter side.Under a kind of similar situation, the PBC114 of receiver side can with transmitter side repeater/time clock piece 1110 is connected again, it helps repeater and the running of time clock again.At this moment, can regain clock signal from the port of receiver side, and this signal can drive the port of transmitter side.
Figure 12 is the block diagram that typical 12 port PBC IBOD use, its utilization with in a port bypass controller, carry out seamless two change relevant.With reference to Figure 12, it has provided 1202,1204 and FC IBOD interface block 1206 of FC-core.In the FC- core 1202,1204 each has all comprised 12 ports, and promptly port 0 to 11.In each FC- core 1202,1204, there is a port to be used as an interface port, these ports couple together FC- core 1202,1204 and FC IBOD interface block 1206.At this moment, because there is a port to be used as interface port, so each FC- core 1202,1204 maximum accessible hard disk number is 11.
Figure 12 has also illustrated the chrysanthemum on-link mode (OLM) of 22 hard disks, and this daisy chain is utilized two FC-cores.At this moment, are first ports at 1202 li ports that link with PBC0 of FC-core, be last port at the PBC10 of 1204 li of FC-cores.Be connected with PBC0 by interface PBC at the PBC10 of 1202 li of FC-cores, at FC-core 1202 called after PBC11, in FC-core 1204 also called after PBC11 1204 li of FC-cores.Be in operation, can send to the PBC11 of FC-core 1202 from the data of FC IBOD interface 1206, pass port PBC0 and the PBC10 by FC-core 1202, turn back to the PBC11 of FC-core 1202 again, enter the PBC11 of FC-core 1204 then by the PBC11 of FC-core 1202, pass port PBC10, by the PBC0 of FC-core 1204, turn back to the PBC11 of FC-core 1204 again, enter FC IBOD interface 1206 then.
The various specific embodiments according to the present invention, can use the repeater of separation and again time clock unify work so that two transfer processes to be provided, thereby the obvious stand-by period that must improve the FC-core port.Among the present invention, thereby time clock can optimisedly have maximum flexibility again, thereby repeater also can optimisedly have the less stand-by period.For the stand-by period between the port that makes the FC-core reaches minimum, can provide automatic multiport bypass.That this flexible structure that the FC-core provides helps multiple functional operation and deposit, for example, in port bypass controller, realize the port bypass, the multiport bypass, loopback, and to the continuous monitoring of input signal.
Therefore, the present invention can be realized with combining of software by hardware, software or hardware.The present invention can be at least one computer system implements with a concentrated form, perhaps implement with discrete form, but this discrete form is meant in the computer system that different element cross-distribution connects in several.Any department of computer science that is suitable for carrying out said method other devices of unifying all are available.Typical hardware combines with software, is a general-purpose computing system, and it has a computer program, when loading and during computer program, it can control computer system to implement said method.
The present invention also can be embedded in the computer program, and it has comprised all features that can implement the method, and when being written into a computer system, also can implement these methods.Computer program herein can be the expression of any language, coding or symbol, and it can cause that a system with a kind of information processing capability carries out a kind of specific function.
Though the present invention is by being described with reference to some concrete aspects and embodiment, what it will be appreciated by those skilled in the art that is to carry out various modifications and equivalence replacement without departing from the scope of the invention.In addition, according to instruction of the present invention, can carry out various modifications to adapt to specific situation or material without departing from the scope of the invention.Therefore, scope of the present invention should not be limited to above-mentioned disclosed specific embodiment, and should comprise all interior embodiments of claims institute's limited range of the present invention.
Claims (7)
1, a kind of method that is used for seamless port bypass controller operation, it is characterized in that, described port bypass controller comprises at least two groups, every group comprises two link ports at least, and the bypass selector that is provided with respectively of corresponding each link port, each link port comprises first port and second port, said method comprising the steps of:
First port at a port bypass controller receives an input signal;
Select at least one second port, make it and described first port link; And
With at least a portion in the described input signal that receives from described first port translation to described at least second port, and without initialization or reconfigure described second port;
Select the bypass of FC-core to enable selector, thereby the all-links port in the group is somebody's turn to do in bypass, and at least a portion in the described input signal that receives is transformed into described at least second port with the all-links port in the group of stopping using.
2, method according to claim 1 is characterized in that, also comprise at least a portion in the described input signal that receives is relayed to described second port, and without initialization or reconfigure the step of described second port.
3, method according to claim 1, it is characterized in that, also comprise producing an again timing signal corresponding, and it is transformed into described at least second port with at least a portion in the described input signal that receives, and without initialization or reconfigure the step of described second port.
4, method according to claim 1 is characterized in that, also comprises the step that obtains timing data from the described input signal that receives.
5, a kind of system that is used for seamless port bypass controller operation is characterized in that, comprising:
One first port of port bypass controller, it is used to receive an input signal, wherein, described port bypass controller comprises at least two groups, every group comprises at least two link ports, corresponding each link port is respectively arranged with the bypass selector, and each link port comprises first port and second port;
At least one selector, it is used to select at least one second port, makes it and described first port link; And
Described at least one selector with at least a portion in the described input signal that receives from described first port translation to described at least second port, and without initialization or reconfigure described second port;
Correspondence is provided with the bypass of FC-core respectively for every group and enables selector, is used for all-links port of its affiliated group of bypass.
6, system according to claim 5 is characterized in that, also comprises a repeater, and it is relayed to described second port with at least a portion in the described input signal that receives, and without initialization or reconfigure described second port.
7, system according to claim 5, it is characterized in that, also comprise a time clock again, it produces an again timing signal corresponding with at least a portion in the described input signal that receives, and it is transformed into described at least second port, and without initialization or reconfigure described second port.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US52920003P | 2003-12-12 | 2003-12-12 | |
| US60/529,145 | 2003-12-12 | ||
| US60/529,143 | 2003-12-12 | ||
| US60/529,200 | 2003-12-12 | ||
| US60/529,421 | 2003-12-12 | ||
| US10/779,234 | 2004-02-13 |
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| Publication Number | Publication Date |
|---|---|
| CN1750500A CN1750500A (en) | 2006-03-22 |
| CN100531107C true CN100531107C (en) | 2009-08-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004101040680A Expired - Fee Related CN100531107C (en) | 2003-12-12 | 2004-12-13 | Method and system for seamless dual switching in a port bypass controller |
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| CN (1) | CN100531107C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8891561B2 (en) * | 2012-07-16 | 2014-11-18 | Broadcom Corporation | 50 Gb/s ethernet using serializer/deserializer lanes |
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