CN100524780C - TFT LCD array substrate structure and method for forming non-comformal insulation film and use - Google Patents
TFT LCD array substrate structure and method for forming non-comformal insulation film and use Download PDFInfo
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- CN100524780C CN100524780C CNB2006101498857A CN200610149885A CN100524780C CN 100524780 C CN100524780 C CN 100524780C CN B2006101498857 A CNB2006101498857 A CN B2006101498857A CN 200610149885 A CN200610149885 A CN 200610149885A CN 100524780 C CN100524780 C CN 100524780C
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Abstract
This invention discloses a TFT LCD array base plate structure including: a base plate, grid lines, a grid electrode, a grid insulation film, an active layer isolated island, a data line, a source, a drain, a transparent conduction film and a passivation insulation film, in which, the grid insulation film is a non-conformal structure or the passivation insulation film is a non-conformal structure or both of them are the non-conformal structure. This invention discloses a forming method for two non-conformal structures and the TFT LCD array base plate structure.
Description
Technical field
The present invention relates to a kind of TFT LCD array base-plate structure manufacture method, relate in particular to a kind of non-comformal insulation film and form methods and applications.
Background technology
Display device shows in order to realize high definition and big capacity, generally uses the switching device of active matrix (ActiveMatrix) to control each pixel.Thin-film transistor is as single control element, by the conducting between gate electrode signal controlling source electrode and the drain electrode.Drain electrode is connected with the transparent pixels electrode, and the data-signal of source electrode can be transported to single pixel.In liquid crystal display device, pixel voltage is regulated the distortion of liquid crystal molecule or is turned to, and causes the variation of light transmission rate.By controlling the transmitance of each pixel, realize that image shows.The tft characteristics of each pixel control switch directly influences the picture display quality.
The semiconductor device structure of thin-film transistor (TFT) and integrated circuit is similar, and each layer pattern covers on another layer pattern at the accurate cloth of certain position.Each layer pattern is made up of difference or identical materials, and as metal, dielectric etc., its thickness is generally from extremely several microns of tens nanometers.Owing to also have a new layer pattern to form on each layer pattern, be necessary to realize the flattening surface of each layer pattern structure, to reduce precipitous step to forming the harm of a new layer pattern.Especially deposit metallic material on the dielectric of semiconductor structure forms the step of line or electrode.Metal level owing to the non-conformal deposit characteristic of sputtering technology itself, is greater than the metal thickness of steep sidewalls normally by the sputtering method preparation at the metal thickness of ledge surface.Cause the metal cross section at step knuckle place to diminish, its current density increases greatly, and plain conductor takes place aging easily.Because the incomplete covering of film step can cause brink the disconnection of metal connecting line to occur.
The making that forms the process of each layer pattern and integrated circuit at Thin Film Transistor-LCD (TFT LCD) is similar, at first forms thin film at substrate surface; Secondly form the pattern of one deck light sensitive material identical with final pattern at film surface; At last the film forming pattern of the design transfer of light sensitive material.Film forming method has physical vapour deposition (PVD) and chemical vapour deposition (CVD), and metallic film is prepared by physical vapour deposition (PVD) such as magnetron sputtering usually, and insulation film and semiconductive thin film are prepared by chemical vapour deposition (CVD) usually.The light sensitive material pattern forms by photoetching method.Thinfilm pattern be formed with liquid corrosion and two kinds of methods of gas attack.Owing to be difficult to find the etchant gas that forms volatile accessory substance with metal, the corrosion of metallic film is generally finished by etching liquid.For certain thin-film material, liquid corrosion and gas attack can form foregoing steep sidewalls and perpendicular steps under specific process conditions.Slow such as acid etching solution for the etch ratio metallic aluminium of metal molybdenum, under the pattern of light sensitive material, be not easy to form down recessed form of metal, tendency forms vertical precipitous pattern more.Chemical vapour deposition (CVD) is a kind of film formation method of conformal, and the film that it deposited has and the identical pattern of following one deck.When forming one deck insulation film on metal pattern when, this insulation film also has the precipitous step shape of same vertical.If continue on insulation film by the very thin conductive film of magnetron sputtering deposition one deck, because the non-conformal nature of sputter and the perpendicular steps of insulation film at the more difficult depositing electrically conductive film of step sidewall, the broken string of conductive film take place easily.As mentioned above, metal on insulation film pattern broken string is because the conformal nature of chemical vapour deposition (CVD) causes, the slit of filling a vacancy of the chemical vapour deposition (CVD) in its essence and the integrated circuit (IC)-components making is the same.United States Patent (USP) 6,794,299 have illustrated that the total inherence of various chemical gaseous phase depositing process is with feature.Because the conformal nature of chemical vapour deposition (CVD) at the insulation film of semiconductor device surface deposit, tends to form perpendicular steps, causes subsequent technique to form unfavorable film shape.
Shown in Figure 1 is the cross-sectional view of a thin-film transistor.The array base palte of this kind back of the body raceway groove corrosion bottom grating structure mainly is made up of film transistor device, transparent pixels electrode 10, grid line 1 and data wire 5.Film transistor device is made up of gate electrode 2, gate insulator 4, semiconductor active layer 3 and source, drain electrode 6,7.The drain electrode 7 of film transistor device is connected with pixel electrode 10 by the via hole 9 of passivating insulation membrane.The data wire of thin-film transistor and source, drain electrode generally are made up of metal molybdenum.Gate insulator 4 shown in Figure 1 is silicon nitrides of 1000 to 8000 dusts, and drain electrode 7 is metal molybdenum of 2000 dust to 4000 dusts, and passivation protection film 3 is silicon nitrides of 1000 to 4000 dusts, and pixel electrode 10 is transparent indium tin oxide films of 100 to 700 dusts.Make flow process according to aforesaid Thinfilm pattern, on gate electrode 2, form one deck grid insulating film 4 and semiconductor active layer 3, on grid electrode insulating film 4, form the drain electrode 7 of thin-film transistor.As previously mentioned, the material of formation thin-film transistor drain electrode generally is a metal molybdenum.Use the mixed solution corroding metal molybdenum of nitric acid, phosphoric acid and acetic acid to form the thin-film transistor drain electrode, because the low corrosion rate of metal molybdenum and more stable chemical property cause the thin-film transistor drain electrode to form the abrupt slope step shape.Use plasma reinforced chemical vapour deposition method deposit one deck insulation film on the thin-film transistor drain electrode, form passivation protection film 8 according to aforesaid design producing flow process.Because the conformality of chemical vapour deposition (CVD), the passivation protection film also forms abrupt slope step shape as shown in Figure 2.The transparent pixels electrode generally is that the sputter indium tin oxide films is made, and the ion sputtering plated film is general difficult at the side of vertical substrate deposition film, therefore forms broken string pixel electrode 10 (the pixel electrode broken string part 11 shown in the figure two) as shown in Figure 2.Pixel electrode is made up of transparent material, can not be detected after array base palte completes.This type of not visible defective causes the inefficacy of film transistor device and the bad point of liquid crystal display device.
Summary of the invention
In order to overcome the defective in the above-mentioned technology, the invention provides TFT LCD array base-plate structure and non-comformal insulation film and form methods and applications.An object of the present invention is to provide a kind of film transistor device structure and a kind of process of improving film morphology, thereby overcome the shortcoming of aforementioned conventional chemical gaseous phase depositing process.With respect to the perpendicular steps shape of chemical vapour deposition (CVD) conformal, process provided by the invention forms the mild step shape of the gradient.Especially, an object of the present invention is to improve the surface topography of the insulation film above the metal electrode, make the source-drain electrode or the transparent conductive film that are deposited on the insulation film form smooth structure continuously.Basic goal of the present invention is to eliminate the not visible defective of film transistor device that source-drain electrode and pixel electrode broken string cause, reduces LCD and detects the bad point that occurs, and improves rate and the good product ratio of manufacturing a finished product.
To achieve these goals, the invention provides a kind of TFT LCD array base-plate structure, comprise: substrate, grid line, gate electrode, grid insulating film, active layer isolated island, data wire, source electrode, drain electrode and transparent conductive film, wherein said grid insulating film are non-conformal structure.
In the such scheme, described structure also comprises passivating insulation membrane, and passivating insulation membrane is non-conformal structure, is formed on described source electrode, drain electrode and the part of grid pole insulation film.
To achieve these goals, the present invention provides another kind of TFT LCD array base-plate structure simultaneously, comprise: substrate, grid line, gate electrode, grid insulating film, active layer isolated island, data wire, source electrode, drain electrode, passivating insulation membrane and transparent conductive film, wherein said passivating insulation membrane are non-conformal structure.
To achieve these goals, the present invention provides the formation method of the insulation film of first kind of non-conformal simultaneously, comprising:
Step 1 provides a substrate;
The ratio of the speed of film etching and thin film deposition is between 0.01 to 0.1 in the described step 2.
In the formation method of the insulation film of above-mentioned first kind of non-conformal, when feeding reacting gas and inert gas in the described step 2 silane flow rate between 400 to 3000sccm, between the ammonia flow 1000 to 10000sccm, nitrogen flow between 5000 to 30000sccm and argon flow amount between 1000 to 10000sccm; Reaction chamber vacuum degree is between 1 millitorr to 100 millitorr; Plasma power 0.07 to 0.7watt/cm
2Between.When described step 2 feeds reacting gas and inert gas silane flow rate between 400 to 3000sccm, between the ammonia flow 1000 to 10000sccm, nitrogen flow between 5000 to 30000sccm and helium gas flow between 1000 to 10000sccm; Reaction chamber vacuum degree is between 1 millitorr to 100 millitorr; Plasma power 0.07 to 0.7watt/cm
2Between.
To achieve these goals, the present invention also provides a kind of insulation film that utilizes aforementioned formation method to form non-conformal to be used to form the grid insulating film and/or the passivating insulation membrane of TFT LCD array base-plate structure TFT device simultaneously.
To achieve these goals, the present invention provides the formation method of the insulation film of second kind of non-conformal simultaneously, comprising:
Step 1 provides a substrate;
In the formation method of the insulation film of above-mentioned second kind of non-conformal, when feeding reacting gas in described step 2 and the step 4 silane flow rate between 400 to 5000sccm, between the ammonia flow 1000 to 10000sccm, nitrogen flow is between 5000 to 30000sccm, the vacuum degree of reaction chamber between 500 millitorr to 3000 millitorrs, plasma power 0.07 to 0.7watt/cm
2Between.The ground floor insulation film that described step 2 forms, thickness is between 1000 to 10000 dusts.The second layer insulation film thickness that forms in the described step 4 is between 1000 to 10000 dusts.Feeding inert gas in the described step 3 is the mixed gas of helium, argon gas or helium and hydrogen.During described step 3 intermediate ion bombardment etching, inert gas flow between 1000 to 20000sccm, the vacuum degree of reaction chamber below 100 millitorrs, plasma power 0.07 to 0.7watt/cm
2Between.Described step 2 to step 4 can repeat repeatedly, and promptly multistep plated film and multistep etching repeatedly repeat plated film and etching.
To achieve these goals, the present invention also provides a kind of insulation film that utilizes aforementioned formation method to form non-conformal to be used to form the grid insulating film and/or the passivating insulation membrane of TFT LCD array base-plate structure TFT device simultaneously.
With respect to prior art, the present invention is on the grid line and gate electrode of array base palte, use plasma reinforced chemical vapour deposition to form gate insulator, form the mild step of non-conformal by process of the present invention, have on the gate insulator that improves step shape, forming semiconductor active layer by plasma reinforced chemical vapour deposition.The isolated island of photoetching formation semiconductor active layer has the step of mild transition, helps forming continuous source-drain electrode thereon.The deposition process of gate insulator provided by the invention and semiconductor active layer helps loosening the dependence for the gate electrode step shape, can reduce the development cost and the use cost of gate electrode etching liquid.
The present invention forms the insulation film with slick and sly step on drain electrode; Continuous transparent conductive film on insulation film.The thickness of drain electrode step corner insulation film is less than the thickness of flat surfaces insulation film, therefore formed a kind of film transistor device with continuous transparent conductive film, reduce the occurrence probability of pixel electrode broken string, reduced not visible defective and bad point of display.
Below in conjunction with the drawings and specific embodiments the present invention is further illustrated in more detail.
Description of drawings
Fig. 1 is the array base-plate structure cross-sectional view that not visible defective takes place in the prior art;
Fig. 2 is the caused film broken string of a membrane deposition method schematic diagram in the prior art;
Fig. 3 is the schematic diagram that deposition of the present invention and etching form non-comformal insulation film simultaneously;
Fig. 4 a is the schematic diagram that first step plasma-reinforced chemical sedimentation of the present invention (PECVD) forms conformal (Conformal) insulation film;
Fig. 4 b is the schematic diagram of insulation film pattern behind the ise of the present invention;
Fig. 4 c is the schematic diagram that PECVD of the present invention forms second layer insulation film or semiconductive thin film;
Fig. 4 d is the schematic diagram that is formed the continuous conduction film by process of the present invention;
Fig. 5 forms cross-sectional view behind the pixel electrode by manufacturing array board structure of the present invention;
Fig. 6 forms cross-sectional view behind the metal gate electrode by manufacturing array board structure of the present invention;
Fig. 7 a forms cross-sectional view behind the gate insulator by manufacturing array board structure of the present invention;
Fig. 7 b forms cross-sectional view behind the smooth step gate insulator by manufacturing array board structure ise of the present invention;
Fig. 7 c forms cross-sectional view behind the active layer silicon island by manufacturing array board structure of the present invention;
Fig. 8 forms cross-sectional view behind source-drain electrode and the conducting channel by manufacturing array board structure of the present invention;
Fig. 9 a forms cross-sectional view behind the passivation protection film by manufacturing array board structure of the present invention;
Fig. 9 b forms cross-sectional view behind the smooth step passivation protection film by manufacturing array board structure of the present invention;
Fig. 9 c forms cross-sectional view behind the passivation protection film via hole by manufacturing array board structure of the present invention.
Mark among the figure: 1, grid line; 2, gate electrode; 3, semiconductor active layer; 4, gate insulator; 5, data wire; 6, source electrode; 7, drain electrode; 8, passivating insulation membrane; 9, passivating insulation membrane via hole; 10, pixel electrode; 11, pixel electrode broken string part; 12, substrate; 13, conductive film; 14, insulation film; 14a, ground floor insulation film; 14b, second layer insulation film; 15, second layer conductive film.
Embodiment
The semiconductor structure that is used in display mainly is a thin-film transistor, and its effect is to provide essential operating voltage to each pixel, realizes that image shows.Amorphous silicon is the main material that constitutes thin-film transistor, the polysilicon that also has exploitation and volume production to use now.Silicon nitride then is a kind of main dielectric, is used in film transistor device.The making of thin-film transistor depends on and the similar a series of technology of semiconductor integrated circuit.This is included in the manufacturing order that the cell process that comes into force on the whole base plate surface is formed, and by suitable photolithographic mask layer, transforms the pattern and the shape of semiconductor and dielectric thereof partly in the mode of appointment.The film transistor device that following processing step generally is used on the glass substrate is made.At first forming thin film on glass substrate, can be metal material or dielectric, also can be the metal oxide of electrically conducting transparent.Coating one deck photoresist film on film, by the mask exposure, each mask is the structure of film transistor device one deck planar design then.The photoresist film of exposure is removed after developing, and remaining photoresist film carries out the corrosion of following thin-film material as etch mask layer.Finish after the thin film corrosive, photoresist film is removed.Repeat above-mentioned processing step for several times, use different thin-film materials at every turn, can make the device architecture of certain pattern according to specific mode.
Each layer film thickness of formation film transistor device structure between thousands of dusts, can form the abrupt slope step hundreds of in the process of making thin-film transistor structure.Be necessary the surface topography on the obvious abrupt slope of planarization, make each layer film of film transistor device accurately be superimposed on another layer film at assigned address, this formation for metallic film or conductive film is even more important.Metallic film or conductive film are generally prepared by physical gas-phase deposite method such as sputter.Because the ion deposition directivity causes the limited conformal of film during sputter coating, make the film thickness of step side less than the film thickness of ledge surface.The minimizing of step side metallic film or conductive film cross section causes the increase of regional current density, causes the ageing failure of lead.Even more serious when being sputter coating, may cause step side not have thin film deposition fully, cause metallic film or conductive film to disconnect, film transistor device cisco unity malfunction and produce the bad point of display.This shows that before depositing metal films or conductive film, the film surface form planarization below them is very important.
As shown in Figure 5, the invention discloses a kind of insulation film is the TFT LCD array base-plate structure of non-conformal, comprising: film transistor device, transparent pixels electrode 10, grid line 1 and data wire 5, passivating insulation membrane 8 are formed.Film transistor device is made up of gate electrode 2, gate insulator 4, semiconductor active layer 3 and source, drain electrode 6,7.The drain electrode 7 of film transistor device is connected with pixel electrode 10 by the via hole 9 of passivating insulation membrane.The insulation film that the invention is characterized in this array base-plate structure is non-conformal, can be the structure of non-conformal as gate insulator 4 and passivating insulation membrane 8, also can be gate insulator become 4 and one of passivating insulation membrane 8 be non-conformal structure.Figure 6 shows that manufacturing array board structure of the present invention forms the cross-sectional view after pixel electrode is made, gate insulator 4 and passivating insulation membrane 8 these two insulation films are the structure of non-conformal in this structure.
Fig. 3 to Fig. 4 d has illustrated the formation method of non-comformal insulation film to reach pixel electrode or the metal electrode that forms successive line on non-comformal insulation film.
Embodiment one:
At first, as shown in Figure 3, provide a substrate 12 that has formed conductive film 13 (can be gate electrode film or source-drain electrode film etc.).
Then, in plasma enhanced chemical vapor deposition equipment, place aforesaid substrate 12, except the plasma reinforced chemical vapour deposition equipment to the deposition insulation film feeds the reacting gass such as silane, ammonia and nitrogen, also feed the mixed gas of inert gas argon gas or helium or helium and hydrogen, in thin film deposition, carry out the film etching, form the insulation film 14 of non-conformal.As feeding the inert gas argon gas to plasma, the argon ion of generation is accelerated to substrate surface under electric field action, and the film etching takes place when causing deposit film the bombarded surface film.As shown in Figure 3, because the preferential etching characteristic of the outstanding wedge angle portion of step, the insulation film 14 on the conductive film 13 forms the mild step of non-conformal.
Embodiment two:
Fig. 4 a to Fig. 4 d has provided the concrete making flow process of this embodiment.
At first, provide a substrate 12 that has formed conductive film 13 (may be grid line and gate electrode or source-drain electrode etc.).
Subsequently, in plasma enhanced chemical vapor deposition equipment, place described substrate 12, feed reacting gass such as silane, ammonia and nitrogen to reaction chamber, after the certain hour, deposit certain thickness ground floor insulation film 14a, stop the feeding of reacting gas.Because the inherent conformal nature of plasma reinforced chemical vapour deposition, ground floor insulation film 14a forms the perpendicular steps shown in Fig. 4 a.
Then, feed inert gas to plasma enhanced chemical vapor deposition equipment, depress in that certain power is gentle, produce inert gas plasma, the ion sputtering corrosion takes place in inert gas ion bombardment substrate surface.Preferential sputtering takes place in the step turning of insulation film, causes manyly than the film etching on plane, forms the mild transition shoulder shown in Fig. 4 b.Feed reacting gas to reaction chamber, the insulation film of deposition predetermined thickness forms the second layer insulation film 14b shown in Fig. 4 c.
At last, on second layer insulation film 14b, form second layer conductive film 15 by sputter, promptly drain electrode or pixel electrode promptly form the continuous conduction film, shown in Fig. 4 d.
Above-mentioned explanation is the method for a kind of two step plated films and a step etching, for pitch time and the non-conformal thin film of reaching optimization, can implement the method for multistep plated film and multistep etching, promptly repeats to carry out successively plated film and etching.
In above-mentioned specific embodiment, when using first method to carry out deposit film and etched film simultaneously, in order to keep the ion bombardment etching effect, it is essential that vacuum degree remains between 1 millitorr to 100 millitorr.Second method deposits separately and etched film successively, and the vacuum degree when carrying out thin film deposition can maintain the holder magnitude.Cause the deposition rate of second method will be higher than the deposition rate of first method thus.But second method adopts the iterative process of multistep deposition, etching, deposition, so two kinds of methods consume the insulation film of close time sedimentary facies stack pile.Use above-mentioned two kinds of methods all can form slick and sly insulation film step, sputtering sedimentation one layer thickness is the transparent conductive film or the metallic film of 100 dust to 5000 dusts on this insulation film, can form the second layer conductive film 15 of the successive line shown in Fig. 4 d, thereby, cause the bad point of display significantly to reduce because the not visible defective that pixel electrode 10 broken strings cause is significantly reduced.
Fig. 6 to Fig. 9 c signal uses method of the present invention to make a kind of TFT LCD array base palte.
At first, on glass substrate, use sputtering equipment deposition ground floor metallic film such as aluminium neodymium alloy, aluminium, molybdenum etc., keep underlayer temperature between 10oC to 200oC, vacuum degree is below 50 millitorrs, the grid metallic film of deposit thickness between 1000 dust to 6000 dusts is by photoetching process formation gate electrode 2 as shown in Figure 6.
Then, the plasma enhanced chemical vapor deposition equipment that uses AKT company or JEL company to provide, deposition gate insulator 4 on gate electrode 2.Keep put substrate the base temperature between 200 ℃ to 400 ℃, feed 400 to 3000sccm silane, 1000 to 10000sccm ammonia, 10000 to 30000sccm nitrogen and 1000 to 10000sccm argon gas simultaneously to reaction chamber, the vacuum degree of feedback circuit control reaction chamber of utilizing vacuum pump and vacuum gauge is between 1 millitorr to 100 millitorr, and (corresponding 0.07 to 0.7watt/cm between 1000 to 10000 watts
2) plasma power of optimized choice reaction chamber, the etch rate by above-mentioned process conditions control insulation film and the ratio of deposition rate are between 0.01 and 0.1.The ratio of etch rate and deposition rate influences film morphology and pitch time, and the ratio of too small etching deposition rate causes forming the insulation film step of non-conformal, and the ratio of excessive etching deposition rate causes the sedimentation time lengthening of insulation film.Use the reaction chamber process conditions of optimizing, on grid 2, realize the mild transition shoulder of gate insulator 4 shown in Fig. 7 b.In this specific embodiment, can use other inert gas that is different from argon gas, mixed gas as helium or helium and hydrogen, with the reactant gas silane, ammonia and the nitrogen that form insulation film together, to the helium of reaction chamber feeding 1000 to 10000sccm, also can realize the insulation film pattern shown in Fig. 7 b.Grid insulating film in this step adopts the formation method of embodiment one to be prepared from.
Grid insulating film in this step also can use the formation method preparation of embodiment two.The plasma enhanced chemical vapor deposition equipment that uses AKT company or JEL company to provide, deposition is as the ground floor insulation film of gate insulator 4.Keep put substrate the base temperature between 300 ℃ to 400 ℃, feed 400 to 5000sccm silane, 1000 to 10000sccm ammonia and 10000 to 30000sccm nitrogen to reaction chamber, the vacuum degree of feedback circuit control reaction chamber of utilizing vacuum pump and vacuum gauge is between 500 millitorr to 3000 millitorrs, and (corresponding 0.07 to 0.7watt/cm between 1000 to 10000 watts
2) plasma power of optimized choice reaction chamber, the ground floor gate insulator 4 of high speed deposition thickness between 1000 dust to 10000 dusts forms the structure shown in Fig. 7 a.Stop the feeding of silane, ammonia and nitrogen, replace inert gas as 1000 to 20000sccm argon gas or helium, the vacuum degree of feedback circuit control reaction chamber of utilizing vacuum pump and vacuum gauge is below 100 millitorrs, and (corresponding 0.07 to 0.7watt/cm between 1000 to 10000 watts
2) plasma power of optimized choice reaction chamber, utilize ion bombardment effects etching ground floor gate insulator 4, make its thickness reduce to original depth half.Stop the feeding of inert gas, feed 400 to 5000sccm silane, 1000 to 10000sccm ammonia and 10000 to 30000sccm nitrogen to reaction chamber again, the vacuum degree of control reaction chamber is between 500 millitorr to 2000 millitorrs, and (corresponding 0.07 to 0.7watt/cm between 1000 to 10000 watts
2) plasma power of optimized choice reaction chamber, the second layer gate insulator 4 of high speed deposition thickness between 1000 dust to 10000 dusts forms the structure shown in Fig. 7 b.
The plasma enhanced chemical vapor deposition equipment that uses AKT company or JEL company to provide, keep put substrate the base temperature between 200 ℃ to 400 ℃, feed 500 to 3000sccm silane and 5000 to 30000sccm hydrogen simultaneously to reaction chamber, the vacuum degree that keeps reaction chamber is between 1000 millitorr to 5000 millitorrs, and (corresponding 0.07 to 0.35watt/cm between 500 watts to 5000 watts to select plasma power
2), at the semiconductor active layer 3 of deposit thickness on the gate insulator 4 between 1000 dust to 5000 dusts, by the active layer isolated island of photoetching process formation shown in Fig. 7 c.
Subsequently, on substrate, use sputtering equipment deposition second layer metal film such as aluminium neodymium alloy, aluminium, molybdenum etc., keep underlayer temperature between 10 ℃ to 200 ℃, vacuum degree is below 50 millitorrs, metallic film is leaked in the source of deposit thickness between 1000 dust to 6000 dusts, by photoetching process formation source electrode 6 and drain electrode 7 as shown in Figure 8.
Again, the plasma enhanced chemical vapor deposition equipment that uses AKT company or JEL company to provide, deposition passivating insulation membrane 8 on source-drain electrode 6,7.Keep put substrate the base temperature between 200 ℃ to 400 ℃, feed 400 to 3000sccm silane, 1000 to 10000sccm ammonia, 5000 to 30000sccm nitrogen and 1000 to 10000sccm argon gas simultaneously to reaction chamber, the vacuum degree of feedback circuit control reaction chamber of utilizing vacuum pump and vacuum gauge is between 1 millitorr to 100 millitorr, and (corresponding 0.07 to 0.7watt/cm between 1000 to 10000 watts
2) plasma power of optimized choice reaction chamber, the etch rate of control insulation film and the ratio of deposition rate are between 0.01 and 0.1.The ratio of etch rate and deposition rate influences film morphology and pitch time, and the ratio of too small etching deposition rate causes forming the insulation film step of non-conformal, and the ratio of excessive etching deposition rate causes the sedimentation time of insulation film to increase.By suitable reaction chamber process conditions, realize the insulation film step of the mild transition shown in Fig. 9 b.In this specific embodiment, can use other inert gas that is different from argon gas, mixed gas as helium or helium and hydrogen, with the reactant gas silane, ammonia and the nitrogen that form insulation film together, to the helium of reaction chamber feeding 1000 to 10000sccm, also can realize the insulation film pattern shown in Fig. 9 b.The non-conformal structure of the passivating insulation membrane in this step adopts the formation method of embodiment one to be prepared from.
Passivating insulation membrane in this step also can use the formation method preparation of embodiment two.The plasma enhanced chemical vapor deposition equipment that uses AKT company or JEL company to provide, deposition is as the ground floor insulation film of passivating insulation membrane 8.Keep put substrate the base temperature between 300 ℃ to 400 ℃, feed 400 to 5000sccm silane, 1000 to 10000sccm ammonia and 5000 to 30000sccm nitrogen to reaction chamber, the vacuum degree of feedback circuit control reaction chamber of utilizing vacuum pump and vacuum gauge is between 500 millitorr to 5000 millitorrs, and (corresponding 0.07 to 0.7watt/cm between 1000 to 10000 watts
2) plasma power of optimized choice reaction chamber, the ground floor passivation protection film 5 of high speed deposition thickness between 1000 dust to 5000 dusts forms the structure shown in Fig. 9 a.Stop the feeding of silane, ammonia and nitrogen, replace inert gas as 1000 to 20000sccm argon gas or helium, the vacuum degree of feedback circuit control reaction chamber of utilizing vacuum pump and vacuum gauge is below 100 millitorrs, and (corresponding 0.07 to 0.7watt/cm between 1000 to 10000 watts
2) plasma power of optimized choice reaction chamber, utilize ion bombardment effects etching ground floor passivation protection film 5, make its thickness reduce to original depth half.Stop the feeding of inert gas, feed 400 to 5000sccm silane, 1000 to 10000sccm ammonia and 5000 to 30000sccm nitrogen to reaction chamber again, the vacuum degree of control reaction chamber is between 500 millitorr to 2000 millitorrs, and (corresponding 0.07 to 0.7watt/cm between 1000 to 10000 watts
2) plasma power of optimized choice reaction chamber, the second layer passivating insulation membrane 8 of high speed deposition thickness between 1000 dust to 5000 dusts forms the passivation protection film step of the mild transition shown in Fig. 9 b.
At last, by the passivating insulation membrane via hole 9 of photoetching process formation shown in Fig. 9 c, and on substrate, use sputtering equipment to deposit layer of transparent conductive film such as tin indium oxide, indium zinc oxide etc., keep underlayer temperature between 10 ℃ to 300 ℃, vacuum degree is below 50 millitorrs, the transparent conductive film of deposit thickness between 100 dust to 1000 dusts is by photoetching process formation pixel electrode 10 as shown in Figure 6.
Above-mentionedly only provided preferable embodiment, it can carry out various forms of accommodations, as only adopt formation method preparation of the present invention on gate insulator, also can only adopt formation method preparation of the present invention on passivation insulation.
It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art should can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.
Claims (12)
1, a kind of formation method of insulation film of non-conformal is characterized in that, comprising:
Step 1 provides a substrate;
Step 2 is placed array base palte in chemical vapor depsotition equipment, feed reacting gas and inert gas to reaction chamber, carries out the film etching in thin film deposition, forms the insulation film of non-conformal;
The ratio of the speed of film etching and thin film deposition is between 0.01 to 0.1 in the described step 2.
2, formation method according to claim 1 is characterized in that: when feeding reacting gas and inert gas in the described step 2 silane flow rate between 400 to 3000sccm, between the ammonia flow 1000 to 10000sccm, nitrogen flow between 5000 to 30000sccm and argon flow amount between 1000 to 10000sccm; Reaction chamber vacuum degree is between 1 millitorr to 100 millitorr; Plasma power 0.07 to 0.7watt/cm
2Between.
3, formation method according to claim 1 is characterized in that: when described step 2 feeds reacting gas and inert gas silane flow rate between 400 to 3000sccm, between the ammonia flow 1000 to 10000sccm, nitrogen flow between 5000 to 30000sccm and helium gas flow between 1000 to 10000sccm; Reaction chamber vacuum degree is between 1 millitorr to 100 millitorr; Plasma power 0.07 to 0.7watt/cm
2Between.
4, a kind of by arbitrary described grid insulating film and/or the passivating insulation membrane that insulation film that method forms non-conformal is used to form TFT LCD array base-plate structure TFT device that form of claim 1 to 3.
5, a kind of formation method of insulation film of non-conformal is characterized in that, comprising:
Step 1 provides a substrate;
Step 2 is placed described substrate in chemical vapor depsotition equipment, feed reacting gas to reaction chamber and form the ground floor insulation film, stops then feeding reacting gas to reaction chamber;
Step 3 feeds inert gas to chemical vapor depsotition equipment, ion bombardment etching ground floor insulation film, make its thickness reduce to original depth half, stop then feeding inert gas to reaction chamber;
Step 4 feeds reacting gas to reaction chamber and forms second layer insulation film.
6, formation method according to claim 5, it is characterized in that: when feeding reacting gas in described step 2 and the step 4 silane flow rate between 400 to 5000sccm, between the ammonia flow 1000 to 10000sccm, nitrogen flow is between 5000 to 30000sccm, the vacuum degree of reaction chamber between 500 millitorr to 3000 millitorrs, plasma power 0.07 to 0.7watt/cm
2Between.
7, formation method according to claim 5 is characterized in that: the ground floor insulation film thickness that described step 2 forms is between 1000 to 10000 dusts.
8, formation method according to claim 5 is characterized in that: the second layer insulation film thickness that forms in the described step 4 is between 1000 to 10000 dusts.
9, formation method according to claim 5 is characterized in that: feeding inert gas in the described step 3 is the mixed gas of helium, argon gas or helium and hydrogen.
10, formation method according to claim 5, it is characterized in that: when described step 3 intermediate ion bombards etching, inert gas flow between 1000 to 20000sccm, the vacuum degree of reaction chamber below 100 millitorrs, plasma power 0.07 to 0.7watt/cm
2Between.
11, formation method according to claim 5 is characterized in that: described step 2 to step 4 can repeat repeatedly, and promptly multistep plated film and multistep etching repeatedly repeat plated film and etching.
12, a kind of by arbitrary described grid insulating film and/or the passivating insulation membrane that insulation film that method forms non-conformal is used to form TFT LCD array base-plate structure TFT device that form of claim 5 to 11.
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| CNB2006101498857A CN100524780C (en) | 2006-10-27 | 2006-10-27 | TFT LCD array substrate structure and method for forming non-comformal insulation film and use |
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| CNB2006101498857A CN100524780C (en) | 2006-10-27 | 2006-10-27 | TFT LCD array substrate structure and method for forming non-comformal insulation film and use |
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| CN100524780C true CN100524780C (en) | 2009-08-05 |
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| CN109599345B (en) * | 2018-10-31 | 2020-03-20 | 厦门市三安集成电路有限公司 | Method for preventing metal connecting wire of heterojunction bipolar transistor from being easily broken |
| CN109616418B (en) | 2018-12-06 | 2021-11-09 | 合肥鑫晟光电科技有限公司 | Thin film transistor, display substrate, manufacturing method of display substrate and display device |
| CN110246885B (en) * | 2019-06-28 | 2021-10-01 | 上海天马有机发光显示技术有限公司 | Display panel |
| CN111290183A (en) * | 2020-03-31 | 2020-06-16 | Tcl华星光电技术有限公司 | Double-conductive-layer wiring, manufacturing method thereof and display panel |
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