CN100508440C - Parallel processing of decoding and of a cyclic redundancy check when mobile radio signals are received - Google Patents
Parallel processing of decoding and of a cyclic redundancy check when mobile radio signals are received Download PDFInfo
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- CN100508440C CN100508440C CNB038199866A CN03819986A CN100508440C CN 100508440 C CN100508440 C CN 100508440C CN B038199866 A CNB038199866 A CN B038199866A CN 03819986 A CN03819986 A CN 03819986A CN 100508440 C CN100508440 C CN 100508440C
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- 125000004122 cyclic group Chemical group 0.000 title claims description 17
- 238000012545 processing Methods 0.000 title description 7
- 238000000034 method Methods 0.000 claims abstract description 35
- 230000003213 activating effect Effects 0.000 claims 1
- 238000012432 intermediate storage Methods 0.000 abstract 1
- 230000005540 biological transmission Effects 0.000 description 8
- 230000009183 running Effects 0.000 description 8
- 238000011144 upstream manufacturing Methods 0.000 description 4
- 230000008676 import Effects 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 238000012937 correction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0046—Code rate detection or code type detection
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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Abstract
According to the sequence of the decoder user signal (am1, ..., amA) and redundancy check bits (Pm1, ..., PmL) delivered by the Viterbi-Traceback, said bits are introduced into a shift register with linear feedback (10) by either a distributor (1), partially from the front and partially from the rear, or all of said bits are introduced from the rear into a shift register with linear feedback (20), if the unaltered coefficient occupancy remains unchanged, or from the front if coefficient occupancy is inverted. In this manner, a redundancy check can be carried out in the shift register (10) on a transmitted data block without the intermediate storage of bits delivered in the decoding process.
Description
Technical field
The present invention relates to the parallel processing of receiving mobile radiotelephone signal decoding and cyclic redundancy check (CRC) of advocating, and relate to the corresponding intrument that carries out according to the inventive method as independent claims.
Background technology
In the example of digital data transfer, often carry out cyclic redundancy check (CRC), to detect the mistake that in the data distributing program process, is taken place.In this example, transmission of data signals in piece, and in each piece, produce a redundant code by described data, and described redundant code is added to described be used for error detection or correction.In most example, use an operation method that is predetermined, obtaining so-called CRC sign indicating number (cyclic redundancy check (CRC)) by load data in one becomes a cyclic redundancy code.Multiply by a so-called generator multinomial (generator polynomial) by a load data burst, and produce described CRC sign indicating number.After receiving code character, divided by described generator multinomial.If the character code of being received is correctly transmitted, then described division routine can not produce any remainder.On the contrary, if described division routine produces a remainder, determine that then described transmission is incorrect.
(linear feedback shiftregister LFSR) simply carries out multiplication of polynomial and division, so the main interest of this case is for example CRC sign indicating number of cyclic code owing to can pass through so-called linear feedback shift register.Thereby described generator multiplication of polynomial can produce code character, by the renewable raw information character of the division of these code characters, and the while check errors.United States Patent (USP) 5,748,652 disclose the cyclic redundancy check (CRC) circuit for example be used to detect with error recovery in a data flow.In this example, in receiver, described in a linear feedback shift register input traffic, wherein be to carry out division by the generator multinomial.If remove an error code character in this circuit, in case then handled described code character, after division, the remainder that is generated by described generator multinomial is retained in the memory cell (cell) in the described shift register.Only have if imported a correct code character, then after division routine, the value in all memory cell is zero.Then this division remainder is delivered to decoder, and if activate described decoder, then in an XOR (EXCLUSIVE-OR) circuit, link the Input Data word symbol, thereby produce a data flow of proofreading and correct.
In order to improve transmission confidence level and eavesdropping protection, the data that institute's tendency to develop is defeated are provided in emitter terminals to a channel coding method, wherein add redundant in the defeated data of described tendency to develop modestly.If use convolutional encoding to be coding method, wherein link the lasting redundancy that forms by information (convolution), then in the decoder of described receiver end, use the Viterbi operation method usually.Found at first on the block encoding data, to carry out after the convolutional encoding program, can reach low error rate by carrying out a crc block coded program.In a chnnel coding that links, usually by a block code, elder generation adds to described information with a plurality of CRC position and is transmitted.The information coding that then, in this mode, will be encoded by a convolution coder.At described receiver end, the recurrence data sequence that described convolution coder provided of deducing then by described Viterbi trace-back operation method.
Treatment step among the 3GPPP-UMTS standard TS 25.212, its thinner auspicious being described as follows.In described emitter terminals, overlap in the measure-alike transport block one, increase by a CRC sign indicating number for each transmission block.For reaching this purpose, described CRC sign indicating number generator has four generator multinomials and has multinomial grade 8,12,16 and 24, and it can be expressed as follows:
(1)g
CRC8(D)＝1+D+D
3+D
4+D
7+D
8，
(2)g
CRC12(D)＝1+D+D
2+D
3+D
11+D
12，
(3)g
CRC16(D)＝1+D
5+D
12+D
16，
(4)g
CRC24(D)＝1+D+D
5+D
6+D
23+D
24。
By determine to define the selection of one of these multinomials in described emitter terminals.
Begin by (in the cover transmission block) m transmission block, as the vector of bit length A
(5)a
m＝(a
m1，a
m2，...，a
mA)，
According to above-mentioned standard, carry out the CRC of system coding, thereby multinomial
(6)z
m(D)＝p
mL+p
m(L-1)D+...+p
m1D
L-1+a
mAD
L+a
m2D
A+L-2+a
m1D
A+L-1
Has null remainder divided by described generator multinomial g (D).At described load signal vector a
mIn the position, and institute's rheme is corresponding to the residue multinomial
(7)p
m(D)＝p
mL+p
m(L-1)D+...+p
m1D
L-1
Be to be mapped across a vectorial b
mAs follows:
(8)b
m＝(b
m1，b
m2，...，b
m(A+L))＝(a
m1，...，a
mA，p
mL，...，p
m1)
In this example, the position corresponding to highest index in equation (6) is to be positioned at described vectorial b
mIn important position least.Described load signal position is to be positioned at described vectorial b
mIn more unessential position, and relatively, described CRC position is to be positioned at center-stage.Yet described CRC check position is the described vectorial b that is mapped across in its original series
m, that is be to be mapped across b corresponding to the coefficient of the lowest index in the described residue multinomial
mIn more unessential position.Especially, corresponding to the coefficient p of highest index in the residue multinomial
M1Be to meet b
mIn position, most important position.
Then, the whole M transport block with CRC check position are connected to each other, and are sent to channel encoder.
In the channel decoding program that described receiver end carried out, can be undertaken by multitude of different ways.In " sliding window method ", the data-signal reclaim in described sequence in wherein is provided in the described encoder that returns in described emitter terminals with described data-signal.So-called actual Viterbi in this case use that the applicant prefers recalls in the running, wherein said Viterbi decoder stores described retrieve data in whole trellis (trellis), relatively, in opposite sequence, be recovered in emitter terminals and be used to return data-signal described in of encoder, that is the sequence of equation (8) right side indication.Present problem is that described load signal position and the parity bit that produces can't directly be sent to known crc error decision-making circuit in this sequence, it is formed by the moving road of linear feedback shift device.Thereby, at first for one or a whole set of piece of checking, in a buffer storage, store so-called hard determining sequence (it is to occur in the described Viterbi trace-back process to produce) corresponding to signal data that described vectorial bm reclaims.Then, convene described data-signal, and it is delivered to shift register in the described crc error decision-making circuit from described buffer storage.On the one hand, in the part of hard disk, because enough memory headrooms must be arranged, be complicated, and on the other hand, because described data must be stored in the described internal memory and must be from its set once, so cause temporal delay so temporarily store described value.
Yet, when recalling in Viterbi when using above-mentioned sliding window method, based on the required bit sequence of translator, before carrying out redundancy check, the demand of above-mentioned temporary transient storage may take place.In this example, also may increase or obtain describedly to join class or redundancy check from described translator, thereby described bit sequence allow described payload data bits and parity bit directly to be sent to described linear feedback shift register to be used for polynomial division in described data block at receiver end.
Moreover, a kind of situation can take place, wherein by bit sequence that translator produced be used for and shift register opposite as the bit sequence of cyclic redundancy check (CRC), to carry out a correct polynomial division.In this example, the mode of at first available complexity temporarily is stored in these positions in the buffer storage.
Summary of the invention
Therefore, a purpose of the present invention provides the method for mobile radiotelephone signal cyclic redundancy check (CRC), and the corresponding intrument that carries out described method, described method meets the sequence of payload data bits and the parity bit that described translator is produced, thereby reduce complexity and potential time, mainly can decipher and cyclic redundancy check (CRC) between parallel processing.The present invention's one special purpose is the described data-signal that is determined in translator directly to be delivered to a shift register carry out cyclic redundancy check (CRC), and does not need temporary transient storage.
Reach purpose of the present invention by the feature in the independent claims.More favourable modification and development are described in the claim dependent claims.Moreover Patent right requirement is provided for carrying out the device of the method according to this invention.
According to the present invention, such as in the independent claims the method for opinion mobile radiotelephone signal cyclic redundancy check (CRC) be based on this situation, wherein in emitter terminals, respectively at forming a for example CRC position of a load signal bit sequence and a redundancy check bit sequence in the piece, and it is delivered to a channel encoder, decipher described bit sequence at the receiver end of a decoder, its decision is used for the sequence of channel encoder and sends the value that is determined, thereby described bit sequence is not suitable for carrying out immediately cyclic redundancy check (CRC) in essence, that is directly the position that determined of input to a linear feedback shift register (LFSR), with it in order to reach this purpose.
Depend on the bit sequence that produces by described translator, the invention provides two kinds of methods, it can make and the redundancy check that bit sequence and described decoder produced of decoded load signal position be sent to a LFSR, and does not need temporarily to be stored in the buffer storage earlier.
The described bit sequence that is provided for example can be a sequence, though wherein first group of position occurs in the suitable sequence, yet, dibit is with respect to described first group and suitable location is arranged, and moreover described dibit be in inappropriate sequence, that is opposite sequence.So according to the present invention, first method provides some positions, it is sent to described shift register from front end, and some other positions, and it is sent to described shift register from the rear end.
To carry out known polynomial division program, the bit sequence that is produced is opposite fully compared to the required bit sequence of the known LFSR that is directly inputted into the polynomial division program.In this example, can use according to second method of the present invention, details are as follows on its basis, from the rear end institute's rheme is all inserted known LFSR continuously, and do not need to change the coefficient that is arranged in multiplier, or in known manner, all insert LFSR continuously in the position from front end, but the coefficient that is arranged in described multiplier is reversed.
In described two kinds of examples, can described LFSR be delivered in the position by suitable device, need not use buffer storage.In case the last position in data block has been inserted into described LFSR, then carries out the polynomial division program in described LFSR, thereby forms cyclic redundancy check (CRC).
The device that is used to carry out first method comprises a distributor, it has an input and two outputs, an and linear feedback shift register, first output of described distributor is first input that is connected to described shift register, and second output of described distributor is second input that is connected to shift register.To import the input of described distributor by the hard decision output valve of decoder.Provide one to control signal to described distributor, thereby described data-signal is delivered to described first output or second output.First input of described shift register is a side that is positioned at described shift register, and described data-signal is delivered to described shift register in this side, yet second input of described shift register is the opposite side that is positioned at described shift register chain, and in this side described data-signal is delivered to described shift register.Contact-making switch is two inputs that are positioned at described shift register, and can be unlocked and close, and optionally to see through first input or second input, signal bits is offset to described shift register.
According to the present invention, described second method is based on bit sequence, and it is produced and reversed by translator.So, described method provides described bit sequence, it is delivered to a linear feedback shift register, be used for redundancy check, and do not need to use any above-mentioned distributor, but institute's rheme is supplied to described shift register from the rear end, and not needing to change described sequence, wherein said coefficient is to be arranged in described multiplier, or institute's rheme is delivered to described shift register from front end, but in described sequence, described coefficient is to be positioned at multiplier and to be reversing.
Two aspects of the present invention are meant and can directly deliver to described CRC check program with from a Viterbi decoder or from other position that decoder was obtained based on trellis.Can be immediately these be inserted described shift register in the described CRC circuit, and do not need temporarily to be stored in the buffer storage that is used for this purpose, then buffer storage is covered and is loaded onto described shift register since then.So, do not need to provide the hardware of buffer storage, with and can save time of storing institute's rheme and with its time of in internal memory, convening.
Thereby enforcement of the present invention also is illustrated in a data block or in a sets of data piece, decoding is superfluous in the parallel processing of verification with circulation.So, if for example running is recalled in a Viterbi decoder or other decoder use one based on trellis, transfer to the described data sequence of channel encoder with the recurrence decision, it also can deliver to described CRC check circuit with the position that is determined, thereby can be inserted in the described shift register.When returning in described Viterbi decoder followed the trail of running when having determined in the data block last, then in being offset to described shift register, work as before the position, determined institute's rheme, and in case insert described last the time, then can see through described or (OR) grid directly send described CRC check program.
Thereby the parallel processing of this kind form can further be saved the processing time at receiving terminal.
Description of drawings
According to the present invention, more details are as follows in two aspects of described method, and see also corresponding intrument and graphic embodiment.
Fig. 1 is the device that explanation is used to carry out first method, has a shift register and the upstream distributor commonly used.
Fig. 2 is the device that explanation is used to carry out first method, has the shift register of commonly using, and provides position and coefficient to be reversing at front end.
Embodiment
As shown in Figure 1, on actual Viterbi recalls the Viterbi decoder of running produce and for a transport block m by the described decoded position of recalling running and producing, be input generation at described CRC circuit.As described in above-mentioned equation (8), institute's rheme comes across described input becomes determined result, in opposite time series, at sequence p
M1..., p
ML, a
MA..., a
M1In decoder in.
According to the present invention, at first described device has a distributor 1, and it is in order to institute's rheme is distributed between two different output D1 and the D2.Described distributor 1 topic is for a control signal CTRL, to switch the signal output between D1 and the D2.
The output D1 of described distributor 1 and D2 are connected to the preceding input and back input of a linear feedback shift register (LFSR) 10 respectively.Described LFSR 10 carries out the polynomial division program in known manner, whether correctly transmits described data block with verification.Described LFSR 10 has many memory cell 2, and in each clock pulse (clock) step, it is stored in the value of input and the value that will before store is delivered to output.Shown in point, other memory cell 2 can be positioned at S
2The expression memory cell 2 and on described shift register right side with S
L-1Memory cell 2 between.Reset (reset) that each memory cell 2 has himself imports, thereby for example in the beginning of handling procedure, all memory cell 2 can be made as zero.XOR (exclusive-or) grid 3 is to be connected between the memory cell 2, and adds to the output valve that comes from multiplier 4 in order to the value with indivedual upstreams memory cell 2.In described multiplier 4, be used to import on duty with 0, the coefficient g of 1} cover
n, and product sent.Described coefficient g
nBe corresponding to the coefficient in the selected generator multinomial of described emitter terminals.Described memory cell 2 also is connected to or grid (OR gate) 5.Foregoing United States Patent (USP) 5,748,652 after finishing described CRC check running, uses the content of described memory cell 2, whether forms remainder to determine described polynomial division.If not and all memory cell 2 values be zero, then described or grid 5 is in its output value of sending zero, thereby can illustrate and correctly transmit described data block.If not, even a memory cell 2 is also even only arranged in value 1, the remainder of then described polynomial division program also is not equal to 0, and described or grid 5 is in its output value of sending 1, thereby determines the described data of correct transmission.
Described CRC circuit also has contact-making switch 6 and 7, thereby can connect or interrupt contacting between the inputing or outputing of individual memory cell 2 and described LFSR 10 among the described LFSR 10.
Described CRC circuit running is as follows:
1. at first, contact-making switch 6 and 7 is to place position of the switch A, thereby described LFSR10 sets the skew bit from right to left.
2. for L clock pulse circulation, described distributor 1 activates described output D2 and cuts out output D1, and suitably controls described distributor 1 by described control signal CTRL.Thereby, at first described CRC check position p
M1..., p
MLImport the right side input of described LFSR 10, and from right to left by described LFSR 10.
3. then, contact-making switch 6 and 7 is placed in contact position B, thereby described LFSR 10 sets the described data bit of skew from left to right.
4. then,, activate the output D1 of described distributor 1, and close described output D2 for next A clock pulse circulation.In LFSR 10, move into information bit a by the left side
MA..., a
M1, and in described LFSR 10, be offset described information bit from left to right, activate the feedback line of described LFSR 10 and make described contact-making switch 7 in described position of the switch B.Once more, by appropriate control signals ztrl, initial described distributor 1 is switched to described output D1.
In a single day 5. insert information bit, can on the data block of institute's verification, carry out CRC check in output place of described OR grid 5.
6. surpass a transport block if described code block comprises, then described program is once more from 1 beginning.
Fig. 2 is the device that is used to carry out carrying out according to the present invention second method among the embodiment.Become when using the required bit sequence of known LFSR when the bit sequence of supply position reverses fully, use the method.
This device has a linear feedback shift register 20.XOR grid 3 is to be connected in to be denoted as S
0To S
L-1Series connected memory cell 2 between, and two input is the output that is connected to the output of multiplier 4 and indivedual upstreams memory cell 2 respectively.Be connected in last memory cell S
L-1Feedback line be to be connected to all multipliers 4.First multiplier 4 is to be connected to the first XOR grid 3, and it is the upstream that is connected to first memory cell 2, and the bit sequence that described translator produced is provided to its second input.The hypothesis basis of described embodiment is that described translator produces an order p
ML..., p
M1, a
MA..., a
M1, it comprises A load signal position and L redundancy check bit.The coefficient of being located makes receives described coefficient g
LDescribed multiplier 4 be to be connected to the first input side XOR grid 3, and receive described coefficient g
1Described multiplier 4 are the XOR grids 3 that are connected to the last outside, and will provide described multiplier 4 to the pointer natural sequence at the coefficient of intermediate treatment in the stage.If, can by the mode that has illustrated it be changed by the device (undeclared) that is connected to described shift register 20 for preestablishing coefficient positions.
Another device, it is equal to the device shown in Fig. 2 basically, is used to carry out described second method, and it is supposed by the bit sequence that described translator produced, sequence p
ML..., p
M1, a
MA..., a
M1Comprising A load signal position and L redundancy check bit, have the mirror image symmetry with device shown in Figure 2, is to be connected to be denoted as S by input position, OR grid right side and XOR (Exclusive-OR) grid
L-1Described memory cell.See through described shift register, be offset institute's rheme from right to left.In the left side, described feedback line is to be connected to be denoted as S
0The output of memory cell.
According to the present invention, use the described method especially can be, known as blindly transport format detecting (BTFD) in conjunction with specific 3GPP mode standard.The basis of this pattern is the size A of transport block and the sum M of transport block, and its dynamic variable changes between Transmission Time Interval (TTI).Because the selected transformat of present described reflector is to transmit on a control channel, so these parameters are generally the known parameter of described receiver.Yet, also may require described receiver to detect transport format blindly, and it is by might the transformat cover for selected institute in the transformat cover, carry out channel decoding and CRC translator and finish.The computing example of described BTFD pattern is to describe as the appendix A of 3GGP TS 25.212 standards " chnnel coding and multiplexing ".Owing in this pattern, must in the Viterbi decoder, carry out many runnings of recalling, and respectively follow CRC check, in fact reduce during total processing of channel decoding and CRC decoding.
Claims (8)
1. method that is used for the mobile radiotelephone signal that cyclic redundancy check (CRC) receives, described signal is that a decoder receives and deciphers and comprises a CRC sign indicating number, in described method, one data block, it is to recall translator by a Viterbi and produce and comprise load signal position and redundancy check bit, described data block is to deliver to the shift register with linear feedback, to carry out cyclic redundancy check (CRC), it is characterized in that:
To recall translator by described Viterbi is produced described load signal position and is supplied in the opposite sequence, wherein said load signal position is provided to a convolution coder in emitter terminals, thereby the described load signal position in described data block and redundancy check bit are at bit sequence P
M1..., P
ML, a
MA..., a
M1In, and
Produce the first group position, that is described redundancy check bit (P
M1..., P
ML), insert described shift register (10) in one first end, and then,
Produce the second group position, that is described load signal position (a
MA..., a
M1), insert described shift register (10) in one second end.
2. method as claimed in claim 1, it is characterized in that: a distributor (1) is delivered in described load signal position and described redundancy check bit, described distributor (1) has two output (D1, D2), be connected to described second end and described first end of described shift register (10) respectively, described distributor (1) be subjected to the control of a control signal (CTRL) and activate or close described output (D1, D2).
3. method as claimed in claim 2, it is characterized in that: activating described output (D1, D2) time, first output (D1) is to be connected to described second end of described shift register by closing first contact-making switch (6), and second output (D2) is to be connected to described first end of described register by closing second contact-making switch (7).
4. method as claimed in claim 3, it is characterized in that: when closing described first contact-making switch (6) of described first output (D1) that is connected to described distributor (1), described second contact-making switch (7) that is connected to described second output (D2) of described distributor (1) is unlocked simultaneously, and described first end of described shift register (10) is to be connected to an XOR grid (3) simultaneously by described second contact-making switch (7), and described XOR grid (3) is disposed between described first output (D1) and described first contact-making switch.
5. a device that is used to carry out as each method of claim 1 to 4 is characterized in that: comprise
One distributor (1), its have an input and two outputs (D1, D2),
One has the shift register (10) of linear feedback,
One first output (D1) of described distributor (1) is one first input that is connected to described shift register (10), and one second output (D2) of described distributor (1) is one second input that is connected to described shift register (10).
6. device as claimed in claim 5 is characterized in that:
One first contact-making switch (6) is connected in described first of described distributor (1) and exports between described first input of (D1) and described shift register (10), and
One second contact-making switch (7) is to be connected in described second of described distributor (1) to export between described second input of (D2) and described shift register (10).
7. device as claimed in claim 6 is characterized in that:
In one first position of the switch (A), described second contact-making switch (7) is connected to described second output (D2) of described distributor (1) described second input of described shift register (10), in a second switch position (B), described second contact-making switch (7) is connected to an XOR grid (3) with described second input of described shift register (10), and described XOR grid (3) is connected between described first output (D1) and described first contact-making switch (6) of described distributor (1).
8. as each device in the claim 5 to 7, it is characterized in that: the memory cell of described shift register (2) is to be connected to an OR grid (5).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10238841.5 | 2002-08-23 | ||
| DE10238841A DE10238841B4 (en) | 2002-08-23 | 2002-08-23 | Parallel processing of the decoding and the cyclic redundancy check when receiving mobile radio signals |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1679267A CN1679267A (en) | 2005-10-05 |
| CN100508440C true CN100508440C (en) | 2009-07-01 |
Family
ID=31501911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB038199866A Expired - Fee Related CN100508440C (en) | 2002-08-23 | 2003-06-25 | Parallel processing of decoding and of a cyclic redundancy check when mobile radio signals are received |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7461324B2 (en) |
| CN (1) | CN100508440C (en) |
| DE (1) | DE10238841B4 (en) |
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| US7181671B2 (en) * | 2003-09-23 | 2007-02-20 | Macronix International Co., Ltd. | Parallelized CRC calculation method and system |
| EP1938458B1 (en) * | 2005-09-21 | 2015-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Cyclic redundancy check circuit and devices having the cyclic redundancy check circuit |
| US7802166B2 (en) * | 2006-09-27 | 2010-09-21 | Qimonda Ag | Memory controller, memory circuit and memory system with a memory controller and a memory circuit |
| US7836386B2 (en) | 2006-09-27 | 2010-11-16 | Qimonda Ag | Phase shift adjusting method and circuit |
| US8379738B2 (en) * | 2007-03-16 | 2013-02-19 | Samsung Electronics Co., Ltd. | Methods and apparatus to improve performance and enable fast decoding of transmissions with multiple code blocks |
| US8386878B2 (en) | 2007-07-12 | 2013-02-26 | Samsung Electronics Co., Ltd. | Methods and apparatus to compute CRC for multiple code blocks |
| US7853857B2 (en) * | 2007-09-14 | 2010-12-14 | Motorola Mobility, Inc. | Multi-layer cyclic redundancy check code in wireless communication system |
| KR101462211B1 (en) * | 2008-01-30 | 2014-11-17 | 삼성전자주식회사 | Apparatus and method for decoding in portable communication system |
| US7987384B2 (en) * | 2008-02-12 | 2011-07-26 | International Business Machines Corporation | Method, system, and computer program product for handling errors in a cache without processor core recovery |
| CN101854222B (en) * | 2009-03-31 | 2014-04-02 | 华为技术有限公司 | Data processing method, communication device and system |
| US8543888B2 (en) | 2009-06-09 | 2013-09-24 | Microchip Technology Incorporated | Programmable cyclic redundancy check CRC unit |
| CN102006084A (en) * | 2010-09-26 | 2011-04-06 | 东南大学 | CRC (Cyclic Redundancy Check) coding method suitable for OFDM-UWB (Orthogonal Frequency Division Multiplexing- Ultra Wideband) system |
| CN102546089B (en) * | 2011-01-04 | 2014-07-16 | 中兴通讯股份有限公司 | Method and device for implementing cycle redundancy check (CRC) code |
| US8856609B2 (en) * | 2011-11-21 | 2014-10-07 | Broadcom Corporation | Accelerated cyclical redundancy check |
| US9286159B2 (en) * | 2013-11-06 | 2016-03-15 | HGST Netherlands B.V. | Track-band squeezed-sector error correction in magnetic data storage devices |
| US10552258B2 (en) | 2016-09-16 | 2020-02-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, electronic device, and driving method thereof |
| US10223194B2 (en) | 2016-11-04 | 2019-03-05 | Semiconductor Energy Laboratory Co., Ltd. | Storage device, semiconductor device, electronic device, and server system |
| TW202032368A (en) * | 2019-02-27 | 2020-09-01 | 智原科技股份有限公司 | Method of executing initial program load applied to electric apparatus |
| CN113574822B (en) * | 2019-03-13 | 2023-06-23 | 中兴通讯股份有限公司 | Wireless communication method, apparatus and computer readable medium |
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| JPS5784377A (en) | 1980-11-14 | 1982-05-26 | Nippon Denso Co Ltd | Device for detecting obstacle |
| JPH03214809A (en) * | 1990-01-19 | 1991-09-20 | Nec Corp | Linear feedback shift register |
| US5103451A (en) * | 1990-01-29 | 1992-04-07 | Motorola, Inc. | Parallel cyclic redundancy check circuit |
| JPH04140677A (en) * | 1990-10-01 | 1992-05-14 | Toshiba Corp | Semiconductor circuit |
| US5390199A (en) * | 1991-07-19 | 1995-02-14 | Anritsu Corporation | Advanced code error detection apparatus and system using maximal-length pseudorandom binary sequence |
| US5920593A (en) * | 1993-11-29 | 1999-07-06 | Dsp Telecommunications Ltd. | Device for personal digital cellular telephones |
| KR0147150B1 (en) * | 1995-06-29 | 1998-09-15 | 김주용 | Crc error debugging system using decoder |
| JP2996615B2 (en) * | 1996-01-08 | 2000-01-11 | 松下電器産業株式会社 | Viterbi decoding apparatus and method |
| US6272187B1 (en) * | 1998-03-27 | 2001-08-07 | Lsi Logic Corporation | Device and method for efficient decoding with time reversed data |
| JP4071879B2 (en) * | 1998-12-09 | 2008-04-02 | 富士通株式会社 | Error detector, communication system including the error detector, and error detection method |
| US6327691B1 (en) * | 1999-02-12 | 2001-12-04 | Sony Corporation | System and method for computing and encoding error detection sequences |
| KR100659265B1 (en) * | 2000-11-10 | 2006-12-20 | 삼성전자주식회사 | Circuit for detecting errors in a CRC code in which parity bits are attached reversely and a mothod therefor |
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2002
- 2002-08-23 DE DE10238841A patent/DE10238841B4/en not_active Expired - Fee Related
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2003
- 2003-06-25 CN CNB038199866A patent/CN100508440C/en not_active Expired - Fee Related
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2005
- 2005-02-23 US US11/063,949 patent/US7461324B2/en not_active Expired - Fee Related
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| Technical Specification Group Radio Access NetworkMultiplexing and channel coding (FDD) (Release 4). 3GPP.3GPP TS 25.212. 2002 * |
Also Published As
| Publication number | Publication date |
|---|---|
| DE10238841B4 (en) | 2010-01-28 |
| WO2004021630A1 (en) | 2004-03-11 |
| CN1679267A (en) | 2005-10-05 |
| US7461324B2 (en) | 2008-12-02 |
| DE10238841A1 (en) | 2004-03-11 |
| US20050229075A1 (en) | 2005-10-13 |
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