CN100505717C - I/Q signal A/D conversion DC offset controller - Google Patents
I/Q signal A/D conversion DC offset controller Download PDFInfo
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- CN100505717C CN100505717C CNB2005101027854A CN200510102785A CN100505717C CN 100505717 C CN100505717 C CN 100505717C CN B2005101027854 A CNB2005101027854 A CN B2005101027854A CN 200510102785 A CN200510102785 A CN 200510102785A CN 100505717 C CN100505717 C CN 100505717C
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Abstract
An A / D conversion type of DC offset controller for I / Q signal consists of index window IIR filter for filtering pilot I / Q symbol series with time synchronization in order to raise accuracy and stability of A / D conversion DC offset voltage regulation and compensation for I / Q signal ; index window IIR filter output for regulation control voltage of pulse density modulator for I channel and Q channel so as to accurately regulate, compensate and control A / D conversion DC offset voltage for I / Q signal by utilizing pulse density modulator output of I channel and Q channel .
Description
Technical field:
The present invention proposes a kind of novel, high reliability, low complex degree, jamproof i/q signal A/D conversion DC offset controller, can be used for realizing high integration, high accuracy, high sensitivity, high reliability, anti-interference, the Embedded third generation/the 4th third-generation mobile communication receiver, belong to moving communicating field.
Background technology:
In the radio receiver of a new generation's (as the third generation/the 4th third-generation mobile communication), analog baseband circuitry is responsible for finishing the analog demodulator process, convert the modulated-analog signal that receives to Serial No., send to digital baseband circuit, finish the digital demodulation process by digital baseband circuit again.Analog baseband circuitry demodulates and sends to digital baseband circuit from analog signal (as BPSK/QPSK/8PSK), be (original) same facies-suite (I signal) and (original) quadrature phase sequence (Q signal).
Analog baseband circuitry is to utilize high speed D/A (A/D) change-over circuit to finish the conversion of analog signal to original I/Q signal.Final stage in conversion, decision unit in the A/D change-over circuit is according to the level of each moment sample value of the signal that demodulates, the sample value that rules out this moment is bit 1 or bit 0, decision unit converts the sample value sequence of the signal that demodulates to binary (original) i/q signal sequence according to court verdict, sends to digital baseband circuit.
The DC of above-mentioned A/D change-over circuit (direct current) bias voltage has determined the judging threshold of decision unit, thereby to the accuracy of the sample value sequence judgement of the signal that demodulates, plays crucial effects.
Because the influence of extraneous factors such as interference, decline, the level of the analog signal that analog baseband circuitry receives often is in the dynamic changing process, causes the level of the i/q signal of A/D change-over circuit output also dynamically changing.If the level of analog signal exceeds the process range of A/D change-over circuit, just cause mistake in judgment probably to the sample value sequence of the signal that demodulates.Therefore, need dynamically adjust DC (direct current) bias voltage of A/D converting unit, make the A/D change-over circuit obtain maximum dynamic process scope according to the dynamic change of the i/q signal level of A/D change-over circuit output.
Summary of the invention:
Purpose of design: the present invention proposes a kind of novel, high reliability, low complex degree, jamproof i/q signal A/D conversion DC offset controller.The i/q signal A/D conversion DC offset controller that utilizes the present invention to propose can be accurately and timely dynamically adjusted the DC bias voltage of i/q signal A/D change-over circuit, has guaranteed the accuracy and the reliability of A/D change-over circuit output i/q signal.This DC offset controller, that utilization receives, from the level of the original I/Q signal of analog baseband circuitry unit (A/D change-over circuit), calculate the DC biasing control voltage of A/D change-over circuit, thereby realize adjustment, compensation and control i/q signal A/D conversion DC bias voltage.
Design: the interface and the structured flowchart of the i/q signal A/D conversion DC offset controller that the present invention proposes, shown in accompanying drawing one.
According to the present invention, i/q signal A/D conversion DC biasing control loop is by constituting with lower member: (1) I/Q data integrate gatherer; (2) I/Q symbol level quantizer; (3) first order pole IIR (infinite impulse response) filter; (4) pulse density modulator; (5) integration is owed sampler; (6) A/D converter.
In above-mentioned parts, except A/D converter is in analog baseband circuitry, other parts are all in digital baseband circuit.And i/q signal A/D conversion DC offset controller then is to be made of following 4 parts in the digital baseband circuit: (1) I/Q data integrate gatherer; (2) I/Q symbol level quantizer; (3) first order pole IIR (infinite impulse response) filter; (4) pulse density modulator.
This DC offset controller, that utilization receives, from the level of the original I/Q signal of analog baseband circuitry unit (A/D change-over circuit), calculate the DC biasing control voltage of A/D change-over circuit, thereby realize adjustment, compensation and control i/q signal A/D conversion DC bias voltage.
Original I/Q data from the Analog Baseband system are owed sampler by integration, finish the short period integration, and the result that integration draws is constituted new sequence, because new sequence is lower than the speed of original I/Q sequence, thereby are referred to as to owe sampled sequence.Integration is owed the output of sampler and is delivered to I/Q data integrate gatherer.I/Q data integrate gatherer is finished processing procedures such as short period integration, sampling, maintenance, elimination respectively to i/q signal, synchronously recover I symbol sebolic addressing and Q symbol sebolic addressing respectively.
By I symbol sebolic addressing and the Q symbol sebolic addressing that I/Q data integrate gatherer recovers, synchronously sent into quantizer, each I symbol and Q symbol is constantly done quantification treatment again.
I symbol sebolic addressing after the quantification and Q symbol sebolic addressing are sent to first order pole window index iir filter and carry out filtering.The result of filtering output is respectively applied for the pulse density modulator control voltage that the pulse density modulator of adjusting the I passage is controlled voltage and Q passage.
At last, the density modulation pulse of the pulse density modulator of the pulse density modulator of I passage and Q passage output is respectively applied for adjustments, compensation, controls the DC bias voltage of the A/D converter of I passage and Q passage.
The above is the basic principle and the course of work of i/q signal A/D conversion DC offset controller, below sets forth the relevant algorithm that this A/D conversion DC offset controller uses.
1. with in the i/q signal A/D conversion DC offset controller, original I/Q sequence through integration owe sampling, integration collect,
Quantizing process is remembered respectively by the sequence of quantizer output and to be made D
iAnd D
q
D
iBe the original I sequence through integration owe to sample, integration collection, quantizing process and the new sequence that constitutes;
D
qBe original Q sequence through integration owe to sample, integration collection, quantizing process and the new sequence that constitutes.
2.D
iAnd D
qCarry out filtering through first order pole window index iir filter
D
iAnd D
qBeing input to first order pole window index IIR (infinite impulse response) filter, carry out filtering by following formula.
DC
i(k)＝(1-β)·DC
i(k-1)+β·D
i(k) (EQ1)
DC
q(k)＝(1-β)·DC
q(k-1)+β·D
q(k) (EQ2)
In the formula, DC
i(k) be the pulse density modulator control contact potential series of I passage, DC
q(k) be the pulse density modulator control contact potential series of Q passage.K is D
iAnd D
qThe subscript of sequence.β is the forgetting factor of first order pole iir filter.
3. adjust the pulse density modulator control voltage of I passage and the pulse density modulator of Q passage respectively and control the pulse density modulator control voltage that voltage (1) is adjusted the I passage:
1) if DC
i(k)〉0, then the control voltage of the pulse density modulator of I passage is increased a voltage and adjust step delta c;
2) if DC
i(k)＜0, then the control voltage of the pulse density modulator of I passage is reduced by a voltage and adjust step delta c;
(2) pulse density modulator of adjusting the Q passage is controlled voltage
1) if DC
q(k)〉0, then the control voltage of the pulse density modulator of Q passage is increased a voltage and adjust step delta c;
2) if DC
q(k)＜0, then the control voltage of the pulse density modulator of Q passage is reduced by a voltage and adjust step delta c.
Technical scheme: the jamproof i/q signal A/D of novel high reliability low complex degree conversion DC offset controller, i/q signal A/D conversion DC biasing control loop is by constituting with lower member: (1) I/Q data integrate gatherer; (2) I/Q symbol level quantizer; (3) first order pole IIR (infinite impulse response) filter; (4) pulse density modulator; (5) integration is owed sampler; (6) A/D converter.
I/q signal A/D conversion DC offset controller, A/D converter is in analog baseband circuitry, all in digital baseband circuit, i/q signal A/D conversion DC offset controller then is to be made of following 4 parts in the digital baseband circuit: (1) I/Q data integrate gatherer to other parts; (2) I/Q symbol level quantizer; (3) first order pole IIR (infinite impulse response) filter; (4) pulse density modulator.
I/q signal A/D conversion DC offset controller, its original I/Q sequence is owed sampling through integration, the integration collection process, original I/Q data from the Analog Baseband system are owed sampler by integration, finish the short period integration, and the result that integration draws constituted new sequence, because new sequence is lower than the speed of original I/Q sequence, thereby be referred to as to owe sampled sequence, integration is owed the output of sampler and is delivered to I/Q data integrate gatherer, I/Q data integrate gatherer is finished the short period integration to i/q signal respectively, sampling, keep, processing procedures such as elimination synchronously recover I symbol sebolic addressing and Q symbol sebolic addressing respectively.
I/q signal A/D conversion DC offset controller, I symbol sebolic addressing and Q symbol sebolic addressing that I/Q data integrate gatherer is recovered quantize again, the I symbol sebolic addressing and the Q symbol sebolic addressing that recover by I/Q data integrate gatherer, synchronously sent into quantizer, each I symbol and Q symbol is constantly done quantification treatment again.
I/q signal A/D conversion DC offset controller is first order pole window index IIR filtering, D to I symbol sebolic addressing and Q symbol sebolic addressing after quantizing
iAnd D
qBeing input to first order pole window index IIR (infinite impulse response) filter, carry out filtering by following formula.
DC
i(k)＝(1-β)·DC
i(k-1)+β·D
i(k)
DC
q(k)＝(1-β)·DC
q(k-1)+β·D
q(k)
In the formula, DC
i(k) be the pulse density modulator control contact potential series of I passage, DC
q(k) be the pulse density modulator control contact potential series of Q passage.K is D
iAnd D
qThe subscript of sequence.β is the forgetting factor of first order pole iir filter.D
iBe the original I sequence through integration owe to sample, integration collection, quantizing process and the new sequence that constitutes; D
qBe original Q sequence through integration owe to sample, integration collection, quantizing process and the new sequence that constitutes.
In the i/q signal A/D conversion DC offset controller, the output of first order pole window index iir filter is used for adjusting respectively the pulse density modulator control voltage of I passage and the pulse density modulator control voltage of Q passage, it is characterized in that:
(1) pulse density modulator of adjusting the I passage is controlled voltage:
1) if DC
i(k)〉0, then the control voltage of the pulse density modulator of I passage is increased a voltage and adjust step delta c; 2) if DC
i(k)＜0, then the control voltage of the pulse density modulator of I passage is reduced by a voltage and adjust step delta c;
(2) pulse density modulator of adjusting the Q passage is controlled voltage:
1) if DC
q(k)〉0, then the control voltage of the pulse density modulator of Q passage is increased a voltage and adjust step delta c; 2) if DC
q(k)＜0, then the control voltage of the pulse density modulator of Q passage is reduced by a voltage and adjust step delta c.
In the i/q signal A/D conversion DC offset controller, the density modulation pulse of the pulse density modulator of the pulse density modulator of I passage and Q passage output is respectively applied for adjustments, compensation, controls the DC bias voltage of the A/D converter of I passage and Q passage.
The i/q signal A/D conversion DC offset controller that the present invention proposes, that utilization receives, from the level of the original I/Q signal of analog baseband circuitry unit (A/D change-over circuit), calculate the DC biasing control voltage of A/D change-over circuit, thereby realize adjustment, compensation and control i/q signal A/D conversion DC bias voltage.In this DC offset controller, adopt the window index iir filter that time synchronized pilot tone I/Q symbol sebolic addressing is carried out filtering, improved accuracy and reliability to i/q signal A/D conversion DC bias voltage adjustment and compensate for estimated.The output of window index iir filter, be used to adjust the control voltage of the pulse density modulator of I passage and Q passage, thereby make the output of pulse density modulator of I passage and Q passage can accurately adjust, compensate, control i/q signal A/D conversion DC bias voltage.This i/q signal A/D conversion DC offset controller is simple in structure, complexity is little, computing cost is low, A/D changes DC biasing control reliability height, is easy to realization, practical, be very suitable for being embedded in the communication chip and realize with hardware mode, can be directly commercial.
Description of drawings:
Fig. 1 is the interface and the structured flowchart of the jamproof i/q signal A/D of the novel high reliability low complex degree conversion DC offset controller that proposes of the present invention.
According to the present invention, i/q signal A/D conversion DC biasing control loop is by consisting of with lower member: (1) I/Q data integrate Collector; (2) I/Q symbol level quantizer; (3) first order pole IIR (infinite impulse response) wave filter; (4) impulse density Modulator; (5) integration is owed sampler; (6) A/D converter.
In above-mentioned parts, except A/D converter is in analog baseband circuitry, other parts are all in digital baseband circuit. And i/q signal A/D conversion DC offset controller then is to be made of following 4 parts in the digital baseband circuit: (1) I/Q The data integrate collector; (2) I/Q symbol level quantizer; (3) first order pole IIR (infinite impulse response) wave filter; (4) Pulse density modulator.
The function of said units and each other relation, all elaboration explanation in summary of the invention.
Embodiment:
Embodiment 1: with reference to accompanying drawing 1.Accompanying drawing 1 is the interface and the structured flowchart of novel, the high reliability that proposes of the present invention, low complex degree, jamproof i/q signal A/D conversion DC offset controller.
According to the present invention, i/q signal A/D conversion DC biasing control loop is by constituting with lower member: (1) I/Q data integrate gatherer; (2) I/Q symbol level quantizer; (3) first order pole IIR (infinite impulse response) filter; (4) pulse density modulator; (5) integration is owed sampler; (6) A/D converter.
In above-mentioned parts, except A/D converter is in analog baseband circuitry, other parts are all in digital baseband circuit.And i/q signal A/D conversion DC offset controller then is to be made of following 4 parts in the digital baseband circuit: (1) I/Q data integrate gatherer; (2) I/Q symbol level quantizer; (3) first order pole IIR (infinite impulse response) filter; (4) pulse density modulator.
This DC offset controller, that utilization receives, from the level of the original I/Q signal of analog baseband circuitry unit (A/D change-over circuit), calculate the DC biasing control voltage of A/D change-over circuit, thereby realize adjustment, compensation and control i/q signal A/D conversion DC bias voltage.
Original I/Q data from the Analog Baseband system are owed sampler by integration, finish the short period integration, and the result that integration draws is constituted new sequence, because new sequence is lower than the speed of original I/Q sequence, thereby are referred to as to owe sampled sequence.Integration is owed the output of sampler and is delivered to I/Q data integrate gatherer.I/Q data integrate gatherer is finished processing procedures such as short period integration, sampling, maintenance, elimination respectively to i/q signal, synchronously recover I symbol sebolic addressing and Q symbol sebolic addressing respectively.
By I symbol sebolic addressing and the Q symbol sebolic addressing that I/Q data integrate gatherer recovers, synchronously sent into quantizer, each I symbol and Q symbol is constantly done quantification treatment again.
I symbol sebolic addressing after the quantification and Q symbol sebolic addressing are sent to the first order pole iir filter and carry out filtering.The result of filtering output is respectively applied for the pulse density modulator control voltage that the pulse density modulator of adjusting the I passage is controlled voltage and Q passage.
At last, the density modulation pulse of the pulse density modulator of the pulse density modulator of I passage and Q passage output is respectively applied for adjustments, compensation, controls the DC bias voltage of the A/D converter of I passage and Q passage.
The i/q signal A/D conversion DC offset controller that the present invention proposes, that utilization receives, from the level of the original I/Q signal of analog baseband circuitry unit (A/D change-over circuit), calculate the DC biasing control voltage of A/D change-over circuit, thereby realize adjustment, compensation and control i/q signal A/D conversion DC bias voltage.In this DC offset controller, adopt the window index iir filter that time synchronized pilot tone I/Q symbol sebolic addressing is carried out filtering, improved accuracy and reliability to i/q signal A/D conversion DC bias voltage adjustment and compensate for estimated.The output of window index iir filter, be used to adjust the control voltage of the pulse density modulator of I passage and Q passage, thereby make the output of pulse density modulator of I passage and Q passage can accurately adjust, compensate, control i/q signal A/D conversion DC bias voltage.This i/q signal A/D conversion DC offset controller is simple in structure, complexity is little, computing cost is low, A/D changes DC biasing control reliability height, is easy to realization, practical, be very suitable for being embedded in the communication chip and realize with hardware mode, can be directly commercial.
What need understand is: though the foregoing description is to the present invention's detailed explanation of contrasting; but these explanations are just illustrative to the present invention; rather than limitation of the present invention, any innovation and creation that do not exceed in the connotation of the present invention all fall within the scope of protection of the present invention.
Claims (1)
1, a kind of i/q signal A/D conversion DC offset controller, it is characterized in that, this i/q signal A/D conversion DC offset controller is made of I/Q data integrate gatherer, I/Q symbol level quantizer, first order pole IIR filter, pulse density modulator, and the integration outside with it owed sampler, A/D converter is formed i/q signal A/D conversion DC biasing control loop; The annexation and the work of this i/q signal A/D conversion DC offset controller and i/q signal A/D conversion DC biasing control loop are:
Original I/Q data from the Analog Baseband system are owed sampler by integration, finish the short period integration, and the result that integration draws is constituted new sequence; Because new sequence is lower than the speed of original I/Q sequence, thereby is referred to as to owe sampled sequence; Integration is owed the output of sampler and is delivered to I/Q data integrate gatherer, and I/Q data integrate gatherer is finished processing procedures such as short period integration, sampling, maintenance, elimination respectively to i/q signal, synchronously recover I symbol sebolic addressing and Q symbol sebolic addressing respectively; By I symbol sebolic addressing and the Q symbol sebolic addressing that I/Q data integrate gatherer recovers, synchronously sent into quantizer, each I symbol and Q symbol is constantly done quantification treatment again; I symbol sebolic addressing and Q symbol sebolic addressing after the quantification are admitted to the first order pole IIR filter, adopt following formula to finish the filtering of first order pole window index infinite impulse response:
DC
i(k)＝(1-β)·DC
i(k-1)+β·D
i(k)
DC
q(k)＝(1-β)·DC
q(k-1)+β·D
q(k)
In the following formula, DC
i(k) be the pulse density modulator control contact potential series of I passage, DC
q(k) be the pulse density modulator control contact potential series of Q passage; K is D
iAnd D
qThe subscript of sequence; β is the forgetting factor of first order pole iir filter; D
iBe the original I sequence through integration owe to sample, integration collection, quantizing process and the new sequence that constitutes; D
qBe original Q sequence through integration owe to sample, integration collection, quantizing process and the new sequence that constitutes;
After finishing the filtering of first order pole window index infinite impulse response according to following formula, this i/q signal A/D conversion DC offset controller is with filtering DC as a result
i(k), DC
q(k) output to the pulse density modulator of I passage and the pulse density modulator of Q passage respectively, be used for adjusting respectively the pulse density modulator control voltage of I passage and the pulse density modulator control voltage of Q passage,
(1) pulse density modulator of adjusting the I passage is controlled voltage:
1) if DC
i(k)〉0, then the control voltage of the pulse density modulator of I passage is increased a voltage and adjust step delta c;
2) if DC
i(k)＜0, then the control voltage of the pulse density modulator of I passage is reduced by a voltage and adjust step delta c;
(2) pulse density modulator of adjusting the Q passage is controlled voltage:
1) if DC
q(k)〉0, then the control voltage of the pulse density modulator of Q passage is increased a voltage and adjust step delta c;
2) if DC
q(k)＜0, then the control voltage of the pulse density modulator of Q passage is reduced by a voltage and adjust step delta c;
The pulse density modulator of the pulse density modulator of I passage and Q passage utilizes said method, and the output density modulating pulse is respectively applied for the DC bias voltage of the A/D converter of adjustment, compensation, control I passage and Q passage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101027854A CN100505717C (en) | 2005-09-19 | 2005-09-19 | I/Q signal A/D conversion DC offset controller |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101027854A CN100505717C (en) | 2005-09-19 | 2005-09-19 | I/Q signal A/D conversion DC offset controller |
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| CN100505717C true CN100505717C (en) | 2009-06-24 |
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| CN103532633B (en) * | 2012-07-04 | 2016-03-30 | 富士通株式会社 | A kind of automatic bias control method for optical sender and device |
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