CN100485470C - Liquid crystal display device and method for manufacturing the same - Google Patents
Liquid crystal display device and method for manufacturing the same Download PDFInfo
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- CN100485470C CN100485470C CNB2006101541236A CN200610154123A CN100485470C CN 100485470 C CN100485470 C CN 100485470C CN B2006101541236 A CNB2006101541236 A CN B2006101541236A CN 200610154123 A CN200610154123 A CN 200610154123A CN 100485470 C CN100485470 C CN 100485470C
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Abstract
A liquid crystal display device (10) includes: a transparent substrate 11; a plurality of signal lines (17) and scan lines (16) arranged on the transparent substrate (11) in a matrix; a plurality of auxiliary capacitor lines (18) provided between the scan lines (16) so as to be in parallel with the scan lines (16); thin film transistors (TFTs) each provided in a vicinity of an intersection of the signal lines (17) and scan lines (16); and pixel electrodes (20) arranged in respective positions defined by the signal lines (17) and the scan lines 16 and each electrically connected to a drain electrode (D) of the thin film transistor (TFT); in which the thin film transistor (TFT)'s gate electrode (G) and the scan line (16) are covered by a gate insulating film formed by an insulating film (a first layer) (25) and an insulating layer (a second layer) (26), and the drain electrode D of the thin film transistor (TFT) extends to overlie an auxiliary capacitor electrode (18 a), with the insulating layer (the second layer) (26) interposed between the drain electrode (D) and the auxiliary capacitor electrode (18 a). As a result, it will be possible to provide a liquid crystal display device and a method for manufacturing the same are provided, in which the capacitance of an auxiliary capacitor electrode is increased without reducing the aperture ratio of each pixel and which is suitable to realize a relatively small pixel area and high definition.
Description
Technical field
The present invention relates to LCD and manufacture method thereof, in particular, the present invention relates to not reduce the aperture opening ratio of each pixel, and increase the electric capacity of auxiliary capacitance electrode, be suitable for less elemental area, and the LCD and the manufacture method thereof that more become more meticulous.
Background technology
In recent years, information communication device not only is even common electrical equipment adopts LCD more.LCD is made of substrate and liquid crystal layer, this substrate is formed by a pair of glass that forms electrode etc. from the teeth outwards etc., this liquid crystal layer is formed between the above-mentioned a pair of substrate, external pressure voltage on the electrode on the substrate, liquid crystal molecule is arranged once more, thus, can change the optical transmission rate, show various images.
Above-mentioned LCD has following structures, it is made of array substrate and color filter substrate, on the surface of this array substrate, be rectangular formation sweep trace and signal wire, passing through these two kinds wiring region surrounded, the thin film transistor (TFT) (Thin FilmTransistor:TFT) of the on-off element that formation is used as liquid crystal drive, pixel capacitors and the auxiliary capacitance line that is formed for the auxiliary capacitor of holding signal to liquid crystal applied voltage, on the surface of this color filter substrate, form red (R), green (G), the color filter of blue (B) and common electrode etc., between two substrates, encapsulated liquid crystals.
The auxiliary capacitance line that is formed on the array substrate is provided with for the auxiliary capacitor of maintenance during being formed on necessarily from the electric charge of signal wire signal supplied, auxiliary capacitor is by the following manner setting, this mode is: with the drain electrode of this auxiliary capacitance line and TFT, even the part of pixel capacitors is as electrode, the gate insulating film that covers the grid of TFT is a dielectric, forms capacitor.In addition, this auxiliary capacitance line is generally formed by the conductive component that is in the light of aluminium, molybdenum or chromium etc.
But, from the cross (talk) that prevents LCD or the viewpoint of flicker, must increase the electric capacity of this auxiliary capacitor, still, follow technical renovation in recent years, the miniaturization processing of LCD, high Precision Processing make progress, and thus, corresponding pixel size diminishes, like this, if consider the aperture opening ratio of each pixel,, then in fact be difficult to overstriking auxiliary capacitance line itself for auxiliary capacitor is big.
Below by Fig. 9, to the scheme that solves above-mentioned such problem, the array substrate 70 of following patent documentation 1 disclosed LCD is described.In addition, Fig. 9 A is the planimetric map of array substrate, and Fig. 9 B is the cut-open view along the IXB among Fig. 9 A-IXB line.
In the array substrate 70 of this LCD, as shown in Fig. 9 A and Fig. 9 B, on transparent dielectric substrate 71, form sweep trace 72, auxiliary capacitance line 73 and rectangular auxiliary capacitor pattern 74 that the conductive layer by aluminium, chromium, molybdenum, chromium nitride, molybdenum nitride or their alloy etc. forms.Sweep trace 72 is connected with the grid G of thin film transistor (TFT) TFT, and auxiliary capacitor pattern 74 is connected with auxiliary capacitance line 73.
On dielectric substrate 71, form by silicon nitride or the such megohmite insulant of monox, thickness exists
Scope in gate insulating film 75 cover sweep trace 72, auxiliary capacitance line 73 and auxiliary capacitor patterns 74.On gate insulating film 75, form semiconductor pattern 76, this semiconductor pattern 76 overlaps with grid G, is formed by uncrystalline silicon etc.On the part and gate insulating film 75 of semiconductor pattern 76, form the signal wire 77 and the auxiliary capacitor that form by conductive materials and use pattern 78 with conducting electricity.Signal wire 77 extends longitudinally, the source S of double as TFT.
Auxiliary capacitor is island with conductive pattern 78 and is formed on one deck identical with such signal wire 77,, overlaps the formation auxiliary capacitor by gate insulating film 75 with the auxiliary capacitor pattern 74 that is positioned at the bottom.At this moment, auxiliary capacitor is electrically connected with pixel capacitors 79 described later with conductive pattern 78.
In addition, formed by silicon nitride or the such megohmite insulant of monox, thickness is 500～2000
Scope in protection dielectric film 80 cover such signal wire 77, auxiliary capacitor with conductive pattern 78 and semiconductor pattern 76.On this protection dielectric film 80, at the top of drain D, form contact hole 81, at the top of auxiliary capacitor conductive pattern 78, opening 82 is set.In addition; on protection dielectric film 80; form pixel capacitors 79; by contact hole 81, pixel capacitors 79 and drain D are electrically connected, and by opening 82; auxiliary capacitor is connected with pixel capacitors 79 with conductive pattern 78; consequently, auxiliary capacitor passes through pixel capacitors 79 with conductive pattern 78 and drain D, realizes being electrically connected.This pixel capacitors 79 is formed by ITO (Indium Tin Oxide) or the such electrically conducting transparent material of IZO (IndiumZinc Oxide).
In above-mentioned prior art; pixel capacitors 79 overlaps with conductive pattern 79 with auxiliary capacitance line 73 and auxiliary capacitor, still, and between pixel capacitors 79 and auxiliary capacitance line 73; protection dielectric film 80 and gate insulating film 75 are set; form auxiliary capacitor, in addition, pixel capacitors 79 is electrically connected with conductive pattern 78 with auxiliary capacitor; but; auxiliary capacitor is with between conductive pattern 78 and the auxiliary capacitor pattern 74, is separated with gate insulating film 75, forms another auxiliary capacitor.In this occasion, because it is little with the thickness of the gate insulating film 75 between conductive pattern 78 and the auxiliary capacitor pattern 74 between auxiliary capacitor, so overlap with pixel capacitors 79 with auxiliary capacitor pattern 74, the occasion that forms auxiliary capacitor is compared, even have identical overlapping area, still can guarantee bigger electrostatic capacitance.So, in following patent documentation 1, in the disclosed LCD,, contrast aperture opening ratio so can improve electrostatic capacitance even, still can increase electrostatic capacitance owing at the area that does not enlarge auxiliary capacitor pattern 74 and auxiliary capacitance line 73.
But, in the array substrate 70 in following patent documentation 1 in the disclosed LCD, electrostatic capacitance (auxiliary capacitor) is electrode with auxiliary capacitor with conductive pattern 78 and auxiliary capacitor pattern 74, with the gate insulating film 78 that is arranged at therebetween is dielectric, the thickness of this gate insulating film 75 is less, yet, even like this, owing to also have the thickness of this gate insulating film 75 2500～4500
Scope in situation, so, still have to increase the area of the auxiliary capacitor pattern 74 that the conductive materials by being in the light property forms in order to ensure the bad auxiliary capacitor of demonstration that is enough to suppress cross (talk) or flicker etc.Promptly, in the array substrate 70 in following patent documentation 1 in the disclosed LCD, in order to increase electrostatic capacitance, the mode of thickness that also can be by reducing gate insulating film 75 realizes, but, if further reduce the thickness of gate insulating film 75 itself, then be difficult to keep by the grid G of gate insulating film 75 coverings and the electrical insulating property between sweep trace 72 and other the parts.
In addition, by Figure 10 and Figure 11, to the scheme of the bigger auxiliary capacitor of conduct acquisition capacity, the array substrate of disclosed LCD 90 is described in the patent documentation 2 below.In addition, Figure 10 is the planimetric map of several pixels of disclosed array substrate in the following patent documentation 2.Figure 11 A～Figure 11 G is the phantom view of the manufacturing step of the array substrate of representing Figure 10 successively.At first, on the insulativity substrate 91 that forms by glass plate, the auxiliary capacitance line 92 that is formed by ITO (Indium Tin Oxide) is carried out pattern-making handle.Then, form grid metal film 93, carry out pattern-making and handle (Figure 11 A).
In addition, by modes such as plasma CVDs, form by SiN continuously
xOr SiO
xThe gate insulating film 94 that forms; As active layer such as, the noncrystalline semiconductor film 95 that forms by a-Si, by being mixed with impurity, such as, n
+The film formed resistive contact of a-Si semiconductor film 96 (Figure 11 B).At this moment, the thickness X of gate insulating film is enough big, in case the short circuit between the leak-stopping utmost point and the grid, between source electrode and the grid, such as, it is set at X=4000
Then, by identical resist, according to pattern, contact is carried out etching (Figure 11 C) with semiconductor film 96 and noncrystalline semiconductor film 95 to resistive.Then, to auxiliary capacitance line 92, with pixel capacitors 97 superposed part that form in the back step as patterns of openings (dotted portion of Figure 10) and residual resist (not shown in Figure 11) applies, etchant by gate insulating film 94 usefulness, carry out etch processes, so that auxiliary capacitor is reduced to required thickness Y=2000 with the thickness of dielectric film
(Figure 11 D).
Below the pixel capacitors 97 that is formed by ITO is carried out pattern-making and handle (Figure 11 E).In addition, if form drain electrode, source electrode metal film 98, carry out pattern-making and handle (Figure 11 F), contact is carried out etch processes with semiconductor film 96 and with its removal, is then made LCD array substrate (Figure 11 G) to the resistive on the groove that residues in TFT.The array substrate that will obtain by such structure, opposed by liquid crystal material with the common electrode substrate, thus, obtain LCD 90.
In above-mentioned prior art, auxiliary capacitance line 92 and pixel capacitors 97 are equivalent to the electrode of capacitor, gate insulating film 94 between auxiliary capacitance line 92 and pixel capacitors 97 is equivalent to the dielectric of capacitor, but because the thickness of the gate insulating film 94 on the relative grid 93
Situation, the thickness of the dielectric film on the auxiliary capacitance line 92
Historical facts or anecdotes now drain and grid between, the short circuit between source electrode and the grid is difficult to produce, even and do not enlarge the area of auxiliary capacitance line 92, still can guarantee the effect of necessary auxiliary capacitor.
Patent documentation 1:JP speciallys permit 2005-No. 506575 documents (Fig. 8, Fig. 9, paragraph 0069～0085)
Patent documentation 2:JP specially permit No. 2584290 document (claim ,～the 3 page of the 5th hurdle of the 30th row, the 2nd page of the 4th hurdle the 17th row, Fig. 1, Fig. 2)
Summary of the invention
Technical matters:
In above-mentioned patent documentation 1 in the array substrate of disclosed LCD 70, in order to ensure being enough to suppress to show bad auxiliary capacitor, still necessarily require the auxiliary capacitor pattern of bigger area, aperture opening ratio reduces, in addition, because in pixel inside, have as being in the light property parts, TFT and auxiliary capacitor are with conductive pattern 78, so aperture opening ratio further reduces.In addition, in above-mentioned patent documentation 2 in the array substrate of disclosed LCD 90, only reduce the thickness of gate insulating film on the surface of auxiliary capacitance line partly by etching mode, at the grid that keeps covering and the state of the electrical insulating property between sweep trace and other the parts by gate insulating film, increase auxiliary capacitor, but, be difficult to reduce partly the thickness of the gate insulating film of auxiliary capacitance line, obtain the control of the etch quantity that required thickness uses, be difficult to keep the film thickness uniformity of gate insulating film of the auxiliary capacitance line of each LCD.
In addition, in above-mentioned patent documentation 2 in the array substrate of disclosed LCD 90, on the insulativity substrate 91 that forms by glass plate, the auxiliary capacitance line 92 that is formed by ITO is carried out pattern-making to be handled, then, grid metal film 93 is carried out pattern-making to be handled, thus, form sweep trace and grid, increase man-hour like this, so, manufacturing efficient reduces, and must consider mask dislocation etc., increase pixel capacitors 97 and the source electrode distance between the metal film 98, can not on the part of TFT, pixel capacitors be set, like this, aperture opening ratio reduces, so, be difficult to adopt less elemental area in recent years, even carry out the auxiliary capacitor that the LCD of high Precision Processing uses and form mechanism.
The inventor is at the problems referred to above, following auxiliary capacity is formed mechanism carried out various analyses, should form the capacitor of auxiliary capacity of efficient mechanism forms to(for) further raising by auxiliary capacity, and particularly do not cause the increase in man-hour, in addition, aperture opening ratio is big, less elemental area, and the LCD that more becomes more meticulous, all can use effectively, consequently find, if for the capacitor that constitute to form this auxiliary capacitor in the paired electrode of the auxiliary capacitance line of an electrode use according to the mode that the drain electrode that makes TFT prolongs, and further shorten distance between auxiliary capacitance line and the drain electrode, then replace marginal gate insulating film, establish the insulation course of its thickness and be situated between less than gate insulating film, then particularly do not cause the increase in man-hour, aperture opening ratio reduces, and can increase the electric capacity of auxiliary capacitor, thus, finished the present invention.
That is, the object of the present invention is to provide the aperture opening ratio that does not reduce each pixel, can suppress cross (talk) in addition, flicker wait to show bad, has little elemental area or the LCD and the manufacture method thereof of the pixel that more becomes more meticulous.
Technical scheme:
In order to realize the 1st purpose of the present invention, LCD of the present invention is included in many signal wires and the sweep trace that is rectangular setting on the transparent substrates; Many auxiliary capacitance lines that between above-mentioned sweep trace, are provided with abreast; Thin film transistor (TFT), this thin film transistor (TFT) are arranged near the intersection point of above-mentioned signal wire and sweep trace; Pixel capacitors, this pixel capacitors are arranged at the relevant position of dividing by above-mentioned signal wire and sweep trace, and are electrically connected with the drain electrode of above-mentioned thin film transistor (TFT), it is characterized in that:
The grid of above-mentioned thin film transistor (TFT) and above-mentioned sweep trace cover by gate insulating film, and on above-mentioned auxiliary capacitance line, folder is established the insulation course of its thickness less than the thickness of above-mentioned gate insulating film, is extended with the drain electrode of above-mentioned thin film transistor (TFT).
In addition, the present invention relates to above-mentioned LCD, it is characterized in that above-mentioned gate insulating film is made of sandwich construction, above-mentioned insulation course is made of one deck at least wherein.
In addition, the present invention relates to above-mentioned LCD, it is characterized in that above-mentioned insulation course is to be formed in the multilayer that constitutes above-mentioned gate insulating film the one deck on the outermost side.
Also have, the present invention relates to above-mentioned LCD, it is characterized in that above-mentioned insulation course is the one deck on the most close transparent substrates side that is formed in the multilayer that constitutes above-mentioned gate insulating film.
Have again, the present invention relates to above-mentioned LCD, it is characterized in that above-mentioned insulation course is made of the thinnest layer in the multilayer that constitutes above-mentioned gate insulating film.
In addition, the present invention relates to above-mentioned LCD, it is characterized in that the edge of thin part of the insulation course on the above-mentioned auxiliary capacitance line is positioned at the inboard at the edge of auxiliary capacitance line.
In addition, the present invention relates to above-mentioned LCD, the thickness that it is characterized in that above-mentioned gate insulating film is 2500～5500
Scope in, the thickness of above-mentioned insulation course is 500～1500
Scope in.
Also have, the present invention relates to above-mentioned LCD, it is characterized in that between above-mentioned pixel capacitors and above-mentioned drain electrode, form interlayer dielectric, in above-mentioned interlayer dielectric, be positioned at part on the auxiliary capacitance line, form contact hole, by contact hole, above-mentioned pixel capacitors and drain electrode are electrically connected.
Have again, the present invention relates to above-mentioned LCD, it is characterized in that the surface or the back side, on above-mentioned thin film transistor (TFT) and auxiliary capacitance line, or form reflectance coating according to the mode that covers with the whole zone of the corresponding position of above-mentioned pixel capacitors in above-mentioned pixel capacitors.
In addition, in order to realize the 2nd purpose of the present invention, the invention of the manufacture method of LCD of the present invention is characterised in that this method comprises the steps:
On transparent substrates, many sweep traces that are connected with grid and auxiliary capacitance line are set according to the mode that is parallel to each other;
Form gate insulating film according to whole the mode that covers on the above-mentioned transparent substrates;
The part that is positioned on the auxiliary capacitance line in the above-mentioned gate insulating film is carried out the filming processing, form its thickness less than the insulation course around the above-mentioned auxiliary capacitance line;
Above above-mentioned gate insulating film, form the drain electrode of thin film transistor (TFT), and the formation auxiliary capacitor is extended in the drain electrode of this thin film transistor (TFT) according to the mode that covers the insulation course on the above-mentioned auxiliary capacitance line;
In addition, the present invention relates to the manufacture method of above-mentioned LCD, it is characterized in that:
The step that forms above-mentioned insulation course comprises the steps:
On above-mentioned gate insulating film, form semiconductor layer;
On the surface of above-mentioned semiconductor layer, apply photoresist;
Adopt half-tone (half-tone) mask, remove the photoetch agent of the auxiliary capacitor formation portion on the above-mentioned auxiliary capacitance line, with the corresponding position of grid, residual thicker photoetch agent, in other part, residual thin photoetch agent;
By etching, remove after the semiconductor layer of the auxiliary capacitor formation portion of exposing, remove the part of the gate insulating film that is positioned at above-mentioned auxiliary capacitor formation portion in addition, form its thickness less than around the insulation course of gate insulating film;
Remove above-mentioned thin photoetch agent, only with the corresponding position of above-mentioned grid, residual light resist;
By etching, remove the semiconductor layer that exposes to the open air;
Remove residual photoetch agent.
Also have, the present invention relates to the manufacture method of above-mentioned LCD, it is characterized in that the step that forms above-mentioned insulation course comprises the steps: several times, form above-mentioned gate insulating film according to a plurality of layers; Remove the one deck at least in it.
Have again, the present invention relates to the manufacture method of above-mentioned LCD, it is characterized in that the step that forms above-mentioned insulation course comprises removal several times, the step of the initial layer that forms when forming above-mentioned gate insulating film by multilayer.
In addition, the present invention relates to the manufacture method of above-mentioned LCD, it is characterized in that the step that forms above-mentioned insulation course comprises removal several times, the step of the last layer that forms when forming above-mentioned gate insulating film according to multilayer.
In addition, the present invention relates to the manufacture method of above-mentioned LCD, it is characterized in that at each layer, changing the mode of underlayer temperature, form the gate insulating film in the above-mentioned sandwich construction by adopting same material.
Have again, the present invention relates to the manufacture method of above-mentioned LCD, it is characterized in that above-mentioned underlayer temperature is the highest when the formation of initial gate electrode film, when forming another gate insulating film, reduce successively.
In addition, the present invention relates to the manufacture method of above-mentioned LCD, the gate insulating film that it is characterized in that above-mentioned sandwich construction is by adopting same material, and at each layer, the mode of the composition of the atmosphere gas around changing forms.
In addition, the present invention relates to the manufacture method of above-mentioned LCD, it is characterized in that this method comprises the steps:
Form the step of interlayer dielectric according to the mode that covers above-mentioned drain electrode;
On above-mentioned interlayer dielectric, the position in above-mentioned drain electrode and the coincidence of additional reservoir line forms contact hole;
On above-mentioned interlayer dielectric, according to passing through contact hole, the mode that is electrically connected with above-mentioned drain electrode forms pixel capacitors.
Also have, the present invention relates to the manufacture method of above-mentioned LCD, it is characterized in that it comprises the steps: before or after the formation of above-mentioned pixel capacitors, with above-mentioned thin film transistor (TFT) and the corresponding position of auxiliary capacitance line, or with whole of the corresponding position of above-mentioned pixel capacitors on, form reflecting plate.
Beneficial effect:
The present invention has such scheme, thus, realizes such good effect given below.Promptly, according to LCD of the present invention, setting is by the insulation course of a part as the gate insulating film of the lip-deep sandwich construction of a part of being located at auxiliary capacitance line, the drain electrode that is connected with pixel capacitors, but, because the thickness of this insulation course is less than the thickness of the gate insulating film on every side that covers auxiliary capacitance line, this insulation course forms the dielectric layer of auxiliary capacitor, so can significantly increase auxiliary capacitor, so, can obtain under the situation of the area that does not increase auxiliary capacitance line, suppress cross (talk), the LCD of the demonstration bad phenomenon of flicker etc.
That is, in order to ensure the insulativity of original interlayer, gate insulating film is in the scope of transparent substrates integral body, with the homogeneous thickness setting, still, particularly on the grid of an end that constitutes TFT, the electrostatic withstand voltage that keeps TFT can not reduce the thickness of gate insulating film.Yet, as LCD of the present invention, because by on the surface of auxiliary capacitance line, than the insulation course of unfertile land formation as the part of the gate insulating film of sandwich construction, can under the situation of the thickness that does not reduce gate insulating film, reduce the thickness of the insulation course on the auxiliary capacitance line, so can be not to other structure, cause under the situation of any adverse effect, realize above-mentioned effect.In addition since can be only by prolonging drain electrode, form auxiliary capacity, thus auxiliary capacity that can being in the light property of good efficiency setting, the aperture opening ratio raising.
In addition, according to LCD of the present invention, when forming the gate insulating film of sandwich construction, if the insulation course on the above-mentioned auxiliary capacitance line is by the one deck that is formed in the multilayer, that is, the layer on the outermost side of gate insulating film, or the layer that is formed on the most close transparent substrates side constitutes, then such as, each of gate insulating film layer different material of employing etching characteristic by etch processes, only removed layer not, thus, can form above-mentioned thin insulation course easily.In addition, if be the thinnest layer in each layer in the gate insulating film, then can increase the electric capacity of auxiliary capacitor easily as the layer of this insulation course.
In addition, according to LCD of the present invention, because the edge of thin part of the insulation course on the auxiliary capacitance line is positioned at the inboard at the edge of auxiliary capacitance line, so can be between the top electrode and sweep trace that constitute auxiliary capacitor, obtain sufficient spacing, in addition, can guarantee to constitute near the top electrode of the auxiliary capacitor the edge of auxiliary capacitance line and the electrostatic withstand voltage of bottom electrode, simultaneously, increase the capacity of auxiliary capacitor.
Also have, according to LCD of the present invention, owing to guarantee that the thickness of gate insulating film exists
Scope in the wall thickness that does not damage insulativity, and the thickness of insulation course reduce and
Scope in, so can increase the electric capacity of capacitor.In addition, the thickness of gate insulating film particularly is preferably in
More than, the thickness of insulation course particularly is preferably
About.
Have again, according to LCD of the present invention, after by the various wirings that are formed with sweep trace, signal wire and thin film transistor (TFT) etc., by interlayer dielectric, cover these wirings, still, because pixel capacitors is arranged on the surface of this interlayer film, so the surface is smooth.Thus, can make the box gap of LCD even, obtain the good LCD of display quality.In addition, because pixel capacitors is by being arranged at the contact hole on the auxiliary capacitance line, with the drain electrode conducting, even so under the situation different of the box gap on this contact hole with box gap on every side, in the part of this contact hole,, block light from back of the body illuminator by the drain electrode of being in the light property, therefore, can not cause adverse effect to display quality.
In addition, according to LCD of the present invention, if with the thin film transistor (TFT) and the corresponding position of auxiliary capacitance line and the surface or the back side of pixel capacitors on, reflecting plate is set, then can form the LCD of Semitransmissive simply, in addition, if reflecting plate is set, then can form the LCD of reflection-type simply according to the mode in the whole zone at the surface that covers pixel capacitors or the back side.
In addition, manufacture method according to LCD of the present invention, not only can make the LCD of the effect that realizes foregoing invention easily, and owing to form the gate insulating film and the semiconductor layer of sandwich construction successively continuously, if with after the formation of carrying out gate insulating film and etching step, the method that forms the film of semiconductor layer is compared, then can with substrate around from atmospheric pressure state, the step that remains on vacuum state reduces 1 time, and owing to be difficult to be subjected to the influence of the pollution that the etching step at gate insulating film produces, so the minimizing of the situation of the characteristic variation of TFT.
Also have, manufacture method according to LCD of the present invention, because when forming the gate insulating film of sandwich construction, removal is formed at the one deck in a plurality of insulation courses on the above-mentioned auxiliary capacitance line, promptly, the layer of the initial formation in the gate insulating film, or the last layer that forms are so can form the insulation course of its thickness less than gate insulating film simply.
Have again, according to the manufacture method of LCD of the present invention, because the gate insulating film of sandwich construction forms by following manner, this mode is: adopt same material, at every layer, change underlayer temperature, so atmosphere around not changing, only by changing underlayer temperature, just can form form identical in fact respectively, but the gate insulating film of the different sandwich construction of rerum natura, in addition, utilize the difference of rerum natura, by etching, can be easily the insulation course on the surface of residual auxiliary capacitance line only.So, when forming the gate insulating film of multilayer, owing to also can carry out etch processes not to each film, thus not only can avoid the pollution on the surface of each film, and can form the insulation course and the gate insulating film of regulation in the short period.In this occasion, the gate insulator film formation material can adopt silicon nitride, monox.
In addition, manufacture method according to LCD of the present invention, the gate insulating film of sandwich construction can form by following manner, this mode is: adopt same material, and at every layer, the composition of the atmosphere gas around changing, in addition, can utilize difference based on the rerum natura of the difference of this composition, by etching, the insulation course on the surface of residual auxiliary capacitance line only.So, when forming the gate insulating film of multilayer, owing to also can carry out etch processes not to each film, thus not only avoid the pollution on the surface of each film, and, can form insulation course and the gate insulating film of stipulating in the short period.The gate insulating film of the sandwich construction that is formed by the different films of forming is preferably formed by silicon nitride and monox, and in addition, particularly preferably top layer is formed by silicon nitride.
Description of drawings:
Fig. 1 amplifies the part of a pixel of the LCD that is equivalent to embodiment 1, represents the planimetric map of color filter substrate with perspective fashion;
Fig. 2 is the LCD of presentation graphs 1, along the side sectional view of II-state that the II line is cut open;
Fig. 3 A～Fig. 3 G is the cut-open view of the manufacturing step of the array substrate of expression shop drawings 1;
Fig. 4 A～Fig. 4 E is that expression is right after Fig. 3 G, the cut-open view of the manufacturing step of the array substrate of shop drawings 1;
Fig. 5 A～Fig. 5 E is the cut-open view of the manufacturing step of the array substrate of expression manufacturing embodiment 2;
Fig. 6 A～Fig. 6 D represents to be right after Fig. 5 E's, makes the cut-open view of manufacturing step of the array substrate of embodiment 2;
Fig. 7 A～Fig. 7 F represents the cut-open view of manufacturing step of the array substrate of embodiment 3;
Fig. 8 A～Fig. 8 E represents to be right after Fig. 7 F's, makes the cut-open view of manufacturing step of the array substrate of embodiment 3;
Fig. 9 A is the planimetric map of the array substrate of the 1st existing example, and Fig. 9 B is the cut-open view along the IXB-IXB among Fig. 9 A;
Figure 10 is the planimetric map of several pixels of the array substrate of the 2nd existing example;
Figure 11 A～Figure 11 G is the cut-open view of the manufacturing step of the array substrate of representing Figure 10 successively.
The explanation of label:
Label 25 ' expression dielectric film;
Label 26 ' expression insulation course;
Film between label 29 presentation layers;
Embodiment
With reference to the accompanying drawings, preferred embodiment of the present invention is described.But, embodiment given below provides the LCD that is used for specific implementation technical conceive of the present invention and the example of manufacture method thereof, do not plan the present invention is specified in this LCD and manufacture method thereof, the present invention can be equal to other the embodiment that comprises in requiring of ground application rights.In addition, to as the LCD of embodiment given below, the LCD of transmission-type is described, and still, obviously, LCD of the present invention is not limited to transmission-type, also can be applicable to the LCD of semitransparent type or reflection-type.
Embodiment 1
Fig. 1 amplifies the part of a pixel of the LCD that is equivalent to embodiment 1, the substrate of representing other with perspective fashion, such as, the planimetric map of color filter substrate, Fig. 2 is the LCD of presentation graphs 1, along the side sectional view of II-state that the II line is cut open, Fig. 3 and Fig. 4 represent the cut-open view of manufacturing step of array substrate of the LCD of shop drawings 1.In addition, Fig. 3 and Fig. 4 all represent along the state of the II among Fig. 1-section that the II line is cut open.
The LCD 10 of present embodiment 1 is made by following manner, this mode is: by encapsulant (diagram is omitted), will be by in the transparent substrates 11 that forms by glass etc., forming the array substrate 13 of various wirings etc. and the surperficial peripheral part of a pair of substrate that color filter substrate 14 forms on 12 fits, liquid crystal 15 injects in portion within it.
(inner face side) forms various wirings etc. on array substrate 13 and color filter substrate 14 respectively, on the array substrate 13 therein, is provided with the many sweep traces 16 and the signal wire 17 that are rectangular; Many auxiliary capacitance lines 18, these many auxiliary capacitance lines 18 are arranged between a plurality of sweep traces 16, and are parallel with this sweep trace 16; Thin film transistor (TFT) TFT, this thin film transistor (TFT) TFT is made of source S, grid G, drain D, semiconductor layer 19; Pixel capacitors 20, this pixel capacitors 20 covers by sweep trace 16 and signal wire 17 region surrounded.In addition, usually adopt as the semiconductor layer 19 of TFT, and many silicon (polysilicone) (p-Si) or uncrystalline silicon (a-Si), but be not limited to this, can be active component.
On color filter substrate 14, be provided with black matrix 21 usually, this black matrix 21 is rectangular setting corresponding to the pixel area of array substrate 13; The color filter 22 of red (R), green (G), blue (B) etc., this color filter 22 is arranged at by above-mentioned black matrix 21 region surrounded; Public electrode 23, this public electrode 23 is provided with according to the mode that covers the color filter that is electrically connected with the electrode of array substrate side.But the present invention is not limited to this, in the occasion of lateral electric field type, also have the situation that does not have public electrode,, then also have the situation that does not have color filter if be white black demonstration, in the occasion that the colour of color compensating type shows, also have and be not trichromatic, situation about constituting by multiple color filter.
In addition,, a plurality of distance pieces etc. are set as required by array substrate 13 and color filter substrate 14, sealant region surrounded, and encapsulated liquid crystals 15, these a plurality of distance pieces are used to make the spacing of substrate even.
Below with reference to Fig. 3 and Fig. 4, provide the manufacturing step of the array substrate of above-mentioned LCD.
At first, as shown in Fig. 3 A, on transparent substrates 11, form the conductive layer 24 that aluminium, molybdenum, chromium or their alloy by specific thickness form.In addition,, adopt known photoetching process, carry out pattern-making and handle, thus, remove its part, form along the many sweep traces 16 of horizontal expansion, auxiliary capacitance line 18 between these a plurality of sweep traces 16 by etching mode as shown in Figure 3.In addition, in Fig. 3 B, the amplitude that the part by the grid G that will extend from sweep trace 16 and auxiliary capacitance line 18 is shown enlarges the auxiliary capacitance electrode 18a that forms.In addition, sweep trace 16 shown here and auxiliary capacitance line 18 illustrate as the wiring of the sandwich construction that is formed by aluminium and molybdenum.In this occasion, though have the little advantage of the resistance value of aluminium,, in contrast, owing to have an easy corrosion, with the shortcoming of the big grade of contact resistance of ITO, so, can improve such shortcoming by the sandwich construction of formation by the molybdenum aluminium coating.
Then, by above-mentioned steps, the mode that is formed with the transparency electrode 11 of sweep trace 16 and auxiliary capacitance line 18 according to covering forms the 1st layer dielectric film 25 of specific thickness.The 1st layer dielectric film 25 adopts the transparent resin material that is formed by silicon nitride etc.In addition, because the thickness of the 1st layer insulation course 25 is relevant with the insulativity of sweep trace 16 and grid G, so best, this thickness is 2500～5500
Scope in, particularly preferably can be 2800
More than.In addition, if form the 1st layer dielectric film 25, then as shown in Fig. 3 D, by etching mode, the part that only will be positioned on the 1st layer the auxiliary capacitance electrode 18a of dielectric film 25 is removed, and forms window portion 27.
In addition, after above-mentioned steps is finished,, form the 2nd layer thin dielectric film 26 of dielectric film 25 than the 1st layer according to the mode that covers transparent substrates 11 as shown in Fig. 3 E.Because the 2nd layer dielectric film 26 is formed at the 1st layer dielectric film 25 and get rid of by above-mentioned etching on the 1st layer the auxiliary capacitance electrode 18a of dielectric film 25, so sweep trace 16 and grid G are by the 1st layer dielectric film 25 and dielectric film 26 the two coverings of the 2nd layer, by 2 tunics, constitute gate insulating film.In addition, auxiliary capacitance electrode 18a only passes through the 2nd layer dielectric film 26 coverings.In addition, the material of the 2nd layer dielectric film 26 both can be and the 1st layer dielectric film 25 identical materials,, by the material that silicon nitride forms, also can be other dielectric film that is, such as, monox etc.The dielectric film 25 of its thickness than the 1st layer is thin, best, 500～1500
Scope in, particularly be preferably in 1000
About, such as, 800～1200
Scope in.
For such structure, its purpose is at the mode identical with gate insulating film, on main of the auxiliary capacitance electrode 18a of auxiliary capacitance line, formation is less than the thickness of grid part, that is, and and the dielectric film of the thickness around the auxiliary capacitance line, thus, also consider to form especially the 2nd layer dielectric film 26, still, gate insulating film can be such as, 2～5 layers sandwich construction, insulation course is made of wherein 1 layer at least, is that effectively the quality of film is good like this.In this occasion, also can change etching characteristic by changing the processing such as quality of film, adopt gate insulating film to form one deck of the bottom wherein as sandwich construction.Best, adopt following effective and efficient manner, that is, form the 1st layer of aforesaid thickness, by etching, it is removed processing, until electrode surface, form the insulation course that is formed by film thereon, thus, insulation course is the one deck that is formed on the face side of gate insulating film.Thus, insulation course can be made of the thinnest layer in the multilayer that constitutes gate insulating film, can further increase auxiliary capacitor.
Then, as shown in Fig. 3 F, on the 2nd layer insulation course 26, according to 1800
Thickness, form silicon layer, such as, the film of a-Si.In addition, as shown in Fig. 3 G, the part of residual cover gate G by etching, is removed a-Si layer, forms the semiconductor layer 19 of a part that constitutes TFT.Then,,, on transparent substrates 11, form the film of conductive materials, to along the many signal wires 17 that extend with the perpendicular direction of sweep trace 16 as shown in Fig. 4 A by identical mode; Extend the source S that is connected with semiconductor layer 19 from this signal wire 17; Cover auxiliary capacitance electrode 18a, and the drain D that an end is connected with semiconductor layer 19 is carried out the pattern-making processing.Thus, near the cross part of the sweep trace 16 of transparent substrates 11 and signal wire 17, form the TFT that constitutes on-off element.
Then; as shown in Fig. 4 B; according to the mode that covers various wirings; on transparent substrates 11, be formed for surface-stable, the protection dielectric film 28 that forms by inorganic insulating material, then; as shown in Fig. 4 C; film 29 between cambium layer, and this interlayer film 29 is used to make having an even surface of array substrate 13, is formed by organic insulation.In addition, be positioned at part on the auxiliary capacitance electrode 18a in this interlayer film 29, offer the hole, this hole forms and is used for contact hole 30 that pixel capacitors 20 described later and drain D are electrically connected, and still, the position in this hole is not limited on the auxiliary capacitance electrode 18a.Owing to forming LCD 10, when fitting with color filter substrate 14, the substrate spacing of part that is formed with contact hole 30 is different with other part, so have the danger that produces surface quality difference, like this, best, be arranged on the auxiliary capacitance electrode 18a as being in the light property material.In addition; as shown in Fig. 4 D; expose in the hole of removal from be formed at interlayer film 29; after the protection dielectric film 28 that forms by inorganic insulating material; at last, as shown in Fig. 4 E, at 1 pixel area that centers on by sweep trace 16 and signal wire 17; formation is by the pixel capacitors 20 that forms such as, ITO (IndiumTin Oxide).At this moment, best, be positioned on sweep trace 16 and the signal wire 17 according to its part, and the mode that the pixel capacitors 20 of adjacency is in contactless state is provided with.By above step, manufacturing array substrate 13.
The auxiliary capacitor of the array substrate 13 that forms by the above-mentioned manufacture method drain D that to be electrode be connected with pixel capacitors 20 with auxiliary capacitance electrode 18a is to be 1000 as thickness by dielectric
The capacitor arrangement of the 2nd layer insulation course 26 constitute.So because as prior art, dielectric is a thickness less than 2500～4500
Scope in the dielectric film of gate insulating film, so can increase capacitor volume significantly.In addition and since grid G and sweep trace 16 by the 1st layer dielectric film 25 and the laminated body of the 2nd layer dielectric film 26 cover, so guarantee its insulativity.
In addition, can reduce to constitute the electrode part of auxiliary capacitor, can improve the aperture opening ratio of pixel by increasing condenser capacity.In addition because the drain electrode double as constitutes the electrode of auxiliary capacitor, so with the drain D of the electrode that is provided as auxiliary capacitor beyond, the occasion of special electrode (conductive layer) is compared, and can reduce the interior part that is in the light of pixel, can further improve aperture opening ratio.
In order to increase the capacity of auxiliary capacitor, can form whole part of auxiliary capacitor, reduce the thickness of dielectric film.In the present embodiment, owing to, reduce the thickness of the dielectric film of auxiliary capacitor part, so in order to increase electric capacity, the part of insulation course 25 that can make the 1st layer of removal is greater than auxiliary capacitance electrode 18a by removing the 1st layer dielectric film 25 partly.That is, the edge of the window portion 27 of the 1st layer dielectric film 25 can be positioned at the outside at the edge of auxiliary capacitance electrode 18a.But in the occasion of the electrode of drain D double as auxiliary capacitor, auxiliary capacitor is provided with near sweep trace 16.Thus, if reduce the thickness of dielectric film, until the outside of auxiliary capacitor part, the spacing that then has the top electrode (drain D) of auxiliary capacitor and sweep trace 16 is too approaching, the problem of stray capacitance etc.So, occasion at the top electrode of drain electrode double as auxiliary capacitor, in the spacing of top electrode that enlarges auxiliary capacitor and sweep trace 16, must reduce the thickness of the dielectric film of auxiliary capacitor part, the edge of thin part of dielectric film is positioned at the inboard at the edge of auxiliary capacitance electrode 18a.In addition, owing to be formed near the edge of the auxiliary capacitance electrode 18a in the dielectric film on the auxiliary capacitance electrode 18a thickness easily less than other part, so can make near the thickness of the thickness of the dielectric film in the edge of auxiliary capacitance electrode 18a greater than near the dielectric film the pars intermedia of auxiliary capacitance electrode 18a, so that also guarantee near the edge of auxiliary capacitance electrode 18a the electrostatic withstand voltage of auxiliary capacitance electrode 18a and top electrode.In the present embodiment, the edge of the part (window portion 27) by making the dielectric film 25 of removing the 1st layer is positioned at the inboard of auxiliary capacitance electrode 18a, between the sweep trace 16 of the top electrode (drain D) of itself and auxiliary capacitor, obtain sufficient spacing, and guarantee the electrostatic withstand voltage of top electrode and auxiliary capacitance electrode.
In the present embodiment, method as the dielectric film that reduces auxiliary capacitor part at first forms the 1st layer dielectric film, fully remove in the 1st layer the dielectric film with the corresponding part of auxiliary capacitance electrode, thereon, stacked the 2nd layer the dielectric film that is thinner than the 1st layer dielectric film.Method as the thickness that reduces auxiliary capacitor dielectric film partly, in addition, also have and also form certain thickness dielectric film earlier, partly this dielectric film is carried out etching, reduce the method for its thickness, still, in the occasion of present embodiment, control the thickness of the dielectric film of auxiliary capacitor part easily, form the dielectric film of uniform thickness.
As above-described, according to LCD of the present invention, because under the situation of the area that does not increase the auxiliary capacitance electrode that forms by being in the light property material, can increase the electric capacity of auxiliary capacitor, in addition, pixel capacitors 20 is positioned on sweep trace 16 and the signal wire 17 according to its part, and the mode that the pixel capacitors 20 of adjacency is in notconnect state is provided with, so do not reduce the aperture opening ratio of each pixel, the demonstration that can suppress cross (talk) and flicker etc. is bad.In addition, because pixel capacitors 20 is arranged on the flat interlayer film 29,, like this, obtain the good LCD 10 of display quality so can make the box gap of the LCD 10 that is obtained even.
In addition, in LCD of the present invention is not transmission-type, but the occasion of Semitransmissive, form small jog partly on the surface of the interlayer film 29 in the zone except contact hole 30 that can be in being formed at pixel capacitors, and between this jog and pixel capacitors 20, or on the surface of pixel capacitors 20, form the reflectance coating that forms by light reflecting material.In the LCD of Semitransmissive, because the area of its transmissive portions is less than the LCD of transmission-type, so but be effective especially for the LCD of the present invention and the manufacture method thereof of the area of enlarged openings portion.In addition, plan be the occasion of reflection-type in this LCD, can and interlayer film 29 between, or at the whole zone on the surface of pixel capacitors 20, formation reflectance coating.
Embodiment 2
Below by Fig. 5 and Fig. 6 the manufacturing step of the array substrate of the LCD 10A of embodiment 2 is described.In addition, be equivalent to represent that with perspective fashion the amplification view of part of a pixel of array substrate of color filter substrate of LCD 10A of embodiment 2 is identical with the occasion of the LCD 1 of embodiment 1 shown in Figure 1, the occasion with along the LCD 10 of the corresponding figure of cut-open view of II-II line of Fig. 1 and embodiment 1 shown in Figure 2 in the array substrate of this embodiment 2 is identical, thus, as required, quote Fig. 1 and Fig. 2 and be described, the part identical with the structure of the LCD 10 of embodiment 1 adopts same label and is described.In addition, Fig. 5 A～Fig. 5 E and Fig. 6 A～Fig. 6 E are the cut-open view of the manufacturing step of the array substrate of the LCD 10A of expression manufacturing embodiment 2.In addition, Fig. 5 A～Fig. 5 E and Fig. 6 A～Fig. 6 E all represent and state along the corresponding position of section of II-II line of Fig. 1.
At first,, on transparent substrates 11, form specific thickness, the conductive layer 24 that forms by aluminium, molybdenum, chromium or their alloy as shown in Fig. 5 A.Then, as shown in Fig. 5 B, adopt known photoetching process, carry out pattern-making and handle, remove its part by etching thus, form along the many sweep traces 16 of horizontal expansion, the grid G that is connected with this sweep trace 16 and the auxiliary capacitance line 18 between these a plurality of sweep traces 16.In addition, in Fig. 5 B, the amplitude that the part by the grid G that will extend from sweep trace 16 and auxiliary capacitance line 18 is shown enlarges the auxiliary capacitance electrode 18a that forms.
Then, as shown in Fig. 5 C, to be formed with the inside of the transparent substrates 11 of sweep trace 16 and auxiliary capacitance electrode 18a by above-mentioned steps at vacuum plant, at high temperature, such as, heat under 350 ℃ the condition, according to conventional method, by plasma CVD (Chemical Vpordeposition) method etc., form from the teeth outwards specific thickness (such as, 1000
), the 1st layer the dielectric film 25 that forms by silicon nitride.Then, the temperature of transparent substrates 11 that is formed with the 1st layer dielectric film 25 from the teeth outwards is reduced to the temperature that is lower than initial temperature, such as, 250 ℃, equally by plasma CVD method etc., form specific thickness (such as, 3000
), the 2nd layer the dielectric film 26 that forms by silicon nitride.The two constitutes gate insulating films the dielectric film 26 of the 1st layer dielectric film 25 and the 2nd layer.In addition, on the whole surface of the 2nd layer dielectric film 26, thickness is (such as, a-Si layer 1800 according to the rules
And n
+A-Si layer 500
) form by such as, a-Si layer and n
+The semiconductor layer 19 that a-Si layer constitutes.
The 1st layer dielectric film 25, the 2nd layer dielectric film 26 and semiconductor layer 19 all can form under the situation of not taking out transparent substrates 11 from vacuum plant continuously.In addition, in the dielectric film 26 of the 1st layer dielectric film 25 and the 2nd layer, because the underlayer temperature difference when the corresponding insulation film forms, even so under situation about forming by identical silicon nitride, the hardness of film is still different, the 1st layer dielectric film 25 hardening that underlayer temperature is high, thus, the Wet-type etching rate of buffer fluoric acid reduces.Best, only otherwise produce short circuit, the thickness of the 1st layer dielectric film 25 is as much as possible little, and this thickness can be 500～1500
Scope in.In addition, the two gross thickness of the dielectric film 26 of the 1st layer dielectric film 25 and the 2nd layer can be 2500～5500
Scope in so that not in the grid G part of TFT, because of static produces insulation breakdown.
Here, the underlayer temperature when changing stacked dielectric film forms the different dielectric film of rate of etch, still, in addition, also can change the composition of atmosphere gas, forms the different dielectric film of rate of etch.Such as, in the occasion that forms silicon nitride, adopt silane gas and nitrogen, still, when forming the 2nd layer, compare with the occasion that forms the 1st layer, increase the ratio of silane gas, thus, can increase the hardness of the 1st layer dielectric film.
Then, as shown in Fig. 5 D, mode according to residual semiconductor layer 19 on the surface of the grid G of TFT is removed semiconductor layer 19 by dry-etching, then, the mode of exposing according to the 1st layer dielectric film 25, by adopting the Wet-type etching of fluoric acid, or dry-etching and remove the 2nd layer the dielectric film 26 on the surface of auxiliary capacitance electrode 18a, window portion 27 formed.At this moment, because the etching speed of the 1st layer dielectric film 25 is slower than the etching speed of the 2nd layer dielectric film 26, so the 1st layer dielectric film 25 can substantially not have etched state left behind.
Then, on transparent substrates 11, form the conductive layer that forms by aluminium, molybdenum, chromium or their alloy, then, as shown in Fig. 1 and Fig. 5 E, to the many signal wires 17 of the perpendicular direction extension of edge and sweep trace 16; Extend the source S that is connected with semiconductor layer 19 from this signal wire 17; Cover auxiliary capacitance electrode 18a, and the drain D that an end is connected with semiconductor layer 19 is carried out the pattern-making processing.Thus, near the cross part of the sweep trace 16 of transparent substrates 11 and signal wire 17, form the TFT that constitutes on-off element.
In addition; as shown in Fig. 6 A; according to the mode that covers various wirings; on transparent substrates 11, be formed for surface-stable; by inorganic insulating material (such as; silicon nitride) the protection dielectric film 28 of Xing Chenging; then, as shown in Fig. 6 B, film 29 between cambium layer; this interlayer film 29 is used to make having an even surface of array substrate 13; form by organic insulation with polyimide etc., then, as shown in Fig. 6 C; by etching, be positioned at the interlayer film 29 on the auxiliary capacitance electrode 18a and protecting formation contact hole 30 on the dielectric film 28.In addition, the position that forms this contact hole 30 is not limited on the auxiliary capacitance electrode 18a, but owing to forming LCD 10, when fitting with color filter substrate 14, be formed with the substrate spacing of the part of contact hole 30, promptly the box gap is different with other part, so have the danger that produces surface quality difference, like this, best, be arranged on the auxiliary capacitance electrode 18a as being in the light property material.
In addition, as shown in Fig. 6 D, at 1 pixel area that centers on by sweep trace 16 and signal wire 17, form by such as, the pixel capacitors 20 that ITO forms.At this moment, best, be positioned on sweep trace 16 and the signal wire 17 according to the part of pixel capacitors 20, and the mode that the pixel capacitors 20 of adjacency is in contactless state is provided with, so that prevent light leak.By above step, manufacturing array substrate 13.
In the auxiliary capacitor of the array substrate 13 of the LCD 10A of the embodiment 2 that forms by above-mentioned manufacture method, auxiliary capacitance electrode 18a and the drain D that is connected with pixel capacitors 20 are equivalent to the electrode of capacitor, be arranged at the 1st layer dielectric film 25 between auxiliary capacitance electrode 18a and the drain D and be equivalent to the dielectric of capacitor, in addition, the thickness of the dielectric that forms by the 1st layer dielectric film 25 can be significantly less than the gate insulating film that uses in the past 2500～4500
Scope in thickness, it is 500～1500
Scope in, thus,, still can increase auxiliary capacitor significantly even do not increase the area of auxiliary capacitance electrode 18a.In addition, because the gate insulating film covering that grid G and sweep trace 16 are formed by the laminated body of the dielectric film 26 of the dielectric film 25 by the 1st layer and the 2nd layer, so guarantee insulativity fully.
As described above, according to the LCD of embodiment 2, owing to can under the situation of the area that does not increase the auxiliary capacitance electrode 18a that forms by being in the light property material, increase auxiliary capacitor, so do not reduce the aperture opening ratio of each pixel, the demonstration that can suppress cross (talk) and flicker etc. is bad.In addition, because pixel capacitors 20 is arranged on the smooth interlayer film 29,, obtain the good LCD of display quality like this so can make the box gap of the LCD 10A that is obtained even.
In addition, in the foregoing description 2, provide the example that the dielectric film 26 of the 1st layer dielectric film 25 and the 2nd layer forms by silicon nitride, but, both also can form by monox, in addition, any one in dielectric film 25 that also can the 1st layer and the 2nd layer the dielectric film 26 adopts monox, and another person adopts silicon nitride.The fast layer of rate of etch can be positioned at top layer, and in addition, if from the aspect of insulativity, the 2nd layer dielectric film 26 can be formed by silicon nitride.In addition, but also auxiliary capacitance line is formed by aluminium, and anodized is carried out on its surface, forms aluminium oxide, and this film constitutes the dielectric film of auxiliary capacity part.
Embodiment 3
Adopt Fig. 7 and Fig. 8 below, the manufacturing step of the array substrate of the LCD 10B of embodiment 3 is described.In addition, be equivalent to represent that with perspective fashion the amplification view of part of a pixel of array substrate of color filter substrate of LCD 10B of embodiment 3 is identical with the occasion of the LCD 10 of embodiment 1 shown in Figure 1, the occasion of the LCD 10 of the corresponding figure of cut-open view of in the array substrate of this embodiment 3 and II Fig. 1-II line and embodiment 1 shown in Figure 2 is identical, thus, as required, quote Fig. 1 and Fig. 2 and be described, the part identical with the structure of the LCD 10 of embodiment 1 adopts same label and is described.In addition, Fig. 7 A～Fig. 7 E and Fig. 6 A～Fig. 6 E are the cut-open view of the manufacturing step of the array substrate of the LCD 10B of expression manufacturing embodiment 3.In addition, Fig. 7 A～Fig. 7 E and Fig. 8 A～Fig. 8 E all represent and state along the corresponding position of section of II-II line of Fig. 1.
At first,, on transparent substrates 11, form specific thickness, the conductive layer 24 that forms by aluminium, molybdenum, chromium or their alloy as shown in Fig. 7 A.Then, as shown in Fig. 7 B, adopt known photoetching process, carry out pattern-making and handle, remove its part by etching thus, form along the many sweep traces 16 of horizontal expansion, the grid G that is connected with this sweep trace 16 and the auxiliary capacitance line 18 between these a plurality of sweep traces 16.In addition, in Fig. 7 B, width by the grid G that will extend from sweep trace 16 and auxiliary capacitance line 18 is shown enlarges and form auxiliary capacitor 18a.In addition, sweep trace 16 shown here and auxiliary capacitor 18 are the sandwich construction that is formed by aluminium and molybdenum, contact with the joint of pixel capacitors so that realize.
Then, as shown in Fig. 7 C, on the surface of the transparent substrates 11 that will form sweep trace 16 and auxiliary capacitance electrode 18a by above-mentioned steps, according to conventional method, by plasma CVD (Chemical Vpor deposition) method etc., form from the teeth outwards specific thickness (such as, 4000
), the dielectric film 25 ' that forms by silicon nitride, then, on the whole surface of dielectric film 25 ', thickness is (such as, a-Si layer 1800 according to the rules
And n
+A-Si layer 500
) form by such as, a-Si layer and n
+The semiconductor layer 19 that a-Si layer constitutes.
Dielectric film 25 ' and semiconductor layer 19 all can form under the situation of not taking out transparent substrates 11 from vacuum plant continuously.In addition, owing to grid G part, not because of static produces insulation breakdown, so the thickness of dielectric film 25 ' can be 2500～5500 at TFT
Scope in
Afterwards,, on the integral surface of transparent substrates 11,, adopt half-tone (half-tone) mask 32, this photo-etch layer 31 is carried out exposure handle according to forming the photoengraving layer 31 that homogeneous thickness is provided with eurymeric as shown in Fig. 7 D.In this half-tone (half-tone) mask 32, have being in the light property fully with the corresponding part 33 of the grid G of TFT, have light transmission with the corresponding part of auxiliary capacitance electrode 18a, other part 35 has half transmitting.So, if after exposure, photo-etch layer 31 is carried out development treatment, then as shown in Fig. 7 E, on the surface of grid G residual thicker photo-etch layer 31
1, on the surface of auxiliary capacity electrode 18a, there is not the light resist layer, semiconductor layer 19 exposes, and in residual part, residual its thickness is less than the photo-etch layer 31 of the photo-etch layer 311 on the surface of grid G
2
At this state, as shown in Fig. 7 F, pass through dry-etching, remove the lip-deep semiconductor layer 19 of auxiliary capacitance electrode 18a, dielectric film 25 ' is exposed,, the part of the dielectric film 25 ' that exposes is carried out Wet-type etching or dry-etching on the surface of auxiliary capacitance electrode 18a by buffer fluoric acid, residual specific thickness (such as, 1000
) dielectric film 26 '.Then, as shown in Fig. 8 A, by ashing treatment (ashing), remove thin photo-etch layer 31
2, semiconductor layer 19 is exposed.At this moment, be positioned at thicker photo-etch layer 31 on the grid G
1At the state of thickness attenuation, residual at the state that covers semiconductor layer 19, so that its part is carried out ashing treatment (ashing).Then, as shown in Fig. 8 B, remove the semiconductor layer 19 that exposes by dry-etching.
Then, by ashing treatment (ashing), removal is positioned at the thicker photo-etch layer 311 on the grid G, on transparent substrates 11, the conductive layer 24 that formation is formed by aluminium, molybdenum, chromium or their alloy, then, as shown in Fig. 1 and the 8C, to along the many signal wires 17 that extend with the perpendicular direction of sweep trace 16; Extend the source S that is connected with semiconductor layer 19 from this signal wire 17; Cover auxiliary capacitance electrode 18a, and the drain D that an end is connected with semiconductor layer 19 is carried out the pattern-making processing.Thus, near the cross part of the sweep trace 16 of transparent substrates 11 and signal wire 17, form the TFT that constitutes on-off element.In addition; according to the mode that covers various wirings; on transparent substrates 11, be formed for surface-stable; by inorganic insulating material (such as; silicon nitride) the protection dielectric film 28 of Xing Chenging, then, film 29 between cambium layer; this interlayer film 29 is used to make having an even surface of array substrate 13, is formed by the organic insulation with polyimide etc.
Then, as shown in Fig. 8 D,, form contact hole 30 being positioned on interlayer film 29 on the auxiliary capacitance electrode 18a and the protection dielectric film 28 by etching.In addition, the position that forms this contact hole 30 is not limited on the auxiliary capacitance electrode 18a, but, owing to forming LCD 10, when fitting with color filter substrate 14, be formed with the substrate spacing of the part of contact hole 30, be that the box gap is different with other part, thus the danger that produces surface quality difference had, like this, best, be arranged on the auxiliary capacitance electrode 18a as being in the light property material.
In addition, as shown in Fig. 8 E, at 1 pixel area that centers on by sweep trace 16 and signal wire 17, form by such as, the pixel capacitors 20 that ITO or IZO etc. form.At this moment, best, be positioned on sweep trace 16 and the signal wire 17 according to the part of pixel capacitors 20, and the mode that the pixel capacitors 20 of adjacency is in contactless state is provided with, so that prevent light leak.By above step, make the array substrate 13 of the LCD 10B of embodiment 3.
In the auxiliary capacitor of the array substrate 13 of the LCD 10A of the embodiment 3 that forms by above-mentioned manufacture method, auxiliary capacitance electrode 18a and the drain D that is connected with pixel capacitors 20 are equivalent to the electrode of capacitor, be arranged at the 1st layer dielectric film 26 ' between auxiliary capacitance electrode 18a and the drain D and be equivalent to the dielectric of capacitor, in addition, the thickness of the dielectric that forms by the 1st layer dielectric film 26 ' can be significantly less than the gate insulating film that uses in the past 2500～4500
Scope in thickness, the former thickness is 500～1500
Scope in, thus,, still can increase auxiliary capacitor significantly even do not increase the area of auxiliary capacitance electrode 18a.In addition, grid G and sweep trace 16 are by passing through the gate insulating film covering that the dielectric film 25 ' of its thickness greater than dielectric film 26 ' forms, so guarantee insulativity fully.
In addition, in the foregoing description 3, provide the example that the dielectric film 26 of the 1st layer dielectric film 25 and the 2nd layer forms by silicon nitride, but, in such occasion, because dielectric film 25 ' is a homogeneous, so dielectric film 25 ' is being carried out wet etch process by buffer fluoric acid, when forming thin dielectric film 26 ', must strictly manage according to etching period.But, if dielectric film 25 ' is the sandwich construction that is formed by the different material of etching speed, then can make etching condition more flexible, make easily.Such as, initial, the temperature of raising transparent substrates 11, the silicon nitride film of hard is set, then, if reduce the temperature of transparent substrates 11, stacked soft silicon nitride film, then for soft silicon nitride film, because by buffer fluoric acid, etching speed increases, even so under the situation of error with etching period a little, silicon nitride film to the hard of bottom carries out etching hardly, like this, can obtain the insulation course 26 of correct thickness.
Also have, dielectric film 25 ' can be formed by the simple layer of monox, in addition, also can be made of the sandwich construction of silicon nitride layer and silicon oxide layer.But if from the aspect of insulativity, top layer can be formed by silicon nitride film.
Have, in the foregoing description 3, provide the example that dielectric film 25 ' and dielectric film 26 ' form by silicon nitride, still, both all can be formed by monox etc., and in addition, also can make 1 in the 1st dielectric film and the 2nd dielectric film is monox, and another person is a silicon nitride.
As recited above, if adopt the LCD 10B of embodiment 3, owing under the situation of the area that does not increase auxiliary capacitance electrode 18a, can increase the electric capacity of auxiliary capacitor, so do not reduce the aperture opening ratio of each pixel, the demonstration that can suppress cross (talk) and flicker etc. is bad.In addition, manufacture method according to the LCD 10B of embodiment 3, if in order to form gate insulating film and semiconductor layer successively continuously, after forming gate insulating film and carrying out etching step, compare with the method for the existing example that forms semiconductor layer, then can with substrate around from atmospheric pressure state, the step that remains on vacuum state reduces 1 time, and by half-tone (half-tone) mask, the light resist layer on every side that residues in auxiliary capacitance line is carried out mask process, by etching, can remove the lip-deep semiconductor layer that is positioned at auxiliary capacitance line, in addition, owing to be difficult to be subjected to the influence of the pollution that the etching step at gate insulating film produces, so the minimizing of the situation of the characteristic variation of TFT.In addition, manufacture method according to the LCD 10B of embodiment 3, because after the semiconductor layer to the surface of auxiliary capacitance line carries out etch processes, can carry out mask process to residual light resist layer and semiconductor layer same as before,, form insulation course by etching, so needn't be after forming insulation course, the situation that the etching step of semiconductor layer increases particularly needn't be provided with lithography step when forming insulation course.
Claims (17)
1. LCD, this LCD are included in many signal wires and the sweep trace that is rectangular setting on the transparent substrates; Many auxiliary capacitance lines that between above-mentioned sweep trace, are provided with abreast; Thin film transistor (TFT), this thin film transistor (TFT) are arranged near the intersection point of above-mentioned signal wire and sweep trace; Pixel capacitors, this pixel capacitors are arranged at the relevant position of dividing by above-mentioned signal wire and sweep trace, and are electrically connected with the drain electrode of above-mentioned thin film transistor (TFT), it is characterized in that:
The grid of above-mentioned thin film transistor (TFT) and above-mentioned sweep trace cover by gate insulating film, on above-mentioned auxiliary capacitance line, extend to form the drain electrode of above-mentioned thin film transistor (TFT) in the following manner, thereby formation auxiliary capacitor, this mode are the drain clip of above-mentioned thin film transistor (TFT) establishes its thickness covers above-mentioned auxiliary capacitance line less than the insulation course of the thickness of above-mentioned gate insulating film mode.
2. LCD according to claim 1 is characterized in that above-mentioned gate insulating film is made of sandwich construction, and described insulation course is to be formed in the multilayer that constitutes above-mentioned gate insulating film the one deck on the outermost side.
3. LCD according to claim 1 is characterized in that above-mentioned gate insulating film is made of sandwich construction, and above-mentioned insulation course is the one deck on the most close transparent substrates side that is formed in the multilayer that constitutes above-mentioned gate insulating film.
4. LCD according to claim 1 is characterized in that the edge of thin part of the insulation course on the above-mentioned auxiliary capacitance line is positioned at the inboard at the edge of auxiliary capacitance line.
5. LCD according to claim 1, the thickness that it is characterized in that above-mentioned gate insulating film is 2500～5500
Scope in, the thickness of above-mentioned insulation course is 500～1500
Scope in.
6. LCD according to claim 1 is characterized in that between above-mentioned pixel capacitors and above-mentioned drain electrode, forms interlayer dielectric, in above-mentioned interlayer dielectric, be positioned at part on the auxiliary capacitance line, form contact hole, by contact hole, above-mentioned pixel capacitors and drain electrode are electrically connected.
7. LCD according to claim 6, it is characterized in that the surface or the back side in above-mentioned pixel capacitors, on above-mentioned thin film transistor (TFT) and auxiliary capacitance line, or form reflectance coating according to the mode that covers with the whole zone of the corresponding position of above-mentioned pixel capacitors.
8. the manufacture method of a LCD is characterized in that this method comprises the steps:
On transparent substrates, according to the mode that is parallel to each other many auxiliary capacitance lines are set and reach many sweep traces that are connected with grid;
Form gate insulating film according to whole the mode that covers on the above-mentioned transparent substrates;
The part that is positioned on the auxiliary capacitance line in the above-mentioned gate insulating film is carried out the filming processing, form the insulation course of its thickness less than the thickness of top peripheral part that is positioned at above-mentioned auxiliary capacitance line of gate insulating film;
Above above-mentioned gate insulating film, form the drain electrode of thin film transistor (TFT), and the formation auxiliary capacitor is extended in the drain electrode of this thin film transistor (TFT) according to the mode that covers the insulation course on the above-mentioned auxiliary capacitance line.
9. the manufacture method of LCD according to claim 8 is characterized in that:
The step that forms above-mentioned insulation course comprises the steps:
On above-mentioned gate insulating film, form semiconductor layer;
Coating photoetch agent on the surface of above-mentioned semiconductor layer;
Adopt half-tone half-tone mask, remove the photoetch agent of the auxiliary capacitor formation portion on the above-mentioned auxiliary capacitance line, with the corresponding position of grid, residual thicker photoetch agent, in other part, residual thin photoetch agent;
Again by etching, remove after the semiconductor layer of the auxiliary capacitor formation portion of exposing, remove the part of the gate insulating film that is positioned at above-mentioned auxiliary capacitor formation portion in addition, form its thickness less than around the insulation course of gate insulating film;
Remove above-mentioned thin photoetch agent, only with the corresponding position of above-mentioned grid, residual light etchant;
By etching, remove the semiconductor layer that exposes to the open air;
Remove residual photoetch agent.
10. the manufacture method of LCD according to claim 8 is characterized in that the step that forms described insulation course comprises the steps: several times, forms above-mentioned gate insulating film according to a plurality of layers; Remove the one deck at least in it.
11. the manufacture method of LCD according to claim 10 is characterized in that the step that forms described insulation course comprises removal several times, the step of the initial layer that forms when forming above-mentioned gate insulating film by multilayer.
12. the manufacture method of LCD according to claim 10 is characterized in that the step that forms above-mentioned insulation course comprises removal several times, the step of the last layer that forms when forming above-mentioned gate insulating film by multilayer.
13. the manufacture method of LCD according to claim 10 is characterized in that at each layer, changing the mode of underlayer temperature by adopting same material, forms the gate insulating film of above-mentioned sandwich construction.
14. the manufacture method of LCD according to claim 13 is characterized in that above-mentioned underlayer temperature is the highest when the formation of initial gate insulating film, reduces successively when forming another gate insulating film.
15. the manufacture method of LCD according to claim 10, the gate insulating film that it is characterized in that above-mentioned sandwich construction are by adopting same material, at each layer, the mode of the composition of the atmosphere gas around changing forms.
16. the manufacture method of LCD according to claim 8 is characterized in that this method comprises the steps:
Form the step of interlayer dielectric according to the mode that covers above-mentioned drain electrode;
On above-mentioned interlayer dielectric, the position in above-mentioned drain electrode and auxiliary capacitance line coincidence forms contact hole;
On above-mentioned interlayer dielectric, according to passing through contact hole, the mode that is electrically connected with above-mentioned drain electrode forms pixel capacitors.
17. the manufacture method of LCD according to claim 16, it is characterized in that it comprises the steps: before or after the formation of above-mentioned pixel capacitors, with above-mentioned thin film transistor (TFT) and the corresponding position of auxiliary capacitance line, or with whole of the corresponding position of above-mentioned pixel capacitors on, form reflectance coating.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101442056B (en) * | 2007-11-23 | 2010-07-07 | 胜华科技股份有限公司 | Pixel array substrate |
| CN102569190B (en) * | 2012-02-10 | 2014-02-05 | 福建华映显示科技有限公司 | Pixel structure and manufacturing method thereof |
| CN105487315A (en) * | 2016-01-19 | 2016-04-13 | 武汉华星光电技术有限公司 | TFT (thin film transistor) array substrate |
| CN109643659B (en) * | 2016-08-23 | 2022-07-26 | 凸版印刷株式会社 | Organic thin film transistor, method of manufacturing the same, and image display device |
| CN106298649A (en) * | 2016-10-27 | 2017-01-04 | 南京华东电子信息科技股份有限公司 | A kind of high permeability film crystal tube preparation method |
| CN114335028A (en) * | 2018-08-10 | 2022-04-12 | 友达光电股份有限公司 | Display device |
| CN111965908B (en) * | 2020-08-27 | 2023-10-24 | 京东方科技集团股份有限公司 | Array substrate and display device |
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| JP2584290B2 (en) * | 1988-09-19 | 1997-02-26 | 三洋電機株式会社 | Manufacturing method of liquid crystal display device |
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| JP2584290B2 (en) * | 1988-09-19 | 1997-02-26 | 三洋電機株式会社 | Manufacturing method of liquid crystal display device |
| CN1290039A (en) * | 1999-09-27 | 2001-04-04 | 株式会社半导体能源研究所 | Semiconductor device and manufacture thereof |
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