CN100476994C - Magnetic storying unit arrays and methods for identifying logic state of magnetic storying units - Google Patents

Abstract

The invention discloses an array of magnetic reserving unit and logical condition distinguishing method of magnetic reserving unit, which comprises the following steps: obtaining first signal according to reading line of magnetic reserving unit; exerting magnetic field on the magnetic reserving unit; obtaining second signal for reading line; comparing the first and second signals to distinguish logic condition of magnetic reserving unit to avoid extra time and power consumption.

Description

The array of magnetic memory cell and the method for distinguishing the magnetic memory cell logic state

Technical field

The invention relates to that containing magnet passage meets face (magnetic tunneljunction, MTJ) Mram of storage unit (magnetoresistive random access memory, MRAM), the write circuit that reads that particularly connects the face unit about the MRAM array that can reduce leakage current and a plurality of magnet passages.

Background technology

The memory storage that magnet passage connects face comprises three basic laminations: free ferromagnetic layer (free ferromagnetic layer), insulativity passage barrier (insulatingtunneling barrier), fixing ferromagnetic layer (pinned ferromagneticlayer).The magnetic moment of free ferromagnetic layer can rotate freely in externally-applied magnetic field.Fixedly ferromagnetic layer can comprise a ferromagnetic layer and the antiferromagnetic layer that the magnetic moment of this ferromagnetic layer is fixing.Therefore fixedly the direction of the magnetic moment of ferromagnetic layer is fixed.Formed by extremely thin insulation course between the fixing passage barrier between ferromagnetic layer and free ferromagnetic layer.

Magnet passage connects the electrical property of face memory element and can be represented by resistance.The size of resistance value is by free ferromagnetic layer and the fixedly magnetic moment direction decision of ferromagnetic layer.When magnetic moment was reverse direction, magnet passage connect the resistance value of face memory element for the highest, and when magnetic moment was equidirectional, the resistance value that magnet passage connects the face memory element was minimum.That is, magnet passage connect the face memory element rely on free ferromagnetic layer and fixedly the relative direction of ferromagnetic layer can store one information.In other words, the relative magnetic moment direction that connects the face memory element in any time following magnet passage only has two kinds of steady state (SS)s.These two kinds of stable magnetic moment direction are called " parallel " and " non-parallel " state, can distinguish the value of presentation logic " 0 " and logical one.

In order to write the state that this magnet passage connects the face memory element or changes this element, can apply an external magnetic field, its intensity enough changes the magnetic moment direction of free ferromagnetic layer.In order to detect the state that magnet passage connects the face memory element, can apply one and read electric current thereon.Owing to magnetic resistance can change according to the state that magnet passage connects the face memory element, can be by apply voltage connects the face memory element with the detecting magnet passage logic state in these memory element two ends.The MRAM array has comprised a plurality of magnet passages and has connect the face memory element, and connects on the bin spare in selected magnet passage by applying current sensor usually, to read the binary logic data of whole M array ram.That on-off element can be set on the current paths is wandering to prevent electric current in reading.Also can use on-off element to prevent to write interference in addition.

Through being commonly used to stop the leakage current in the MRAM circuit, these leakage currents take place when connecing bin spare for magnet passage and read usually such as the on-off element of transistor or diode.Prevent to write interference when in addition, these on-off elements also are used to carry out write activity.For instance, the design of the noiseless programmed circuit of part two transistors of utilization on each magnetic passage knot element or storage unit.Yet because these on-off elements connect in magnet passage and occupy a large amount of areas in the face unit, the circuit design of this kind kenel will reduce component density (cell density).The design of using one-transistor or diode to read electric current with control and preventing leakage current is still arranged in addition, but the MRAM component density of these designs also is not enough to meet the market demand of today in each storage unit.

In the 6th, 606, No. 263 patents of the U.S., Tang discloses the noiseless programmed circuit of MRAM array.Fig. 1 shows the structure of the mram cell 100 of the disclosed 2T1R of Tang.For with data write storage unit 14A, selector switch element 10A and 10B, the write current I on the line program 15A _WTo produce magnetic field, with the magnetic moment direction of the free ferromagnetic layer that changes memory element 14A.When selecting on-off element 10C, read electric current I r flow through bit line 12, memory element 14B, line program 15B and on-off element 10C.But the therefore voltage on the borrow line 12 and learn the data that are stored in memory element 14B.Write interference though the memory cell structure of Fig. 1 is eliminated effectively, the component density of the MRAM among Fig. 1 is very low.

In the 5th, 640, No. 343 patents of the U.S., Gallagher discloses a utilization magnet passage and connects the MRAM array of bin spare as storage unit.Fig. 2 shows the circuit 200 of Gallagher, and it uses an on-off element with control current sensor and blocks drain electric current in every storage unit.By applying electric current I _BBy bit line 22A and apply electric current I _WBy word line 24A, can write selected storage unit 20A.In addition, separately by electric current I _BOr I _WTherefore the magnetic field that is produced have only electric current I less than changing the required magnetic field of state of memory cells _BOr I _WThe storage unit 20B that is passed through (referred to herein as the half selected storage unit of getting) can not be written into.Yet combine electric current I _BOr I _WThe magnetic field that is produced, its intensity has been enough to change the store status of the storage unit 20A that chooses.

In reading action,, can go up in selected storage unit 20A and produce a forward bias voltage drop by reducing the voltage on the word line 24A and promoting voltage on the bit line 22A.In addition, the bit line 24B and the word line 22B that are chosen still remain on V Standby, and therefore half selected word line and the pressure drop between the bit line of getting storage unit is 0, therefore can conducting.The resistance value of the storage unit 20A that is chosen by detecting can be obtained the data that are stored in this storage unit.Chosen the current sensor size that storage unit flow to the word line of choosing, the resistance value of the storage unit that can obtain choosing according to the bit line of choosing certainly via this.

In the 6th, 317, No. 375 patents of the U.S., Perner has disclosed the method and apparatus of the resistance that reads the cross point memory cell array, wherein uses two stage read methods and is configured to reduce leakage current with specific voltage.Fig. 3 is a crosspoint array 300, connects face storage unit 31 comprising a plurality of magnet passages.Crosspoint array 300 comprises n line 32 (being called word line) and m alignment 33 (being called bit line), and its neutrality line 33 and word line 32 are vertical, and also both intersect.Magnet passage connects the point of crossing that face memory element 31 is positioned at word line 32 and bit line 33.Storage unit 31 is for to connect bin spare in 33 magnet passages of connecting of word line 32 and bit line.

Fig. 4 A and Fig. 4 B are the flow through current sensor of the equivalent resistance of crosspoint array and the path of leakage current among Fig. 3.Fig. 4 A shows the equivalent resistance of memory cell array.The storage unit of choosing represents that with resistance 42A the storage unit of being chosen is represented with resistance 42B, 42C and 42D.Resistance 42B represents the storage unit of not choosing along the bit line of choosing, and resistance 42C represents the storage unit of not choosing along the word line of choosing, and resistance 42D represents that remaining does not choose storage unit.For instance, array comprises the capable and m row of n if the normal resistance of all storage unit 31 is about R, and then the size of resistance 42B is about R/ (n-1), and the size of resistance 42C is about R/ (m-1), and the size of resistance 42D is about R/[(n-1) (m-1)].

By applying voltage V _STo the bit line of staggered place, and with the word line ground connection of staggered place, optional power taking resistance 42A.Current sensor I so then _SFlow through resistance 42A.Yet resistance 42B, 42C and 42D also are coupled to voltage V _SAnd between the ground voltage.In order when reading action, to alleviate leakage current effects, can be with operating voltage Vb=V _SPut on the bit line of being selected.If Vb=V _S, leakage current just can not flow through resistance 42B and 42D, and a leakage current S 3 is arranged through resistance 42C inflow place voltage, therefore can not disturb current sensor I _S

In addition, also can be by applying operating voltage Vb=V _SOn unselected word line, to alleviate leakage current effects, shown in Fig. 4 B.This moment, leakage current just can not flow through resistance 42B.Flowing through the leakage current S3 of resistance 42C and 42D and S4 can inflow place voltage, therefore can not disturb current sensor I _STherefore apply a voltage to the error that the word line do not chosen in the matrix and bit line can alleviate or eliminate current sensor.The resistance value of the storage unit that therefore can obtain reliable current sensor and choose.Because all do not comprise transistor in each storage unit, the disclosed circuit of Perner provides the MRAM of high component density.Yet the read method that Perner disclosed need be sold a large amount of power supplys of consumption, and its circuit is also very complicated, because must apply extra bias voltage on word line of not choosing and bit line when carrying out the fetch program.

In the 6th, 421, No. 271 patents of the U.S., Gogl discloses a MRAM 500, is plotted in Fig. 5, and it comprises bit line 50 and word line 51A, 51B, and wherein word line 51A, 51B are vertical also at a distance of a segment distance approximately with the direction of this bit line 50.Magnet passage meets face memory element 51-54 between bit line 50 and word line 51A, and magnet passage meets face memory element 55-58 between bit line 50 and word line 51B.Another end points that storage unit 51-54 is not connected to bit line 50 is connected to the source electrode or the drain electrode of transistor Tr 1, and storage unit 55-58 is not connected to source electrode or drain electrode that another end points of bit line 50 is connected to transistor Tr 2.The grid of transistor Tr 1 is connected to word line 51A, and the grid of transistor Tr 2 is connected to word line 51B.Transistor Tr 1 reaches or the then ground connection that drains with another source of Tr2.

When reading action, the predetermined voltage that can apply about 1V to 2V is to bit line 50.Except selected particular word line, all therefore the transistor on all word lines closes.Suppose word line 51A conducting, then transistor Tr 1 conducting.This moment is if magnet passage connects face memory element 52 and is positioned at low resistance state (magnetic moment direction of two ferromagnetic layers is parallel), and connecing face memory element 51,53,54, magnet passage is positioned at high resistance state (magnetic moment direction of two ferromagnetic layers is not parallel), then can go up obtain a signal, the signal when this signal is different from all storage unit and all is in high resistance state in word line 51A.In order to determine what person is in low resistance state among the storage unit 51-54, just uses the method for sensing (self referencesensing scheme) of self-reference.Yet this read method is called as " destructiveness reads " (destructive read), still needs after it is finished and carries out data answer program.Must once again original data be write in the storage unit that is read after destructiveness reads, this supervisor must consume extra time and power supply.

Summary of the invention

The non-destructive that discloses the MRAM array herein and used reads and writes the method that magnet passage connects the face memory element.The non-destructive method of this reading cells comprises for the read line of being chosen corresponding to this storage unit takes a sample to obtain first signal, apply temporary magnetic field to this storage unit, take a sample to obtain secondary signal for the read line of being chosen, relatively first and second signal is to distinguish the logic state of this storage unit.Then can connect the resistance change of bin spare based on this magnet passage that is detected, distinguish before and after applying magnetic field to be stored in the data that magnet passage connects bin spare.

The method that reads magnetic memory cell comprises provides a magnet passage memory element, this magnet passage memory element to comprise free ferromagnetic layer, fixing ferromagnetic layer and between free ferromagnetic layer and the fixing insulated channel barrier between the ferromagnetic layer.Implement in the kenel in this, the magnetic moment of free ferromagnetic layer can freely change, and fixedly the magnetic moment of ferromagnetic layer immobilizes.So the resistance that this magnet passage connects the face memory element can be first steady resistance or second steady resistance, and when the external magnetic field that an intensity surpasses lower bound magnetic field was applied to magnet passage and connects the face memory element, the resistance that magnet passage connects the face memory element just can change.This method also comprises uses an oneself to plan with reference to detecting, and to be compared to the difference that swing magnetic field applies front and back two signals (can be voltage or electric current), wherein this swing magnetic field can be no more than the magnetic moment rotation one of free ferromagnetic layer the angles of 90 degree.After relatively this first signal and secondary signal, can distinguish that being stored in magnetic wears fringe and connect data in the face memory element.

In addition, the MRAM array circuit comprises and is used to the data line of choosing signal is provided in the reading of data program, and the bit line that is used to apply in the data read program voltage.In addition, this array also comprises on-off element, and the grid of this on-off element is coupled to data line, is coupled to first end points of bit line, and second end points, and wherein this on-off element can be switched on when choosing signal when receiving.This array also comprises that a plurality of magnet passage that couples between second end points and word line connects the face memory element, wherein each magnet passage connects the face memory element and comprises free ferromagnetic layer, fixing ferromagnetic layer and between free ferromagnetic layer and the fixing insulated channel barrier between the ferromagnetic layer, wherein the magnetic moment of free ferromagnetic layer can freely change, fixedly the magnetic moment of ferromagnetic layer immobilizes, and can be first steady resistance or second steady resistance and this magnet passage connects the resistance of face memory element.

This array comprises that more a plurality of line program connects the face memory element corresponding to each magnet passage individually, in order to provide second to write magnetic field and swing magnetic field, wherein this first writes the merging magnetic field that magnetic field and this second write magnetic field and surpasses lower bound magnetic field, this lower bound magnetic field is required for this magnet passage of conversion connects the resistance of face memory element, and wherein the line program that connects the face memory element corresponding to this magnet passage produces second and writes magnetic field in the data write-in program.This line program provides less than the swing magnetic field in lower bound magnetic field changing the magnetic moment that magnet passage connects the free ferromagnetic layer of face memory element, and provides enough swing magnetic field corresponding to what this magnet passage connect the face memory element in the data read program.Comprise that more a sensing circuit connects first signal of face memory element through this magnet passage with detecting before not applying swing magnetic field, and after applying swing magnetic field, detect the secondary signal that connects the face memory element through this magnet passage, and borrow relatively first signal and secondary signal to distinguish to be stored in this magnet passage to connect data in the face memory element, wherein this magnet passage connects bin spare corresponding to the line program that this swing magnetic field is provided.

The MRAM array circuit comprises data line, in order to first word line that writes magnetic field to be provided, crosses over the bit line of word line.Still comprise that in addition its grid of an on-off element is coupled to data line, first end points is coupled to word line, and second end points, and wherein this switch is in receiving conducting when choosing signal.A plurality of magnet passages connects the face memory element and couples between this second end points and this bit line, each magnet passage connects the face memory element and comprises free ferromagnetic layer, fixing ferromagnetic layer and between free ferromagnetic layer and the fixing insulated channel barrier between the ferromagnetic layer, wherein the magnetic moment of free ferromagnetic layer can freely change, fixedly the magnetic moment of ferromagnetic layer immobilizes, and can be first steady resistance or second steady resistance and this magnet passage connects the resistance of face memory element.This array circuit comprises that more a plurality of line program connects the face memory element corresponding to each magnet passage individually, in order to provide second to write magnetic field, wherein this first writes the merging magnetic field that magnetic field and this second write magnetic field and surpasses lower bound magnetic field, and the resistance value that this magnet passage connects the face memory element changed, wherein the line program that connects the face memory element corresponding to this magnet passage produces second and writes magnetic field in the data write-in program.

The present invention is achieved in that

The invention provides a kind of array of magnetic memory cell, each these magnetic memory cell comprises by free ferromagnetic layer, fixing ferromagnetic layer and be positioned at piling up that insulated channel barrier between the former two forms, wherein a write signal and a magnetic field surpass the lower bound magnetic field intensity that can change this resistance value of being chosen magnetic memory cell in the merging magnetic field intensity of being chosen the generation of magnetic memory cell place, the array of this magnetic memory cell comprises: a plurality of magnetic memory cells is coupled in together mutually; The first a plurality of leads, correspond respectively to each these a plurality of magnetic memory cell, being used to read when action is chosen the magnetic memory cell place and applies one and adjust signal in being adjacent to, this adjustment signal produces a magnetic field, and the intensity in this magnetic field is enough to change the magnetic moment that this is chosen magnetic memory cell; Second lead, perpendicular to each this first a plurality of lead, read signal to these a plurality of magnetic memory cells in order to apply first, and be applied in this adjustment signal and be adjacent to this when being chosen the storage unit place, in order to apply the second reading number of winning the confidence to these a plurality of magnetic memory cells; And sensing circuit, be coupled to this second lead, in order to relatively this first reads signal and this second reading number of winning the confidence, chosen the logic state of storage unit so that distinguish this.

The array of magnetic memory cell of the present invention more comprises on-off element, is coupled to these a plurality of magnetic memory cells.

The array of magnetic memory cell of the present invention, also comprise word line, described on-off element is a transistor, this transistor is in order to read and to write the logic state that this is chosen magnetic memory cell, wherein this transistorized grid is coupled to one and chooses signal to this transistorized data line in order to apply, this transistorized first source/drain electrode is coupled to this word line corresponding with it, this transistorized second source/drain electrode is coupled to first end points of this a plurality of magnetic memory cell, and second end points of this a plurality of magnetic memory cell is coupled to this second lead.

The array of magnetic memory cell of the present invention more comprises two on-off elements, is coupled to the two ends of these a plurality of magnetic memory cells respectively, and these a plurality of magnetic memory cell parallel connections are between these on-off elements.

The array of magnetic memory cell of the present invention, also comprise bit line, described on-off element is a transistor, this transistor is in order to read or to write the logic state of each these magnetic memory cell of being chosen, wherein these transistorized grids are coupled to one and choose signal to these transistorized word lines in order to apply, these transistorized first source/drain electrodes are coupled to this bit line corresponding with it, these transistorized second source/drain electrodes are coupled to first end points of these a plurality of magnetic memory cells, and second end points of this a plurality of magnetic memory cell is coupled to this second lead.

The present invention also provides a kind of method of distinguishing the logic state of the magnetic memory cell of being chosen in the array, and the described method of the logic state of the magnetic memory cell of being chosen in the array of distinguishing comprises: apply first signal to these magnetic memory cells that are coupled in together; Detect this first signal; Apply and adjust signal to being adjacent to the magnetic memory cell place that these are chosen, this adjustment signal can produce a magnetic field, and the intensity in this magnetic field is enough to change the magnetic moment direction that these are chosen magnetic memory cell; When applying this adjustment signal, apply secondary signal to these a plurality of storage unit; Detect this secondary signal; And relatively this secondary signal and this first signal, this is chosen the logic state of magnetic memory cell to distinguish each.

The method of distinguishing the logic state of the magnetic memory cell of being chosen in the array of the present invention, this step that applies this first signal comprises that more utilization is coupled to two on-off elements at the two ends of these a plurality of magnetic memory cells respectively, and these a plurality of magnetic memory cell coupled in parallel together.

The method of distinguishing the logic state of the magnetic memory cell of being chosen in the array of the present invention, these magnetic memory cells are coupled in together with parallel way, or be coupled in together via following manner, wherein first group of these a plurality of magnetic memory cell is cascaded, and second group of these a plurality of magnetic memory cell is cascaded, and this first group is in parallel with this second group these a plurality of magnetic memory cells afterwards again.

The method of distinguishing the logic state of the magnetic memory cell of being chosen in the array of the present invention, the step that applies this adjustment signal is included near these and is subjected to selected magnetic memory cell place to apply this adjustment signal, wherein the intensity of this adjustment signal only is enough to this magnetic moment direction of being chosen magnetic memory cell is temporarily changed an acute angle angle, and after removing this adjustment signal, this magnetic moment of being chosen magnetic memory cell returns back to the preceding script state of this adjustment signal that do not apply.

The method of distinguishing the logic state of the magnetic memory cell of being chosen in the array of the present invention, these magnetic memory cells are magnetic random access memory unit, comprise that the magnet passage that has a plurality of laminations meets face (magnetic tunneling junction, MTJ) pile up, and this adjustment signal applies a magnetic field along this hard axis of being chosen magnetic memory cell.

The array of magnetic memory cell of the present invention and the method for distinguishing the magnetic memory cell logic state need not once again original data to be write in the storage unit that is read after reading, so can avoid consuming extra time and power supply.

Description of drawings

Fig. 1 connects the structure of the MRAM array of bin spare for the magnet passage of the disclosed 2T1 of invention of Tang;

Fig. 2 is the disclosed MRAM circuit of the invention of Gallagher;

Fig. 3 is the disclosed crosspoint array of the invention of Perner, wherein comprises a plurality of magnet passages and connects the face storage unit;

Fig. 4 A and Fig. 4 B are the sensing and the leakage current path of the resistive crosspoint array of the Perner that flows through among Fig. 3;

Fig. 5 is the disclosed MRAM configuration of the invention of Gogl;

Fig. 6 is the mac function figure of the integrated circuit component that comprises memory cell array of the embodiment of the invention;

Fig. 7 is the mac function figure that applies to the storage unit of memory cell array among Fig. 6 of the embodiment of the invention;

Fig. 8 is the partial circuit figure of the memory cell array of the embodiment of the invention;

Fig. 9 is the partial cross section figure of the memory cell array among Fig. 8;

Figure 10 is the partial plan of the memory cell array among Fig. 8;

Figure 11 is the process flow diagram of method of the reading cells of the embodiment of the invention;

Figure 12 is another enforcement kenel of the memory cell array among Fig. 8;

Figure 13 is the partial circuit figure of another embodiment of the memory cell array among Fig. 8;

Figure 14 is the partial circuit figure of another embodiment of the memory cell array among Fig. 8;

Figure 15 is the partial circuit figure of another embodiment of the memory cell array among Figure 14;

Figure 16 is the partial circuit figure of another embodiment again of the memory cell array among Figure 14;

Figure 17 is the partial circuit figure of another embodiment of the memory cell array among Figure 16;

Figure 18 is the partial circuit figure of another embodiment of the memory cell array among Figure 17;

Figure 19 is the partial circuit figure of another embodiment again of the memory cell array among Figure 17;

Figure 20 is the circuit diagram that connects the storage array of face memory element according to the magnet passage of the single on-off element of configuration of the embodiment of the invention;

Figure 21 is the partial cross section figure of the circuit among Figure 20;

Figure 22 is the partial plan of the circuit among Figure 20;

Figure 23 is another part planimetric map of the circuit among Figure 20;

Figure 24 connects the circuit diagram of the storage array of face memory element for the magnet passage that disposes single on-off element according to another embodiment of the present invention;

Figure 25 for according to the present invention again the magnet passage of the single on-off element of configuration of another embodiment connect the circuit diagram of the storage array of face memory element;

Figure 26 applies to the embodiment that another grouping that magnet passage among Figure 25 connects the face memory element couples.

Embodiment

Following many embodiment or the example of will proposing is to reach the difference in functionality of the present invention under various enforcement situation.In order to simplify the present invention, the following particular example that will describe assembly or configuration.These examples are only in order to illustrating, and are not limitation of the invention.In addition, the present invention will repeat to address numeral and letter in various example; This is in order to illustrate and to simplify example, and these numerals and letter are not the relation that is used for representing between various embodiment or its configuration.In addition following meeting is addressed first characteristic body and is formed at situation on second characteristic body, this can comprise the performance that first characteristic body and second characteristic body directly contact, also can include other characteristic bodies and generate and be interspersed between first characteristic body and second characteristic body, so that the performance that first characteristic body and second characteristic body directly do not contact.

With reference to figure 6, this is the calcspar according to the integrated circuit 600 of the embodiment of the invention.Integrated circuit 600 comprises memory cell array 610, and it is controlled by array logic circuit 620 via interface 630.Array logic circuit 620 can comprise various logical circuit, for example ranks code translator, sensing amplifier, and interface 630 can comprise one to several bit lines, gate line (gate lines), digital line (digit lines), control line (control lines), word line, and other connect the communication line of memory cell arrays 610 and array logic circuit 620.Though be called as bit line or word line in these communication lines herein, and in different application aspect of the present invention, also may use different communication lines.This integrated circuit more comprises such as other logical circuits 640 of counter, timer, processor and such as the input/output circuitry 650 of impact damper, driving circuit.

With reference to figure 7, (magnetic random access memory, MRAM) unit 700 in this a plurality of magnetoresistance random access storage that is comprised for the memory cell array 610 of Fig. 6.The structure of each mram cell 700 does not need identical, but in order to illustrate so, the structure of each mram cell is considered as comprising that one connects bin spare 710 and to several on-off elements 720 to several magnet passages herein.Magnet passage connects the various enforcement kenel of bin spare 710 and will further discuss in following, and the example of on-off element then comprises metal-oxide semiconductor (MOS) (MOS) transistor, MOS diode, reaches bipolar transistor.Storage unit 700 can store 1,2,3,4 or more a plurality of position.In addition, the single or dual magnet passage that connects face that the present invention can be applicable to different resistance varying-ratios (MR ratio) connects bin spare, and the latter can comprise 4 kinds of magnetic resistance change rate values.Different resistance varying-ratios can be promoted the ability of at least 4 kinds of magnetic resistance change rate values of sensing, and allows and store at least two in the single element.

Mram cell 700 comprises 3 end points, is respectively first end points 730, second end points 740, the 3rd end points 750.For instance, first end points 730 can be connected to one to several bit lines, and in reading when action output voltage to this equipotential line.Second end points 740 is connected to one to several word lines, and this word line can start the read-write motion of storage unit 700.The 3rd end points 750 is similar to control line, for example gate line or digital line, and this end points can produce electric current so that magnetic field to be provided, so that change the state that this magnet passage connects face (MTJ) element.We must understand the configuration of bit line, word line, control line and other signal wires can be different with different circuit design, and herein only for explanation with an example is provided.

With reference to figure 8, shown here is the partial circuit figure of the memory cell array 800 of the embodiment of the invention.Memory cell array 800 comprises word line W1, W2, bit line B1-B4, and lead A1-A4 and A1 '-A4 ', read line R1, R2, on-off element 110a-110h, magnet passage connect face and pile up 120a-120d, 125a-125d, 130a-130d, 135a-135d.Each magnet passage connects that face piles up 120a-120d, 125a-125d, 130a-130d, 135a-135d can be such as storage unit storage unit such as (1,1).Certainly, memory cell array 800 still can comprise the more multiple memory cell except shown in Fig. 8.

Each magnet passage connects face and piles up 120a-120d, 125a-125d, 130a-130d, 135a-135d and can comprise the free layer, the passage barrier layer (tunneling barrier layer) that is adjacent to free layer that are adjacent to line program, be adjacent to the fixed bed of passage barrier layer and be positioned at terminal word line.Yet implement in the kenel at other, the position of free layer and fixed bed may exchange.Each magnet passage connects face and piles up 120a-120d, 125a-125d, 130a-130d, 135a-135d one major axis (being referred to as easy magnetizing axis herein, easy axis) and a minor axis (being referred to as hard axis herein, hard axis) are also arranged.

Each fixed bed may comprise the ferromagnetism material, and the magnetic pole wherein and the direction of magnetic moment are fixed.For instance, can comprise an antiferromagnetic layer or antiferromagnetism exchange layer (an anti-ferromagnetic exchange layer) in adjacency or contiguous fixed bed part.Implement in the kenel in one, fixed bed comprise the alloy of NiFe, NiFeCo, CoFe, Fe, Co, Ni, above-listed material or compound, with and/or other ferromagnetism materials.Fixed bed also can comprise a plurality of laminations.For instance, fixed bed can comprise that being interspersed in two to several layers Ru between ferromagnetic layer makes separate layers (spacer layer).Therefore each fixed bed can be or comprises compound antiferromagnetic layer (synthetic anti-ferromagnetic layer).Fixed bed can by chemical meteorology deposition method (CVD), plasma-assisted chemical vapour deposition (PE CVD), ald (atomic layer deposition, ALD), physical vapor deposition (PVD), electrochemical deposition (electro-chemical deposition), molecule manipulation (molecular manipulation) and/or other processing procedures form.

The passage barrier can comprise Siox, SiNx, SiOxNy, AlOx, TaOx, Tiox, AlNx, with and/or other nonconductor materials.In an enforcement kenel, the passage barrier can form via CVD, PE CVD, ALD, PVD, electrochemical deposition, molecule manipulation and/or other processing procedures.The material of free layer and processing procedure roughly are similar to fixed bed.For instance, free layer can comprise alloy or compound and/or other ferromagnetism materials of NiFe, NiFeCo, CoFe, Fe, Co, Ni, above-mentioned material, and free layer also can form via CVD, PECVD, ALD, PVD, electrochemical deposition, molecule manipulation and/or other processing procedures.Yet free layer may not link to each other with the antiferromagnetism material, so the magnetic moment direction of free layer can change.For instance, the magnetic moment of free layer can refer to toward surpassing more than one direction.In an enforcement kenel, free layer can comprise a plurality of laminations, for example is interspersed in 2 to the Ru between several ferromagnetic layers system separate layers.Therefore free layer can be or comprises compound antiferromagnetic layer.

Word line W1, W2, bit line B1-B4, lead A1-A4 and A1 '-A4 ', read line R1, R2 all can be the conducting wire, comprise conductor main body (bulk conductor) and batch coating (cladding layer).The conductor main body can form via CVD, PECVD, ALD, PVD, electrochemical deposition, molecule manipulation and/or other processing procedures, and wherein can comprise Cu, Al, Ag, Au, W, these alloy/compound or other materials.The conductor main body also can comprise the diffused barrier layer of being made up of Ti, Ta, TiN, TaN, WN, SiC or other materials (barrier layer).Composition and the manufacture of criticizing coating roughly can be similar to free layer.For instance, criticize coating and can comprise NiFe, NiFeCo, CoFe, Fe, Co, Ni, its alloy or compound or other ferromagnetism materials, and can form via CVD, PE CVD, ALD, PVD, electrochemical deposition, molecule manipulation and/or other processing procedures.

When writing to storage unit, the magnetic field intensity of bit line of being chosen and word line staggered place enough changes the state of selected storage unit.For instance, in storage unit (1,1) is carried out can choosing word line W1 in the performance of write activity, and apply write current Iw1 on the lead A1, apply write current Iw2 on bit line B1, but All other routes ground connection then.And desire is when reading a certain storage unit, and for example storage unit (1,1) then need be chosen word line W1, and applies and read voltage Vr on read line R1.Then just can go up sampling and read electric current I r1 by read line R1.In reading action when carrying out, read electric current I r1 and on read line R1, can keep a period of time.Can on lead A1, excite one to adjust electric current I _Adj, and take a sample for the electric current I r2 that reads of read line R1.Can more originally read electric current I r1 and read electric current I r2, to determine the logic state of storage unit (1,1) through what adjust.Can eliminate the adjustment electric current I afterwards _Adj

With reference to figure 9, be the partial cross section figure of the embodiment of the memory cell array 800 among Fig. 8 herein.Memory cell array 800 can comprise base material 105 and be formed at one in the base material to several on-off elements 110a-110h.For instance, the part of the memory cell array 800 among Fig. 9 comprises on-off element 110a, 110b, and wherein on-off element 110a, 110b are transistor, and it comprises source electrode, the drain electrode 115 that is formed in the base material 105, and the grid on base material 117.Though do not show among Fig. 9 that grid 117 is as can directly or indirectly being coupled to word line W1 among Fig. 8.Implement in the kenel in part, can use diode to replace the transistor of on-off element 110a-110h.

The material of base material 105 can comprise silicon, gallium arsenide, gallium nitride, tension force silicon wafer, germanium silicide, silit, carbonide, diamond and/or other materials.Implement in the kenel in one, base material 105 comprises silicon insulation course (SOI, silicon-on-insulator) base material, for example silicon on sapphire (silicon on sapphire) base material, strain isolated germanium (silicongermanium on insulator) base material or other are included in the base material of the semiconductor layer of extension on the insulation course.Base material 105 also can comprise complete vague and general silicon insulation course base material, and it comprises a thickness at the active layer (active layer) of 5nm to the scope of about 200nm.Base material 105 also can comprise clearance (air gap), for example is formed to cover silicon (silicon onnothing, SON) clearance in the structure on the air-gap.

The part that memory cell array 800 is shown among Fig. 9 also comprises bit line B1, B2, lead A1-A4, and read line R1.Fig. 9 also more clearly draws and how to use writing line 190 to connect face and pile up 120a-124d with the programming magnet passage, may apply to lead A1-A4 in the lump in its process.Memory cell array 800 also can comprise: intraconnections 140 is connected to read line R1 in order to these magnet passages are connect after face piles up the 120a-120d parallel connection; Intraconnections 150 is in order to be connected to writing line 190 source/drain region 115 of on-off element 110a, 110b; And intraconnections 160, in order to bit line B1, B2 are connected to source/drain region 115 of on-off element 110a, 110b.

Intraconnections 140,150,160 is extensible pass through one to several dielectric layers to be connected to on-off element 110a-110h, bit line B1-B4, read line R1, R2, lead A1-A4, A1 '-A4 ', word line W1, W2, writing line 190, or the characteristic body in other memory cell arrays 800.For instance, intraconnections 150,160 can be connected to bit line B1, B2 via on-off element 110a, 110b with writing line 190, wherein writing line 190 can be adjacent to magnet passage and piles up 120a-120d, piles up 120a-120d so that allow these magnet passages of current programmable between bit line B1, B2 connect face.The material of intraconnections 140,150,160 can comprise copper, tungsten, gold, aluminium, CNT transistor (Carbon Nano-Tube, CNT), carbon bunch (carbon fullerene), refractory metal or other materials, and it can form via CVD, PECVD, ALD, PVD or other processing procedures.Dielectric layer can comprise silicon dioxide, BLACK DIAMOND (product of Applies Material) or other materials, and can form via CVD, PECVD, ALD, PVD, rotary coating (spin-on coating) or other processing procedures.

As above-mentioned, under the performance of write storage unit (1,1), can choose word line W1 with turn-on transistor 110a, 110b, put on write current Iw2 on the bit line B1 and can flow on the writing line 190 (in this action, but bit line B2 ground connection) so that allow.Can apply write current Iw1 this moment to lead A1, thereby the magnetic field intensity that the electric current on writing line 190 and the lead A1 produces has been enough to memory cells (1,1).Since lead A1-A4 can with writing line 190 and usefulness, connect the state that face piles up 120a-120d to change magnet passage, lead A1-A4 herein also can be called as writing line.Writing line A1-A4 and writing line 190 also can be called as line program.

With reference to Figure 10, be the partial plan of the memory cell array 800 among Fig. 9 herein.Each lead A1-A4 roughly can be perpendicular to writing line 190.Each magnet passage connects face and piles up 120a-120d one hard axis that is roughly parallel to writing line 190 can be arranged, and an easy magnetizing axis that is roughly parallel to lead A1-A4 corresponding with it.Magnet passage connects the orientation that face piles up 120a-120d can be roughly parallel to hard axis, as shown in Figure 10.Magnet passage connects the magnetic moment of the direction of the hard axis that face piles up perpendicular to fixed bed.

To Figure 10, memory cell array 800 can comprise a plurality of groups 170 of piling up with reference to figure 8.Each piles up group 170 can comprise that N magnet passage in parallel connects face and pile up.For instance, the 9th and Figure 10 in the group of piling up 170 comprise that 4 magnet passages connect face and pile up 120a-120d, this moment N=4.Yet N can be the arbitrary integer of the enforcement kenel of giving an example greater than the present invention.When reading, the value that reads electric current can reflect the selected parallel resistance value of organizing in 170 of piling up.So can eliminate any leakage current (such as the leakage current in the cross-point memory array of traditional form).So the component density of the memory cell array 800 among Fig. 8 to Figure 10 can be the same high with traditional cross point memory cell array, but can avoid the leakage problem in the cross point memory cell array.

With reference to Figure 11, shown herely be process flow diagram according to the non-destructive method that reads storer 1100 of the embodiment of the invention.Method 1100 comprises step 210, choose this moment one to several word lines or bit line with a selected storage unit.But remaining circuit is ground connection then.In step 220, detect and keep reading electric current I r1.In step 230, apply one and adjust on the line program or writing line of the storage unit that electric current reads to being adjacent in the step 230, therefore the direction in the hard axis of this storage unit produces a magnetic field.In step 240, in adjusting electric current I _AdjWhen applying, r2 detects to electric current I.Then in step 250, compare the value that electric current I r1 and Ir2 are detected, to distinguish the state of the storage unit that is read.

Vector 205 explanations among Figure 11 can be adjusted the magnetic moment direction of free layer along the magnetic field of the hard axis of the storage unit that is read.In step 260, if the value of the second electric current I r2 surpasses the first electric current I r1, then the magnet passage that is read connect the face memory element free ferromagnetic layer script magnetic moment direction for the magnetic moment of fixing ferromagnetic layer in the other direction.Thereby the magnetic moment direction of original free layer and fixed bed is not parallel, and it is not parallel that the magnet passage that is therefore read connects the face position, shown in step 270.If the value of the first electric current I r1 surpasses the second electric current I r2, then the magnet passage that is read connects the magnetic moment direction of script of free ferromagnetic layer of face memory element for equidirectional with the magnetic moment of fixing ferromagnetic layer.Thereby original free layer is identical with the magnetic moment direction of fixed bed, and it is parallel that the magnet passage that is therefore read connects the face position, shown in step 275.In step 280, can eliminate the adjustment electric current I _AdjImplement to adjust electric current I in the kenel in one _AdjCan be with the magnetic moment correction one acute angle angle of free layer, for example 45 spend, and do not change its state.

Another sample attitude of the memory cell array 800 of Figure 12 displayed map 8 is referred to as memory cell array 1200 herein.The memory cell array 1200 of Figure 12 is roughly similar in appearance to the memory cell array 800 of Fig. 8.Yet the group 170 of piling up of Fig. 8 redraws pattern into simplifying in Figure 12.Each piles up group and 170 comprises that N magnet passage connects face and pile up 120, and these magnet passages connect face and pile up 120 and be connected in parallel to its corresponding read line R1, R2.Numeral N can be the integer greater than 1.

Be arranged in and pile up group each magnet passage of 170 and connect face and pile up 120 and can be serially connected with a writing line, for example the writing line 190 among Fig. 9 and Figure 10.For instance, connecting these magnet passages in piling up group 170 connects face and piles up 120 writing line 190 and may be connected to each magnet passage and connect face and pile up 120 the fixed bed or the contiguous place of free layer.Yet each magnet passage connect face pile up 120 may only be near but be isolated with corresponding writing line A1-An, A1 '-An ', wherein connecing face in each numbering n and magnet passage that piles up writing line A1-An in the group 170, to pile up 120 numbering n identical.Each piles up the element that group 170 can be considered three end points, wherein an end points is connected to corresponding read line R1, R2, and another end points is connected to bit line (for example B1 or B3) via on-off element 110, and another end points is connected to another bit line (for example B2 or B4) via another on-off element 110.On-off element 110 can be or comprises one to several transistors, diode or element.

Figure 13 is the partial circuit figure of another embodiment of the memory cell array 800 among Fig. 8, and this sentences memory cell array 1300 expressions.Memory cell array 1300 roughly is similar to memory cell array 800.For instance, memory cell array 1300 comprises bit line B1, B2, word line W1, W2, lead A1-An, A1 '-An '.Yet memory cell array 1300 also comprises reverse bit line B1 ', B2 ' and reverse word line W1 ', W2 '.

Storage array 1300 can comprise and pile up group 170, and wherein each end points that piles up group is connected to bit line via on-off element or oppositely bit line, its another end points are connected to same bit line via another on-off element or oppositely bit line and another end points are connected to another circuit in bit line and the reverse bit line pairing.For instance, the storage unit 1305 in the memory cell array 1300 can comprise piles up group 170, and the one end points is connected to bit line B1 via on-off element 1310a, and wherein the grid of on-off element 1310a is connected to word line W1.Another end points that piles up group 170 in the storage unit 1305 can be connected to bit line B1 via an on-off element 1310b, and wherein the grid of on-off element 1310b can be connected to reverse word line W1 '.Another end points that piles up group 170 in the storage unit 1305 can be connected to reverse bit line B1 '.

In storage unit 1305 is carried out in the performance of write activity, optional negate is to word line W1 ', and can apply a write current Iw1 on lead A1.Then can apply another write current Iw2 to bit line B1, but All other routes ground connection then.In the performance of reading cells 1305, can choose word line W1, and apply and read voltage Vr to bit line B1.But All other routes are ground connection then.Then on bit line B1, just can keep reading electric current I r1, and detect its value.Still can on lead A1, excite one to adjust electric current I in addition _Adj, the adjusted electric current I r2 that reads on the pairs of bit line B1 detects then.Then relatively read the value of electric current I r1 and Ir2 to distinguish the state of storage unit 1305.Eliminate then and adjust electric current I _Adj

The partial circuit figure of another embodiment of the memory cell array 800 in Figure 14 displayed map 8, this sentences memory cell array 1400 expressions.Memory cell array 1400 roughly is similar to memory cell array 800.For instance, memory cell array 1400 comprises bit line B1-B4, word line W1, W2, lead A1-An, A1 '-An '.Yet memory cell array 1400 also comprises reverse bit line B1 '-B4 ', reverse word line W1 ', W2 ', and lead A1 "-An ".

Memory cell array 1400 also comprises piles up group 170, wherein each end points that piles up group be connected to bit line or oppositely bit line one of them, its another end points is connected to bit line or reverse another in the bit line via on-off element, and another end points is connected to other bit line or reverse bit line via another on-off element.For instance, the storage unit 1405 in the memory cell array 1400 can comprise piles up group 170, and the one end points is connected to reverse bit line B1 '.Another end points that piles up group 170 in the storage unit 1405 can be connected to bit line B1 via an on-off element 1410a, and wherein the grid of on-off element 1410a can be connected to reverse word line W1 '.Another end points that piles up group 170 in the storage unit 1405 can be connected to bit line B2 via another on-off element 1410b, and wherein the grid of on-off element 1410b can be connected to reverse word line W1 '.Another storage unit 1407 in the memory cell array 1400 can comprise piles up group 170, and the one end points is connected to reverse bit line B2 '.Another end points that piles up group 170 in the storage unit 1407 can be connected to bit line B2 via an on-off element 1410c, and wherein the grid of on-off element 1410c can be connected to word line W1.Another end points that piles up group 170 in the storage unit 1407 can be connected to bit line B3 via another on-off element 1410d, and wherein the grid of on-off element 1410d can be connected to word line W1.

In storage unit 1405 is carried out in the performance of write activity, optional negate is to word line W1 ', and can apply a write current Iw1 on lead A1.Then can apply another write current Iw2 to bit line B1, but All other routes ground connection then.In the performance of reading cells 1405, optional negate is to word line W1 ', and applies and read voltage Vr to reverse bit line B1 '.But All other routes are ground connection then.Then on reverse bit line B1 ', just can keep reading electric current I r1, and detect its value.Still can on lead A1, excite one to adjust electric current I in addition _Adj, then the adjusted electric current I r2 that reads on the reverse bit line B1 ' is detected.Then relatively read the value of electric current I r1 and Ir2 to distinguish the state of storage unit 1405.Eliminate then and adjust electric current I _Adj

Figure 15 shows the partial circuit figure of another embodiment of the memory cell array 1400 among Figure 14, and this sentences memory cell array 1500 expressions.Memory cell array 1500 roughly is similar to memory cell array 1400.For instance, memory cell array 1400 comprises bit line B1-B4, B1 '-B4 ', word line W1, W2, W1 ', W2 ', lead A1-An, A1 '-An ', A1 "-An ".

Memory cell array 1500 also comprises piles up group 170, wherein each end points that piles up group via on-off element be connected to bit line, oppositely bit line one of them, its another end points is connected to another in bit line or the reverse bit line, and another end points is connected to other bit line or reverse bit line via another on-off element.For instance, the storage unit 1505 in the memory cell array 1500 can comprise piles up group 170, and the one end points is connected to reverse bit line B1 ' via on-off element 1510a, and wherein the grid of on-off element 1510a can be connected to reverse word line W1 '.Another end points that piles up group 170 in the storage unit 1505 can be connected to bit line B1.Another end points that piles up group 170 in the storage unit 1505 can be connected to bit line B2 via another on-off element 1510b, and wherein the grid of on-off element 1510b can be connected to reverse word line W1 '.Another storage unit 1507 in the memory cell array 1500 can comprise piles up group 170, and the one end points is connected to reverse bit line B2 ' via on-off element 1510c, and wherein the grid of on-off element 1510c can be connected to word line W1.Another end points that piles up group 170 in the storage unit 1507 can be connected to bit line B2.Another end points that piles up group 170 in the storage unit 1507 can be connected to bit line B3 via another on-off element 1510d, and wherein the grid of on-off element 1510d can be connected to word line W1.

In storage unit 1505 is carried out in the performance of write activity, optional negate is to word line W1 ', and can apply a write current Iw 1 on lead A1.Then can apply another write current Iw2 to bit line B1, but All other routes ground connection then.In the performance of reading cells 1505, optional negate is to word line W1 ', and applies and read voltage Vr to reverse bit line B1 '.But All other routes are ground connection then.Then on reverse bit line B1 ', just can keep reading electric current I r1, and detect its value.Still can on lead A1, excite one to adjust electric current I in addition _Adj, then the adjusted electric current I r2 that reads on the reverse bit line B1 ' is detected.Then relatively read the value of electric current I r1 and Ir2 to distinguish the state of storage unit 1505.Eliminate then and adjust electric current I _Adj

Figure 16 is the partial circuit figure of another embodiment of the memory cell array 1400 among Figure 14, is referred to as memory cell array 1600 herein.Memory cell array 1600 is roughly similar in appearance to memory cell array 1400.For instance, memory cell array 1600 comprises bit line B1, B2, word line W1, W2, W1 ', W2 ', and lead A1-An, A1 '-An '.

Memory cell array 1600 also comprises piles up group 170, wherein each end points that piles up group is connected to bit line via on-off element, its another end points is connected to word line or reverse in the word line, and another end points is connected to word line or reverse another in the word line via another on-off element.Yet several on-off elements in the memory cell array 1600 can be diode but not transistor.For instance, the storage unit 1605 in the memory cell array 1600 can comprise piles up group 170, and the one end points is connected to bit line B1 via on-off element 1610a, and wherein on-off element 1610a can be or comprises diode.Another end points that piles up group 170 in the storage unit 1605 can be connected to reverse word line W1 '.Another end points that piles up group 170 in the storage unit 1605 can be connected to word line W1 via another on-off element 1610b, and wherein on-off element 1610b is a transistor, and its grid can be connected to bit line B1.

In storage unit 1605 is carried out in the performance of write activity, optional bitline B1, and can on lead A1, apply a write current Iw1.Then can apply another write current Iw2 to word line W1, but All other routes ground connection then.In the performance of reading cells 1605, can be with word line W1 and W1 ' ground connection, and the voltage on the every other word line increased to Vdd.Then apply one and read voltage Vr on bit line B1, All other routes are ground connection then.Then just can go up maintenance one and read electric current I r1, and detect its value in bit line B1.Still can on lead A1, excite one to adjust electric current I in addition _Adj, the adjusted electric current I r2 that reads on the pairs of bit line B1 detects then.Then relatively read the value of electric current I r1 and Ir2 to distinguish the state of storage unit 1605.Eliminate then and adjust electric current I _Adj

Figure 17 is the partial circuit figure of another embodiment of the memory cell array 1600 among Figure 16, is referred to as memory cell array 1700 herein.Memory cell array 1700 is roughly similar in appearance to memory cell array 1600.For instance, memory cell array 1700 comprises bit line B1, B2, word line W1, W2, W1 ', W2 ', and lead A1-An, A1 '-An '.Memory cell array 1700 also comprises piles up group 170, wherein each end points that piles up group is connected to word line or reverse in the word line via on-off element, its another end points is connected to bit line or reverse in the bit line, and another end points is connected to bit line or reverse another in the bit line via another on-off element.Several on-off elements in the memory cell array 1700 can be diode but not transistor.

For instance, the storage unit 1705 in the memory cell array 1700 can comprise piles up group 170, and the one end points is connected to word line W1 via on-off element 1710c, and wherein on-off element 1710c can be or comprises diode.Another end points that piles up group 170 in the storage unit 1705 can be connected to bit line B1.Another end points that piles up group 170 in the storage unit 1705 can be connected to reverse bit line B1 ' via another on-off element 1710d, and wherein on-off element 1710d is a transistor, and its grid can be connected to reverse word line W1 '.

In storage unit 1705 is carried out in the performance of write activity, optional bitline B1, and can on lead A1, apply a write current Iw1.Then can apply another write current Iw2 to word line W1, but All other routes ground connection then.In the performance of reading cells 1705,, and the voltage on the every other word line (for example W1 and W2) increased to Vdd with all reverse word lines (for example W1 ' and W2 ') ground connection.Then apply one and read voltage Vr on bit line B1, other circuits that comprise word line W1 are ground connection then.Then just can go up maintenance one and read electric current I r1, and detect its value in bit line B1.Still can on lead A1, excite one to adjust electric current I in addition _Adj,, the adjusted electric current I r2 that reads on the pairs of bit line B 1 detects then.Then relatively read the value of electric current I r1 and Ir2 to distinguish the state of storage unit 1705.Eliminate then and adjust electric current I _Adj,

Figure 18 is the partial circuit figure of another embodiment of the memory cell array 1700 among Figure 17, is referred to as memory cell array 1800 herein.Memory cell array 1800 roughly is similar to memory cell array 1700.For instance, memory cell array 1800 comprises bit line B1, B2, word line W1, W2, lead A1-An, A1 '-An '.Yet memory cell array 1800 also comprises bit line B3, B4, oppositely word line W1 '-o, W1 '-e, W2 '-o, W2 '-e, lead A1 "-An ".Therefore every the word line (for example W1) in the memory cell array 1800 can be corresponding to two reverse word lines (for example W1 '-o, W1 '-e).For instance, the storage unit of the odd numbered that links to each other with word line W1 can be connected to reverse word line W1 '-o, and the storage unit of the even number that links to each other with word line W1 can be connected to reverse word line W1 '-e.Yet these storage unit that are connected to a word line do not need to be connected to equably the reverse bit line of corresponding difference, so the equal distribution situation shown in Figure 18 (the reverse bit line of each bar all is connected with 50% storage unit) is unnecessary.In addition, every word line still can have and surpasses two corresponding reverse bit line (for example W1 '-1, W1 '-2, W1 '-3).

Memory cell array 1800 also comprises piles up group 170, wherein each end points that piles up group is connected to word line or reverse in the word line via on-off element, its another end points is connected to bit line, and another end points is connected to another bit lines via another on-off element.Several on-off elements in the memory cell array 1800 can be diode but not transistor.

For instance, the storage unit 1805 in the memory cell array 1800 can comprise piles up group 170, and the one end points is connected to word line W1 via on-off element 1810a, and wherein on-off element 1810a can be or comprises diode.Another end points that piles up group 170 in the storage unit 1805 can be connected to bit line B1, and its another end points can be connected to bit line B2 via another on-off element 1810b, and wherein on-off element 1810b is a transistor, and its grid can be connected to reverse word line W1 '-o.Another storage unit 1807 in the memory cell array 1800 can comprise piles up group 170, and the one end points is connected to word line W1 via on-off element 1810c, and wherein on-off element 1810c can be or comprises diode.Another end points that piles up group 170 in the storage unit 1807 can be connected to bit line B2, and its another end points can be connected to bit line B3 via another on-off element 1810d, and wherein on-off element 1810d is a transistor, and its grid can be connected to reverse word line W1 '-e.

In storage unit 1805 is carried out in the performance of write activity, optional bitline B1, and can on lead A1, apply a write current Iw1.Then can apply another write current Iw2 to word line W1, but All other routes ground connection then.In the performance of reading cells 1805, with all reverse word lines (ground connection of W1 '-o, W1 '-e, W2 '-o, W2 '-e) for example, and the voltage on the every other word line (for example W1 and W2) increased to Vdd.Then apply one and read voltage Vr on bit line B1, other circuits that comprise word line W1 are ground connection then.Then just can go up maintenance one and read electric current I r1, and detect its value in bit line B1.Still can on lead A1, excite one to adjust electric current I in addition _Adj, the adjusted electric current I r2 that reads on the pairs of bit line B1 detects then.Then relatively read the value of electric current I r1 and Ir2 to distinguish the state of storage unit 1805.Eliminate then and adjust electric current I _Adj

Figure 19 is the partial circuit figure of another embodiment of the memory cell array 1700 among Figure 17, is referred to as memory cell array 1900 herein.Memory cell array 1900 roughly is similar to memory cell array 1700.For instance, memory cell array 1900 comprises bit line B1, B2, word line W1, W1 ', W2, W2 ', lead A1-An, A1 '-An '.Yet memory cell array 1900 also comprises bit line B3, B4, and lead A1 "-An ".

Memory cell array 1900 also comprises piles up group 170, wherein each end points that piles up group is connected to word line or reverse in the word line via on-off element, its another end points is connected to bit line, and another end points is connected to another bit lines via another on-off element.Several on-off elements in the memory cell array 1900 can be diode but not transistor.Part in these on-off elements may be connected.

For instance, the storage unit 1905 in the memory cell array 1900 can comprise piles up group 170, and the one end points is connected to word line W1 ' via on-off element 1910a, and wherein on-off element 1910a can be or comprises diode.Another end points that piles up group 170 in the storage unit 1905 can be connected to bit line B1, and its another end points can be connected to bit line B2 via another on-off element 1910b, wherein on-off element 1910b is a transistor, its grid is connected to the end points of on-off element 1910a, and wherein this end points is arranged in on-off element 1910a and piles up group 170 magnet passage and connect the other end that face piles up the end points that links to each other.Another storage unit 1907 in the memory cell array 1900 can comprise piles up group 170, and the one end points is connected to word line W1 via on-off element 1910c, and wherein on-off element 1910c can be or comprises diode.Another end points that piles up group 170 in the storage unit 1907 can be connected to bit line B2, and its another end points can be connected to bit line B3 via another on-off element 1910d, wherein on-off element 1910d is a transistor, its grid is connected to the end points of on-off element 1910c, and wherein this end points is arranged in on-off element 1910c and piles up group 170 magnet passage and connect the other end that face piles up the end points that links to each other.

In storage unit 1905 is carried out in the performance of write activity, optional negate is to word line W1 ', and can apply a write current Iw1 on lead A1.Then can apply another write current Iw2 to bit line B1, but All other routes ground connection then.In the performance of reading cells 1905,, and the voltage on the every other bit line increased to Vdd with bit line B1 and B2 ground connection.Then apply one and read voltage Vr on reverse word line W1 ', other word lines and reverse word line be ground connection then.Then just can go up maintenance one and read electric current I r1, and detect its value in reverse word line W1 '.Still can on lead A1, excite one to adjust electric current I in addition _Adj, then the adjusted electric current I r2 that reads on the reverse word line W1 ' is detected.Then relatively read the value of electric current I r1 and Ir2 to distinguish the state of storage unit 1905.Eliminate then and adjust electric current I _Adj

The foregoing description provides the MRAM array of various kenels, and it comprises a plurality of group and a plurality of leads of piling up.Each piles up group and comprises that N magnet passage in parallel connects face and pile up, and wherein N is the integer greater than 1.Each magnet passage connects face and piles up and comprise a hard axis, and the direction of this hard axis roughly connects the orientation that face piles up with this N magnet passage and parallels.All pairing with it or all N magnet passage of these a plurality of leads connects face and piles up not electric coupling mutually, connects the hard axis that face piles up and the bearing of trend of these leads is approximately perpendicular to these magnet passages.The embodiment of these MRAM arrays can comprise a plurality of groups of piling up, and wherein these pile up group except comprising that above-mentioned magnet passage connects face piles up, and comprises that still being electrically coupled to this magnet passage connects two on-off elements that face piles up.In these two on-off elements one or all can be transistor or diode.Yet, connect face in the MRAM array described in the following embodiment for a plurality of magnet passages and pile up and only apply to an on-off element.

Figure 20 is for connecing the circuit diagram of the array 2000 of face memory element according to the magnet passage of the embodiment of the invention.MRAM array 2000 comprises data line D1, D2, bit line B1, B2, word line W1, W2.Magnet passage meets face memory element 61A, 61B, 61C, 61D and is parallel between word line W1 and the node 63.Each magnet passage connects the face memory element and comprises free ferromagnetic layer 2020, fixing ferromagnetic layer 2040 and between free ferromagnetic layer 2020 and the fixing insulated channel barrier 2030 between the ferromagnetic layer 2040.The magnetic moment direction of free ferromagnetic layer 2020 can freely change, and fixedly the magnetic moment direction of ferromagnetic layer 2040 is fixed, and insulated channel barrier 2030 is an insulation course as thin as a wafer.

The nmos pass transistor of on-off element 65 connects between bit line B1 and node 63, and this nmos pass transistor is subjected to the control of choosing signal on the data line D1.In the enforcement kenel of Figure 20, these 4 magnet passages meet bin spare 61A to 61D and all are connected to node 63.Except 4 magnet passages of a node configuration connect bin spare, also can connect the face memory element by 2 or 3 magnet passages of a node configuration.Line program A1, A2, A3, A4 lay respectively at corresponding magnet passage connect face memory element 61A, 61B, 61C, 61D near.In addition, sensing circuit 2010 is detected the electric current on flow through bit line B1 and the B2 when action is read in execution.

In order to write or to change the state that magnet passage meets face memory element 61A, must apply an external magnetic field, this magnetic field size is enough to change fully the stable state magnetic moment direction that magnet passage connects the free ferromagnetic layer among the face memory element 61A.Figure 21 shows the partial cross section figure of the circuit 2000 among Figure 20.Figure 22 shows the partial plan of the circuit 2000 among Figure 20.Circuit in Figure 21 is formed on the base material 70.Meet face memory element 61A for data being write to magnet passage, choose word line W1 and line program A1.So apply the first write current Iw1 on the word line W1 that chooses, and apply the second write current Iw2 on the line program A1 that chooses.The first write current Iw1 produces first and writes magnetic field near selected word line W1.The second write current Iw2 produces second and writes magnetic field near selected line program A1.The result produce by electric current I w1 and Iw2 first and second write magnetic field and meet face memory element 61A place in magnet passage and form a merging magnetic field.In addition, the MRAM array circuit of Figure 21 is provided in to form on the base material 70 example of MRAM layer.The method can repeat to implement for several times to form the MRAM of sandwich construction.For instance, 2 of Figure 21 gate array layers can superpose on base material 70.Therefore the memory capacity of wafer can increase to nearly two times.

The stable magnetic moment direction of free ferromagnetic layer is parallel to easy magnetizing axis and perpendicular to hard axis.In Figure 22, hard axis is perpendicular to the bearing of trend of line program A1.Implement in the kenel in another, the angle of hard axis and line program A1 bearing of trend is about 45 degree, shown in the circuit among Figure 23 2000.First and second writes the merging magnetic field in magnetic field, and its intensity has surpassed a lower bound magnetic field, and this lower bound magnetic field is enough to change the stable magnetic moment direction that the magnet passage that is written into connects the free ferromagnetic layer in the face memory element.So the magnet passage that is selected connects among the face memory element 61A and has stored the binary digit data.

The fetch program of the MRAM array implement example shown in Figure 20 to Figure 23 can be with reference to the process among Figure 11.At first, in step 210, choose the bit line B1 that meets face memory element 61A corresponding to the magnet passage that is read, and apply and read voltage V _ReadThereon.Choose the data line D1 that meets face memory element 61A corresponding to the magnet passage that is read this moment again, and connect the word line W1 ground connection of face memory element 61A corresponding to the magnet passage that is read.So on-off element 65 is switched on, and first read electric current I r1 and flow through bit line B1, on-off element 65 and these magnet passages in parallel and connect the face memory element, flow to the word line W1 of ground connection at last.

Then, in step 220, electric current I r1 is read in maintenance first and this reads electric current I r1 by means of sensing circuit 2010 samplings.Then in step 230, on line program A1, apply one and adjust electric current I _AdjTo produce one " swing " magnetic field (wiggle magnetic field, its direction is for connecing the hard axis direction of bin spare along magnet passage) so that the temporary transient magnetic moment direction that magnet passage connects the free ferromagnetic layer of face memory element 61A that read that changes corresponding to line program A1.This swing magnetic field is less than lower bound magnetic field, so the magnetic moment direction that magnet passage meets face memory element 61A can permanently not change.In addition, there is a nonzero component in this swing magnetic field along hard axis, thereby the magnetic moment direction that the magnet passage that is read connects the ferromagnetism free layer of face memory element can temporarily change an angle between 0 to 90 degree.Then apply second reading power taking stream Ir2, its bit line B1 that flows through, on-off element 65, these magnet passages in parallel connect the face memory element, flow to the word line W1 of ground connection at last.In step 240, when swing magnetic field still exists, borrow sensing circuit 2010 to keep and sampling second reading power taking stream Ir2.Should be noted that, in the embodiment that all disclose herein, according to circuit design and application mode, the adjustment signal (curtage) that applies in order to produce swing magnetic field may can permanently change the magnetic moment direction of being chosen storage unit, but not temporary change only is provided.In these implement kenels, storage unit read (destructive) that (and writing) can be considered " destructiveness ", and must use extra step to return to the state of original magnetic moment with the storage unit that will be read.

In step 250 first and second being read electric current I r1, Ir2 after the sensing circuit 2010 compares.In step 260, if find that second reading power taking stream Ir2 surpasses first and reads electric current I r1, the free ferromagnetic layer that the magnet passage that is then read connects the face memory element in by the magnetic moment direction before the swing current transitions for capable with the magnetic moment direction irrelevancy of fixing ferromagnetic layer.So originally the magnetic moment direction of free ferromagnetic layer is to be not parallel to fixedly ferromagnetic layer, therefore to connect the script state of face memory element be uneven to the magnet passage that is read, shown in step 270.If in applying the swing electric current I _AdjShi Faxian first reads electric current I r1 and surpasses second reading power taking stream Ir2, the free ferromagnetic layer that the magnet passage that is then read connects the face memory element in by the magnetic moment direction before the swing current transitions for paralleling with the fixing magnetic moment direction of ferromagnetic layer.So originally the magnetic moment direction of free ferromagnetic layer is to be parallel to fixedly ferromagnetic layer, therefore to connect the script state of face memory element be parallel to the magnet passage that is read, shown in step 275.In these embodiment, applying the resistance value (R that the magnet passage that is read under the situation in swing magnetic field connects the face memory element _Present) can represent by following formula (1):

$R_{\mathrm{present}}=R_L+\frac{R_H-R_L}{2}(1-\cos \mathrm{\θ})---\left(1\right)$

R wherein _LFor when free ferromagnetic layer and when fixedly the magnetic moment direction of ferromagnetic layer is parallel to each other, magnet passage connects the low-resistance value of face memory element; And R _HFor when free ferromagnetic layer and when fixedly the magnetic moment direction of ferromagnetic layer is not parallel, magnet passage connects the high resistance of face memory element; And θ serves as reasons the swing magnetic field that applied and the angle that produces changes.

Then, in step 280, eliminate and adjust electric current I _AdjSo, removed swing magnetic field.Because swing magnetic field connects the lower bound magnetic field of the steady resistance of face memory element less than the conversion magnet passage, the magnetic direction of free ferromagnetic layer returns back to the state that does not originally apply swing magnetic field.So after removing swing magnetic field, the resistance value that the magnet passage that is read connects the face memory element is with to apply swing magnetic field resistance value before identical.Therefore, need after the fetch program, separately original data not write in the storage unit that is read, not read because this is " destructiveness ".

Figure 24 is for connecing the circuit diagram of the array 2400 of face memory element according to the magnet passage that only uses single on-off element of the embodiment of the invention.MRAM array 2400 comprises data line D1, D2, bit line B1, B2, word line W1, W2.Magnet passage meets face memory element 71A, 71B, 71C, 71D and is parallel between bit line B1 and the node 73.Each magnet passage connects the face memory element and comprises free ferromagnetic layer 2420, fixing ferromagnetic layer 2440 and between free ferromagnetic layer 2420 and the fixing insulated channel barrier 2430 between the ferromagnetic layer 2440.The magnetic moment direction of free ferromagnetic layer 2420 can freely change, and fixedly the magnetic moment direction of ferromagnetic layer 2440 is fixed, and insulated channel barrier 2430 is an insulation course as thin as a wafer.

The nmos pass transistor of on-off element 2450 connects between word line W1 and node 73, and this nmos pass transistor is subjected to the control of choosing signal on the data line D1.In the enforcement kenel of Figure 24, these 4 magnet passages meet bin spare 71A to 71D and all are connected to node 73.Except 4 magnet passages of a node configuration connect bin spare, also can connect the face memory element by 2 or 3 magnet passages of a node configuration.Line program A1, A2, A3, A4 lay respectively at corresponding magnet passage connect face memory element 71A, 71B, 71C, 71D near.In addition, sensing circuit 2410 is detected the electric current on flow through bit line B1 and the B2 when action is read in execution.

Meet face memory element 71A for data being write to magnet passage, must choose word line W1 and line program A1.So apply the first write current Iw1 on the word line W1 that chooses, and apply the second write current Iw2 on the line program A1 that chooses.The first write current Iw1 produces first and writes magnetic field near selected word line W1.The second write current Iw2 produces second and writes magnetic field near selected line program A1.The result produce by electric current I w1 and Iw2 first and second write magnetic field and meet face memory element 71A place in magnet passage and form a merging magnetic field, the stable magnetic moment direction that the intensity in this merging magnetic field is enough to magnet passage is connect the free ferromagnetic layer among the face memory element 71A changes fully.(with reference to Figure 22)

The stable magnetic moment direction of free ferromagnetic layer is parallel to easy magnetizing axis and perpendicular to hard axis.Implement in the kenel in part, hard axis is perpendicular to the bearing of trend of line program A1.Implement in the kenel in other, the angle of hard axis and line program A1 bearing of trend can be 45 degree.First and second writes the merging magnetic field in magnetic field, and its intensity has surpassed a lower bound magnetic field, and this lower bound magnetic field intensity is enough to change the stable magnetic moment direction that the magnet passage that is written into connects the free ferromagnetic layer in the face memory element.So the magnet passage that is selected connects among the face memory element 71A and has stored the binary digit data.

The fetch program of the MRAM array implement example shown in Figure 24 is still followed the step described in Figure 11.At first, choose the bit line B1 that meets face memory element 71A corresponding to the magnet passage that is read, and apply and read voltage V _ReadThereon, shown in step 210.Then choose the data line D1 that meets face memory element 71A corresponding to the magnet passage that is read again, and connect the word line W1 ground connection of face memory element 71A corresponding to the magnet passage that is read.So on-off element 2450 is switched on, and first read that electric current I r1 flows through bit line B1, these magnet passages in parallel connect face memory element and on-off element 2450, flow to the word line W1 of ground connection at last.Then keep first read electric current I r1 and borrow sensing circuit 2410 samplings this read electric current I r1, shown in step 220.Then on line program A1, apply one and adjust electric current I _AdjTo produce a swing magnetic field, so that temporary transient change is corresponding to the magnetic moment direction that magnet passage connects the free ferromagnetic layer of face memory element 71A that read of line program A1, shown in step 230.Swing magnetic field intensity herein is less than the intensity in lower bound magnetic field.In addition, there is a nonzero component in this swing magnetic field along hard axis, thereby the magnetic moment direction that the magnet passage that is read connects the ferromagnetism free layer of face memory element can temporarily change an angle between 0 to 90 degree.

Then apply second reading power taking stream Ir2, its bit line B1 that flows through, these magnet passages in parallel connect face memory element, on-off element 2450, flow to the word line W1 of ground connection at last.Then, when swing magnetic field still exists, borrow sensing circuit 2410 to keep and sampling second reading power taking stream Ir2, shown in step 240.Then sensing circuit 2410 reads electric current I r1, Ir2 to first and second and compares, shown in step 250.In step 260, if find that second reading power taking stream Ir2 surpasses first and reads electric current I r1, the magnet passage that is then read meets face memory element 81A before by the swing current transitions, the magnetic moment direction of free ferromagnetic layer originally is for capable with the magnetic moment direction irrelevancy of fixing ferromagnetic layer, shown in step 270.If find that first reads electric current I r1 above second reading power taking stream Ir2, the magnet passage that is then read meets face memory element 81A before by the swing current transitions, the magnetic moment direction of free ferromagnetic layer originally is for paralleling with the fixing magnetic moment direction of ferromagnetic layer, shown in step 275.Because second reading power taking stream Ir2 can reflect the overall resistance between node 73 and the word line W1, and this overall resistance has been swung the influence in magnetic field and has been changed owing to magnet passage connects the face memory element, therefore be stored in the magnet passage that is read connect the data of face memory element can be by relatively first reading electric current I r1 and flow the value of Ir2 with the second reading power taking and obtain.

Then remove swing magnetic field, shown in step 280.Because swing magnetic field connects the lower bound magnetic field of the steady resistance of face memory element 71A less than the conversion magnet passage, the magnetic direction of free ferromagnetic layer returns back to the state that does not originally apply swing magnetic field.So after removing swing magnetic field, the resistance value that the magnet passage that is read meets face memory element 71A is with to apply swing magnetic field resistance value before identical.So need not write original data in the storage unit that is read separately after the fetch program this moment.

Figure 25 is for connecing the circuit diagram of the array 2500 of face memory element according to the magnet passage that only uses single on-off element of the embodiment of the invention.MRAM array 2500 comprises data line D1, D2, bit line B1, B2, word line W1, W2.Magnet passage meets face memory element 81A, 81B and is parallel between node 82 and the node 83, is parallel between node 82 and the bit line B1 and magnet passage meets face memory element 81C, 81D.The magnet passage of parallel connection herein connects the face memory element to be formed a magnet passage and connects the face sets of memory elements, connects with parallel way and several magnet passages connect the face sets of memory elements.For instance, magnet passage meets face memory element 81A and 81B and forms first magnet passage and connect the face sets of memory elements, form second magnet passage and connect the face sets of memory elements and magnet passage meets face memory element 81C and 81D, this first magnet passage connects face sets of memory elements and second magnet passage and connects the face sets of memory elements and be in series.

Implement in the kenel in another, magnet passage connects the face memory element 81A back of connecting with 81B and forms first magnet passage and connect the face sets of memory elements, and magnet passage connects the face memory element 81C back of connecting with 81D and forms second magnet passage and connect the face sets of memory elements, connect the face sets of memory elements and be in parallel and first magnet passage connects face sets of memory elements and second magnet passage, shown in the MRAM array 2600 of Figure 26.Yet under the different enforcement kenel of this kind, the connected mode of other signal line is still with identical shown in Figure 25, for example data line D1, bit line B1, word line W1, line program A1～A4.

In the enforcement kenel of Figure 25, magnet passage meets face memory element 81A and 81B is disposed under the node 83, and magnet passage meets face memory element 81C and 81D is disposed under the node 82.Though each magnet passage connects the face sets of memory elements and only comprises that two magnet passages connect the face memory element in the present embodiment, each magnet passage connects the face sets of memory elements also can comprise that the magnet passage more than two connects the face memory element.Each magnet passage connects the face memory element and comprises free ferromagnetic layer 2520, fixing ferromagnetic layer 2540 and between free ferromagnetic layer 2520 and the fixing insulated channel barrier 2530 between the ferromagnetic layer 2540.The magnetic moment direction of free ferromagnetic layer 2520 can freely change, and fixedly the magnetic moment direction of ferromagnetic layer 2540 is fixed, and insulated channel barrier 2530 is an insulation course as thin as a wafer.The nmos pass transistor of on-off element 2550 connects between word line W1 and node 83, and this nmos pass transistor is subjected to the control of choosing signal on the data line D1.Line program A1, A2, A3, A4 lay respectively at corresponding magnet passage connect face memory element 81A, 81B, 81C, 81D near.In addition, sensing circuit 2510 can be detected the electric current on flow through bit line B1 and the B2.

Meet face memory element 81A for data being write to magnet passage, must choose word line W1 and line program A1.So apply the first write current Iw1 on the word line W1 that chooses, and apply the second write current Iw2 on the line program A1 that chooses.The first write current Iw1 produces first and writes magnetic field near selected word line W1.The second write current Iw2 produces second and writes magnetic field near selected line program A1.The result produce by electric current I w1 and Iw2 first and second write magnetic field and meet face memory element 81A place in magnet passage and form a merging magnetic field, the stable magnetic moment direction that the intensity in this merging magnetic field is enough to magnet passage is connect the free ferromagnetic layer among the face memory element 81A changes fully.

The stable magnetic moment direction of free ferromagnetic layer is parallel to easy magnetizing axis and perpendicular to hard axis.Implement in the kenel in this, hard axis is perpendicular to the bearing of trend of line program A1.Implement in the kenel in other, the angle of hard axis and line program A1 bearing of trend can be 45 degree.First and second writes the merging magnetic field in magnetic field, and its intensity has surpassed a lower bound magnetic field, and this lower bound magnetic field intensity is enough to change the stable magnetic moment direction that the magnet passage that is written into connects the free ferromagnetic layer in the face memory element.Therefore the magnet passage that is selected connects among the face memory element 81A and has stored the binary digit data.

The fetch program of the MRAM array implement example shown in Figure 25 is still followed the step described in Figure 11.At first, choose the bit line B1 that meets face memory element 81A corresponding to the magnet passage that is read, and apply and read voltage V _ReadThereon, shown in step 210.Then choose the data line D1 that meets face memory element 81A corresponding to the magnet passage that is read again, and will connect the word line W1 ground connection of face memory element 81A corresponding to the magnet passage that is read.So on-off element 2550 is switched on, and first read that electric current I r1 flows through bit line B1, these magnet passages in parallel connect face memory element 81A-81D and on-off element 2550, flow to the word line W1 of ground connection at last.Then keep first read electric current I r1 and borrow sensing circuit 2510 samplings this read electric current I r1, shown in step 220.Then on line program A1, apply one and adjust electric current I _AdjTo produce a swing magnetic field, so that temporary transient change is corresponding to the magnetic moment direction that magnet passage connects the free ferromagnetic layer of face memory element 81A that read of line program A1, shown in step 230.Swing magnetic field intensity herein is less than the intensity in lower bound magnetic field.In addition, there is a nonzero component in this swing magnetic field along hard axis, thereby the magnetic moment direction that the magnet passage that is read connects the ferromagnetism free layer of face memory element can temporarily change an angle between 0 to 90 degree.

Then apply second reading power taking stream Ir2, its bit line B1 that flows through, magnet passage connect face memory element 81A-81D, on-off element 2550, flow to the word line W1 of ground connection at last.Then, when swing magnetic field still exists, borrow sensing circuit 2510 to keep and sampling second reading power taking stream Ir2, shown in step 240.Then sensing circuit 2510 reads electric current I r1, Ir2 to first and second and compares, shown in step 250.In step 260, if find that second reading power taking stream Ir2 surpasses first and reads electric current I r1, the magnet passage that is then read meets face memory element 81A before by the swing current transitions, the magnetic moment direction of free ferromagnetic layer originally is for capable with the magnetic moment direction irrelevancy of fixing ferromagnetic layer, shown in step 270.If find that first reads electric current I r1 above second reading power taking stream Ir2, the magnet passage that is then read meets face memory element 81A before by the swing current transitions, the magnetic moment direction of free ferromagnetic layer originally is for paralleling with the fixing magnetic moment direction of ferromagnetic layer, shown in step 275.Because second reading power taking stream Ir2 can reflect the overall resistance between node 83 and the word line W1, and this overall resistance has been swung the influence in magnetic field and has been changed owing to magnet passage connects the face memory element, therefore be stored in the magnet passage that is read connect the data of face memory element can be by relatively first reading electric current I r1 and flow the value of Ir2 with the second reading power taking and obtain.

Then remove swing magnetic field, shown in step 280.Because swing magnetic field connects the lower bound magnetic field of the steady resistance of face memory element 81A less than the conversion magnet passage, the magnetic direction of free ferromagnetic layer returns back to the state that does not originally apply swing magnetic field.So after removing swing magnetic field, the resistance value that the magnet passage that is read meets face memory element 81A is with to apply swing magnetic field resistance value before identical.So need not write original data in the storage unit that is read separately after the fetch program this moment.It should be noted that in above-mentioned all embodiment, all use a sensing circuit, connect data stored in the face memory element to obtain the target magnet passage by the value that compares the first electric current I r1 and the second electric current I r2.Yet also can apply the target magnet passage of swing before and after the magnetic field and connect voltage on the face memory element, to obtain wherein stored data by measurement.

The present invention has introduced with non-destructive mode with embodiment and has write method with reading cells, and comprising: (1) is taken a sample on the bit line of choosing and kept first signal; (2) the hard axis direction that connects the face storage unit along each a plurality of magnet passage applies a swing magnetic field, wherein this magnetic field is enough to make magnetic moment direction swing one acute angle between 0 to 90 degree of the free ferromagnetic layer of being chosen, but this magnetic field is not enough to again this magnetic moment direction is converted to another stable state; (3) when swinging this free ferromagnetic layer of this position of being chosen, once again the secondary signal on this same bit line is taken a sample; (4) relatively first and second signal is chosen the state of position to distinguish this.

Though the present invention by the preferred embodiment explanation as above, this preferred embodiment is not in order to limit the present invention.Those skilled in the art without departing from the spirit and scope of the present invention, should have the ability this preferred embodiment is made various changes and replenished, so protection scope of the present invention is as the criterion with the scope of claims.

In addition, chapter title herein only is regulation that meets Patent Law and the structure of pointing out interior literary composition.These titles should not limit claim scope of the present invention.For instance, though title is " TECHNICAL FIELD OF THE INVENTION ", claim should not be subject in this title paragraph in order to describe the diction sentence of so-called technical field.In addition, described technology should be by judgement for not being recognized as known techniques of the present invention under " background technology " title.And " summary of the invention " also should not be considered to be for the described description of the invention of claim.In addition, express with " one " in the narration of the present invention, must not claim whereby that the present invention only comprises this thing of single quantity.Can propose a plurality of inventions according to the restrictive condition in a plurality of claims, and these claims the present invention and equivalent thing thereof have been defined jointly, protect scope of the present invention whereby.Under all situations, the scope of these claims should determine according to the legal sense of itself, but not is subjected to the restriction of title in the instructions.

Being simply described as follows of symbol in the accompanying drawing:

The mram cell of the 2T1R of 100:Tang

10A, 10B, 10C: switch element

12: bit line

14A, 14B: memory cell

15A, 15B: line program

The circuit of 200:Gallagher

20A, 20B: memory cell

22A, 22B: bit line

24A, 24B: word line

The cross point memory cell array of 300:Perner

31: magnet passage junction memory cell

32: the word line

33: bit line

42A, 42B, 42C, 42D: the resistance of memory cell

Is: current sensor

S3, S4: leakage current

The MRAM of 500:Gogl

50: bit line

51A, 51B: word line

51,52,53,54,55,56,57,58: magnet passage junction memory element

Tr1, Tr2: transistor

600: integrated circuit

610: memory cell array

620: Array Logic Circuit

630: interface

640: other logic circuits

650: input/output circuitry

The 700:MRAM storage unit

710: magnet passage connects bin spare

720: on-off element

730,740,750: end points

800: memory cell array

(1,1): storage unit

W1, W2: word line

B1-B4: bit line

A1-A4, A1 '-A4 ': lead

R1, R2: read line

110a-110h: on-off element

120a-120d, 125a-125d, 130a-130d, 135a-135d: magnet passage connects face and piles up

105: base material

110a, 110b: transistor

115: source drain

117: grid

140,150,160: intraconnections

190: writing line

170: pile up group

1100: the non-destructive method that reads storer

1200,1300,1400,1500,1600,1700,1800,1900: memory cell array

110: on-off element

120: magnet passage connects face and piles up

170: pile up group

R1, R2: read line

A1-An, A1 '-An ', A1 "-An ": writing line

B1, B2, B3, B4: bit line

B1 ', B2 ', B3 ', B4 ': reverse bit line

W1, W2: word line

W1 ', W2 ', W1 '-o, W1 '-e, W2 '-o, W2 '-e: reverse word line

1305,1405,1407,1505,1507,1605,1705,1805,1807,1905,1907: storage unit

1310a, 1310b, 1410a-1410d, 1510a-1510d: on-off element

1610a, 1710c, 1810a, 1810c, 1910a, 1910c: diode

1610b, 1710d, 1810b, 1810d, 1910b, 1910d: transistor

2000,2400,2500,2600:MRAM array

2010,2410,2510: sensing circuit

2020,2420,2520: free ferromagnetic layer

2030,2430,2530: the insulated channel barrier

2040,2440,2540: fixing ferromagnetic layer

D1, D2: data line

B1, B2: bit line

W1, W2: word line

61A, 61B, 61C, 61D, 71A, 71B, 71C, 71D, 81A, 81B, 81C, 81D: magnet passage connects the face memory element

A1, A2, A3, A4: line program

63,73,82,83,84: node

65,2450: on-off element

70: base material

Iw1: first write current

Iw2: second write current

I _Adj: adjust electric current

Ir1: first reads electric current

Ir2: second reading power taking stream

Claims (10)

1. the array of a magnetic memory cell, it is characterized in that, each this magnetic memory cell comprises by free ferromagnetic layer, fixing ferromagnetic layer and be positioned at piling up that insulated channel barrier between the former two forms, wherein a write signal and a magnetic field surpass the lower bound magnetic field intensity that can change this resistance value of being chosen magnetic memory cell in the merging magnetic field intensity of being chosen the generation of magnetic memory cell place, and the array of this magnetic memory cell comprises:

A plurality of magnetic memory cells is coupled in together mutually;

The first a plurality of leads, correspond respectively to each this a plurality of magnetic memory cell, being used to read when action is chosen the magnetic memory cell place and applies one and adjust signal in being adjacent to, and this adjustment signal produces a magnetic field, and the intensity in this magnetic field is enough to change the magnetic moment that this is chosen magnetic memory cell;

Second lead, perpendicular to each this first a plurality of lead, read signal to this a plurality of magnetic memory cell in order to apply first, and be applied in this adjustment signal and be adjacent to this when being chosen the storage unit place, in order to apply extremely this a plurality of magnetic memory cell of the second reading number of winning the confidence; And

Sensing circuit is coupled to this second lead, in order to relatively this first reads signal and this second reading number of winning the confidence, is chosen the logic state of storage unit so that distinguish this.

2. the array of magnetic memory cell according to claim 1 is characterized in that, more comprises on-off element, is coupled to this a plurality of magnetic memory cell.

3. the array of magnetic memory cell according to claim 2, it is characterized in that, also comprise word line, described on-off element is a transistor, this transistor is in order to read and to write the logic state that this is chosen magnetic memory cell, wherein this transistorized grid is coupled to one and chooses signal to this transistorized data line in order to apply, this transistorized first source/drain electrode is coupled to this word line corresponding with it, this transistorized second source/drain electrode is coupled to first end points of this a plurality of magnetic memory cell, and second end points of this a plurality of magnetic memory cell is coupled to this second lead.

4. the array of magnetic memory cell according to claim 1 is characterized in that, more comprises two on-off elements, is coupled to the two ends of this a plurality of magnetic memory cell respectively, and this a plurality of magnetic memory cell parallel connection is between this on-off element.

5. the array of magnetic memory cell according to claim 4, it is characterized in that, also comprise bit line, described on-off element is a transistor, this transistor is in order to read or to write the logic state of each this magnetic memory cell of being chosen, wherein this transistorized grid is coupled to one and chooses signal to this transistorized word line in order to apply, this transistorized first source/drain electrode is coupled to this bit line corresponding with it, this transistorized second source/drain electrode is coupled to first end points of this a plurality of magnetic memory cell, and second end points of this a plurality of magnetic memory cell is coupled to this second lead.

6. a method of distinguishing the logic state of the magnetic memory cell of being chosen in the array is characterized in that, the described method of the logic state of the magnetic memory cell of being chosen in the array of distinguishing comprises:

Apply first signal to this magnetic memory cell that is coupled in together;

Detect this first signal;

Apply and adjust signal to being adjacent to the magnetic memory cell place that this is chosen, this adjustment signal can produce a magnetic field, and the intensity in this magnetic field is enough to change the magnetic moment direction that this is chosen magnetic memory cell;

When applying this adjustment signal, apply secondary signal to this a plurality of storage unit;

Detect this secondary signal; And

Relatively this secondary signal and this first signal, this is chosen the logic state of magnetic memory cell to distinguish each.

7. the method for distinguishing the logic state of the magnetic memory cell of being chosen in the array according to claim 6, it is characterized in that, this step that applies this first signal comprises that more utilization is coupled to two on-off elements at the two ends of this a plurality of magnetic memory cell respectively, and this a plurality of magnetic memory cell coupled in parallel together.

8. the method for distinguishing the logic state of the magnetic memory cell of being chosen in the array according to claim 6, it is characterized in that, this magnetic memory cell is coupled in together with parallel way, or be coupled in together via following manner, wherein first group of this a plurality of magnetic memory cell is cascaded, and second group of this a plurality of magnetic memory cell is cascaded, and this first group is in parallel with this second group this a plurality of magnetic memory cell afterwards again.

9. the method for distinguishing the logic state of the magnetic memory cell of being chosen in the array according to claim 8, it is characterized in that, the step that applies this adjustment signal is included near this and is subjected to selected magnetic memory cell place to apply this adjustment signal, wherein the intensity of this adjustment signal only is enough to this magnetic moment direction of being chosen magnetic memory cell is temporarily changed an acute angle angle, and after removing this adjustment signal, this magnetic moment of being chosen magnetic memory cell returns back to the preceding script state of this adjustment signal that do not apply.

10. the method for distinguishing the logic state of the magnetic memory cell of being chosen in the array according to claim 6, it is characterized in that, this magnetic memory cell is a magnetic random access memory unit, comprise that the magnet passage that has a plurality of laminations connects face and piles up, and this adjustment signal applies a magnetic field along this hard axis of being chosen magnetic memory cell.

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