CN100470835C - Electronic device containing group-III elements based nitride semiconductors - Google Patents
Electronic device containing group-III elements based nitride semiconductors Download PDFInfo
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- CN100470835C CN100470835C CNB2006101270802A CN200610127080A CN100470835C CN 100470835 C CN100470835 C CN 100470835C CN B2006101270802 A CNB2006101270802 A CN B2006101270802A CN 200610127080 A CN200610127080 A CN 200610127080A CN 100470835 C CN100470835 C CN 100470835C
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Abstract
An electronic device includes a substrate; a single-crystalline first buffer layer, disposed on the substrate, containing a semiconductor represented by the formula AlxGa1-xN; a non-single-crystalline second buffer layer, disposed on the first buffer layer, containing a semiconductor represented by the formula AlyGa1-yN; and an undoped base layer, disposed on the second buffer layer, containing GaN, wherein 0<x<=1 and 0<=y<=1. The first buffer layer is formed at a temperature of 1000 DEG C to 1200 DEG C. The second buffer layer is formed at a temperature of 350 DEG C to 800 DEG C. The substrate contains SiC. The second buffer layer has a thickness of 5 to 20 nm.
Description
Technical field
The present invention relates to electronic device for example light-emitting diode and the field-effect transistor (FETs) that comprises High Electron Mobility Transistor (HEMTs).The present invention is specifically related to contain the electronic device of III family element nitride semiconductor.
Background technology
The open No.2002-359255 (hereinafter being called patent document 1) of Japanese unexamined patent discloses a kind of technology, wherein form basic unit on conductive silicon carbide (SiC) substrate under 1100 ℃ of-1250 ℃ of temperature, this basic unit has the nitride-based semiconductor that contains aluminium (Al) and the thickness of 0.5-100 μ m; Form undoped gallium nitride (GaN) layer in the basic unit and on the GaN layer, forming nitride semiconductor layer.In this technology, basic unit is used to make insulated substrate.Basic unit most preferably comprises the aluminium nitride (AlN) with broad-band gap and insulation.
In conventional art, basic unit and/or the GaN layer that is positioned in the basic unit are doped with for example iron (Fe) of transition metal, are used to form Deep impurity level, and perhaps doping carbon (C) in some cases is so that these layers are considered to insulate.
In patent document 1 disclosed technology, though the problem that exists is device and insulated substrate, but when basic unit is become by the nitride system semiconductor with essential element Al, electronic device by this technology preparation has low dielectric strength, and when not conducting of electronic device or disconnection, leakage current flows between input and output side.In conventional art, problem is because following factor causes the device property deterioration:
(1) when the crystal growth in the undoped layer or after the crystal growth, dopant (for example transition metal) migrates to undoped layer; Thereby the degree of crystallinity of undoped layer and be positioned on the above-mentioned undoped layer or the degree of crystallinity deterioration of the semiconductor layer of top.
(2) be positioned at the heterojunction near zone and form the two-dimensional electron gas layer if dopant (for example transition metal) migrates to by thermal diffusion etc., then the gained dopant causes electronics to be dispersed in the zone on the raceway groove, increases the conducting resistance of the electronic device that comprises the layer that contains dopant thus.
Summary of the invention
Proposing the present invention is in order to address the above problem.The purpose of this invention is to provide a kind of electronic device, it has high dielectric strength owing to reducing leakage current.
In order to address the above problem, following device is useful.
The invention provides a kind of electronic device, it prepares by the semiconductor crystal layer that crystal growth forms a plurality of III of containing family element nitride base semiconductor.This electronic device comprises substrate; Be positioned at monocrystal first resilient coating on the substrate, it comprises by general formula Al
xGa
1-xThe semiconductor of N representative; Be positioned at on-monocrystalline body second resilient coating on first resilient coating, it comprises by general formula Al
yGa
1-yThe semiconductor of N representative; With the not doping basic unit that comprises GaN that is positioned on second resilient coating, wherein 0＜x≤1 and 0≤y≤1.
Basic unit is defined as the layer that is positioned on second resilient coating and is used to strengthen the degree of crystallinity that is positioned at the layer that is used as device in the basic unit.Layer as device can be arranged in the basic unit, and perhaps basic unit can be used as device.First resilient coating is made by monocrystalline semiconductor.Substrate is specifically restriction and can contain SiC or made by sapphire not.When first resilient coating comprises Al
xGa
1-xN (0＜x≤1) and when having big thickness, especially under the situation of using AlN, first resilient coating has high-insulativity; Therefore can use conductive substrates for example Si substrate or n-type SiC substrate.
First resilient coating preferably has 100nm-20 μ m, the more preferably thickness of 150nm-15 μ m.Yet first resilient coating is not specifically limited on thickness, can use any thickness so that first resilient coating can have high-crystallinity.
The on-monocrystalline body of second resilient coating relates to amorphous body or polycrystal.The example of second resilient coating comprises the polycrystal semiconductor layer, and this polycrystal semiconductor layer forms amorphous semiconductor layer, at high temperature obtains in the mode of polycrystallization subsequently by utilizing crystal growth at low temperatures.Therefore, can to form the mode of common low temperature-grown buffer layer with being used for growing GaN crystalline solid on sapphire or SiC substrate identical for the generation type of second resilient coating.
In electronic device, first resilient coating preferably forms under 1000 ℃ of-1200 ℃ of temperature.First resilient coating forms by the mode that growth at high temperature has with the monocrystal semiconductor of the first resilient coating same composition usually.
Second resilient coating preferably 350-800 ℃, more preferably 400 ℃-750 ℃, more preferably form under 400 ℃-600 ℃ the temperature again.In order to allow second resilient coating to become the on-monocrystalline body, second resilient coating preferably forms under this temperature.If gained second resilient coating is non-monocrystal, then second resilient coating can form by high growth temperature method or sputtering method.
Second resilient coating preferably has the thickness of 5-20nm.
Advantage of the present invention is as described below.
In electronic device, as on-monocrystalline body (Al
yGa
1-yN; 0≤y≤1) second resilient coating is between first resilient coating and basic unit; Thereby may prevent between first resilient coating and basic unit, to form leakage current through its leakage path that flows, although leakage path may be present between the resilient coating and basic unit that is included in the conditional electronic device.Scheme as an alternative, the existence of second resilient coating may cause the sheet resistance of this leakage path effectively to increase.This allows electronic device to have high dielectric strength owing to reducing leakage current.Hereinafter, leakage current is called as the buffering leakage current under some situation.
If first resilient coating forms under 1000 ℃ of-1200 ℃ of temperature, then first resilient coating can the coverlet crystallization.
If second resilient coating forms, can prevent that then the second resilient coating coverlet crystallization and second resilient coating from can be non-monocrystal under 350 ℃ of-800 ℃ of temperature.
If substrate comprises SiC, then basic unit can have high-crystallinity, and this is because the GaN that is included in the basic unit has the lattice constant that approaches SiC.
If second resilient coating has the thickness of 5-20nm, then can prevent from not wish boundary effect (side-effect).If second resilient coating has very small thickness, then the thickness of second resilient coating can not accurately be controlled, thereby is heterogeneous.On the contrary, if second resilient coating has very big thickness, then the high-crystallinity of first resilient coating can not put in the basic unit and the flatness of second resilient coating poor; Therefore basic unit has low-crystallinity and/or difference flatness.This is not preferred.
Description of drawings
Fig. 1 is the sectional view according to the field-effect transistor of the electronic device example of first embodiment of the invention;
Fig. 2 is the graph of a relation that illustrates between the buffering leakage current that is applied to the included source electrode of each sample and voltage between the drain electrode and correspondence; With
Fig. 3 is the graph of a relation that illustrates between the half-peak breadth of X ray swing curve of the thickness of the second included resilient coating of each sample and sample.
Embodiment
Describe embodiment of the present invention now in detail.This embodiment should be considered as restrictive by any way.
Substrate preferably comprises SiC.SiC and GaN are incompatible.Therefore, if substrate comprises SiC, first resilient coating that then is positioned on the substrate preferably comprises the Al that mainly contains Al
xGa
1-xN (0＜x≤1), most preferably AlN.More preferably first and second resilient coatings all comprise AlN.
First embodiment
Fig. 1 illustrates the field-effect transistor 100 according to the electronic device example of first embodiment of the invention.Field-effect transistor 100 is the semiconductor device by deposition III family elements based nitride semiconductor fabrication.With reference to figure 1, second semiconductor crystal layer 109 that field-effect transistor 100 comprises crystalline growth substrate 101, first resilient coating 103, second resilient coating 105, do not mix first semiconductor crystal layer 107 and mix, these layers with above-mentioned arranged in order on crystal growth substrate 101.Crystal growth substrate 101 has the thickness of about 400 μ m and comprises SiC.First resilient coating 103 has the thickness of about 200nm and comprises AlN.
Second resilient coating 105 has the thickness of about 10nm and contains AlN.Following described in detail, confirmed that this device has good character when the thickness of second resilient coating 105 is 5-20nm.
First semiconductor crystal layer 107 has the thickness of about 2 μ m and comprises unadulterated GaN.Second semiconductor crystal layer 109 has the thickness of about 45nm and comprises by general formula Al
0.2Ga
0.8The not doped semiconductor of N representative.Second semiconductor crystal layer 109 is as the charge carrier accommodating layer.Second semiconductor crystal layer 109 can comprise by general formula Al
zGa
1-zThe semiconductor of N representative, wherein 0.15≤z≤0.20.
When gate turn-on, on the heterogeneous interface between first and second semiconductor crystal layers 107 and 109, produce the two-dimensional electron gas layer.The thickness of the second semiconductor junction crystal 109 (about 45nm) is enough little to reach the two-dimensional electron gas layer to allow electronics to be tunnelled to from following Ohmic electrode.
Field-effect transistor 100 also comprises ohm source electrode 115, Schottky (Schottky) type gate electrode 116 and ohm drain electrode 117, and these electrode arrangement are on second semiconductor crystal layer 109.Source and drain electrode 115 and 117 comprise the first metal layer that forms by vapour deposition separately and are formed on second metal level on the first metal layer by vapour deposition.The first metal layer contains titanium (Ti) and has the thickness of about 10nm.Second metal level contains Al and has the thickness of about 300nm.Source electrode and drain electrode 115 and 117 and second semiconductor crystal layer, 109 strong bonded or the alloying of its below, its method is to be no more than for 1 second by short annealing heat treatment source electrode and drain electrode 115 and 117 under about 700 ℃ of-900 ℃ of temperature.Gate electrode 116 comprises by the 3rd metal level of vapour deposition formation and the 4th metal level on the 3rd metal level.The 3rd metal level contains nickel (Ni) and has the thickness of about 10nm.The 4th metal level contains gold (Au) and has the thickness of about 300nm.
A kind of method of making field-effect transistor 100 is below described.
First and second resilient coating 103 and 105 and first and second semiconductor crystal layer 107 and 109 preferably by the vapor phase growth technology for example gas phase epitaxy of metal organic compound (MOVPE) form.The gas source that is used for forming these layers is the Gaseous Hydrogen (H as carrier gas
2) or nitrogen (N
2), gaseous ammonia (NH
3), gaseous state trimethyl gallium (Ga (CH
3)
3), gaseous state trimethyl aluminium (Al (CH
3)
3) etc.
The technical examples that is used to form these layers also comprises molecular beam epitaxy (MBE) and halide vapour phase epitaxy (HVPE) except that MOVPE.
The condition that forms these layers is as described below.
1. first resilient coating 103
(1) crystal growth temperature To:1140 ℃
(2) layer structure: (about 200nm is thick, AlN) for single layer structure
2. second resilient coating 105
(1) crystal growth temperature To:400 ℃
(2) layer structure: (about 10nm is thick, AlN) for single layer structure
3. first semiconductor crystal layer 107
(1) crystal growth temperature T
A: 1150 ℃
(2) layer structure: single layer structure (about 2 μ m are thick, unadulterated GaN)
4. second semiconductor crystal layer 109
(1) crystal growth temperature T
B: 1000 ℃
(2) layer structure: (about 45nm is thick, unadulterated Al for single layer structure
0.2Ga
0.8N)
Under these conditions, can form the layer that is included in the field-effect transistor shown in Figure 1 100.
Experiment 1
Prepare first sample, second sample, the 3rd sample and the 4th sample and comparative sample.First to fourth sample has and field-effect transistor shown in Figure 1 100 identical construction substantially, except not forming second semiconductor crystal layer 109.In these samples, source and leakage Ohmic electrode 115 and 117 directly are arranged on first semiconductor crystal layer 107 and do not form gate electrode.Therefore, can prevent unconditionally that raceway groove from being that the two-dimensional electron gas layer is formed on first semiconductor crystal layer 107 and does not apply grid voltage; Thereby leakage current does not depend on condition and the grid voltage that forms any second semiconductor crystal layer 109.These samples can be realized OFF state and not form depletion layer by applying grid voltage.Therefore, can realize the leakage current of the HEMT of accurate survey map 1.First sample comprises second resilient coating 105 that thickness is 5nm, second sample comprises second resilient coating 105 that thickness is 10nm, the 3rd sample comprises second resilient coating 105 that thickness is 15nm, it is that second resilient coating, 105, the five samples of 20nm are as not containing the comparative sample of second resilient coating 105 that the 4th sample comprises thickness.
Measure the leakage current of first to the 5th sample by the mode that between the source of each sample and drain electrode, applies voltage.The electrode of first to the 5th sample and layer have equal length on the y of Fig. 1 direction of principal axis.
Fig. 2 illustrates the relation between the source electrode that is applied to each sample and the voltage between the drain electrode and the corresponding buffering leakage current.In Fig. 2, the trunnion axis representative is applied to the voltage between source and the drain electrode, the buffering leakage current of vertical axis representative correspondence of unit length on the y of Fig. 1 direction of principal axis.In Fig. 2, square point (), triangulation point (△), hollow circling point (zero), solid circling point (zero) and Diamond spot (◇) are represented the buffering leakage current that flows in first sample, second sample, the 3rd sample, the 4th sample and the 5th sample respectively.
As can be seen from Figure 2, in the voltage range of 25-140V, the buffering leakage current that flows in embodiment of the invention HEMT (field-effect transistor 100) under the visible OFF state is very little, is about 0.2%-0.3% of leakage current mobile in the conventional field effect transistor.In addition, the buffering leakage current in first to fourth sample only with the source that is applied to the first and the 4th sample and the voltage between the drain electrode and slight the variation.On the contrary, as the leakage current in the prepared comparative sample that does not comprise second resilient coating of comparative example big and with the voltage between source that is applied to the 5th sample and the drain electrode acute variation.
As seen, the buffering leakage current when not forming second resilient coating in each chip changes, and the buffering leakage current in each chip does not change when forming second resilient coating.
This experiment shows in the field-effect transistor that the buffering leakage current that flows can be included in the thickness of second resilient coating in this field-effect transistor and reduces greatly by suitable control, and the dielectric strength of this field-effect transistor can be strengthened thus.
Experiment 2
Analyze first to the 5th sample by X-ray diffraction method.Particularly, check first semiconductor crystal layer 107 (002) plane and (100) plane after formation 2 μ m are thick that is included in each first to the 5th sample.
Fig. 3 illustrates the relation between the half-peak breadth of X ray swing curve of the thickness of sample one each second included resilient coating in the sample five and each sample.
In Fig. 3, trunnion axis is represented the thickness of second resilient coating 105, and vertical axis is represented the half-peak breadth of X ray swing curve.
As can be seen from Figure 3, first semiconductor crystal layer 107 of first sample that comprises thick second resilient coating 105 of 5nm is little with the difference of the 5th sample that does not comprise second resilient coating 105 aspect degree of crystallinity, although the difference of first sample and the 5th sample is very big aspect the buffering leakage current, as shown in Figure 2.This shows and is reducing do not have direct relation between leakage current and the degree of crystallinity as first semiconductor crystal layer 107 of basic unit by second resilient coating 105.
Other embodiment
The type of substrate used herein is not specifically limited.For example, if use dielectric substrate, then consider insulation, position first resilient coating thereon can have little thickness.Scheme as an alternative can be used following substrate: form the template substrate that the mode corresponding to the thick monocrystal AlN of the 10 μ m layer of described first resilient coating 103 of first embodiment prepares by utilize HVPE on n-type SiC substrate.Template substrate preferably has on-monocrystalline body second resilient coating of low temperature formation thereon.Scheme can use monocrystal AlN or AlGaN layer corresponding to first resilient coating 103 by forming on Sapphire Substrate to prepare template substrate as an alternative.This template substrate preferably has on-monocrystalline body second resilient coating of low temperature formation thereon.
In the first embodiment, first and second resilient coatings 103 and 105 all contain AlN.First resilient coating 103 can comprise the semiconductor based on III family element nitride that mainly contains aluminium.Second resilient coating 105 can comprise other III group-III nitride base semiconductor, and it must not comprise Al and its composition is arbitrarily.
Therefore because leakage current reduces to have high dielectric strength, be suitable for electronic equipment according to electronic device of the present invention, for example be used for the high-voltage operation amplifier of mobile telephone base station or high pressure, high-frequency electronic equipment.
Claims (12)
1. field-effect transistor prepares by the semiconductor crystal layer that utilizes crystal growth to form a plurality of III of containing family element nitride base semiconductor, and this field-effect transistor comprises:
Substrate;
Monocrystal first resilient coating that contacts with substrate, it comprises by general formula Al
xGa
1-xThe semiconductor of N representative, wherein 0＜x≤1;
Be positioned at on-monocrystalline body second resilient coating on first resilient coating, it comprises by general formula Al
yGa
1-yThe semiconductor of N representative, wherein 0≤y≤1;
Be positioned at the not doping basic unit on second resilient coating, it comprises GaN;
Be positioned at the unadulterated charge carrier accommodating layer in the basic unit of not mixing, it comprises Al
yGa
1-yN, wherein 0.15≤y≤0.2; With
Be positioned at source electrode, gate electrode and drain electrode on the unadulterated charge carrier accommodating layer.
2. according to the field-effect transistor of claim 1, wherein first resilient coating forms under 1000 ℃ of-1200 ℃ of temperature.
3. according to the field-effect transistor of claim 1, wherein second resilient coating forms under 350 ℃ of-800 ℃ of temperature.
4. according to the field-effect transistor of claim 2, wherein second resilient coating forms under 350 ℃ of-800 ℃ of temperature.
5. according to the field-effect transistor of claim 1, wherein substrate contains SiC.
6. according to the field-effect transistor of claim 2, wherein substrate contains SiC.
7. according to the field-effect transistor of claim 3, wherein substrate contains SiC.
8. according to the field-effect transistor of claim 1, wherein second resilient coating has the thickness of 5-20nm.
9. according to the field-effect transistor of claim 2, wherein second resilient coating has the thickness of 5-20nm.
10. according to the field-effect transistor of claim 3, wherein second resilient coating has the thickness of 5-20nm.
11. according to the field-effect transistor of claim 4, wherein second resilient coating has the thickness of 5-20nm.
12. according to the field-effect transistor of claim 5, wherein second resilient coating has the thickness of 5-20nm.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005280743 | 2005-09-27 | ||
| JP2005280743 | 2005-09-27 | ||
| JP2006168795 | 2006-06-19 |
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|---|---|
| CN1941408A CN1941408A (en) | 2007-04-04 |
| CN100470835C true CN100470835C (en) | 2009-03-18 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009295753A (en) | 2008-06-04 | 2009-12-17 | Showa Denko Kk | Method of manufacturing group iii nitride semiconductor light-emitting device and group iii nitride semiconductor light-emitting device, and lamp |
| US8680581B2 (en) * | 2008-12-26 | 2014-03-25 | Toyoda Gosei Co., Ltd. | Method for producing group III nitride semiconductor and template substrate |
| JP2015035534A (en) * | 2013-08-09 | 2015-02-19 | ルネサスエレクトロニクス株式会社 | Semiconductor device and semiconductor device manufacturing method |
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