CN100468687C - Method for filling isolation plough groove - Google Patents
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- CN100468687C CN100468687C CNB2006101191463A CN200610119146A CN100468687C CN 100468687 C CN100468687 C CN 100468687C CN B2006101191463 A CNB2006101191463 A CN B2006101191463A CN 200610119146 A CN200610119146 A CN 200610119146A CN 100468687 C CN100468687 C CN 100468687C
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Abstract
The invention relates to an isolation groove filling method which comprises the following steps that: a semiconductor substrate is provided; the surface of the substrate is provided with an isolation groove; at least a high-density plasma chemical vapor deposition technique and at least an etching technique are performed; insulating substance is deposited on the groove till the groove is filled in; the high-density plasma chemical vapor deposition technique with a first sputtering yield is continued to perform; a covering layer is deposited on the surface of the insulating substance; the high-density plasma chemical vapor deposition technique with a second sputtering yield is performed; another covering layer is also deposited on the surface of the covering layer; the second sputtering yield is greater than the first sputtering yield. The isolation groove filling method of the invention can increase the thickness of the insulating layer on the fringe field of a wafer after the wafer with large dimension is filled in the isolation groove, thereby improving the consistency and flatness of the insulating layer thickness of the central field and the fringe field of the wafer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of fill method of isolated groove.
Background technology
In semiconductor fabrication process, plasma has obtained using very widely.The generation of plasma is normally under environment under low pressure, in reative cell, feed reacting gas and introduce electron stream, utilize radio frequency (RF) electric field that electronics is quickened, electronics and gas molecule are bumped and shift kinetic energy, thereby make gas molecule generation ionization become plasma.The plasma that produces can be used for various semiconductor fabrication process, for example plasma etching, deposit etc.Application number is that 95307268.3 European patent discloses a kind of system that produces plasma, Fig. 1 is the existing system configuration rough schematic view that produces plasma, as shown in Figure 1, described system comprises reative cell 10, its inner bottom part is provided with chuck 50, chuck 50 surperficial placements need be carried out the wafer 60 of PROCESS FOR TREATMENT, have coil 20 at the top and the top of reative cell, and the radio-frequency voltage drive coil 20 generation rf electric fields of radio frequency power source 30 outputs excite reacting gas and are plasma 40.
Along with the densification and the miniaturization of IC device, all adopt shallow trench isolation between the semiconductor device active area from (shallow trench isolation, STI) structure is isolated and insulated.The formation of STI isolation structure at first forms cushion oxide layer (pad oxide) and silicon nitride layer at substrate surface, and etch silicon nitride, cushion oxide layer and substrate-like become groove then; Then form cushion oxide layer, utilize chemical vapor deposition (CVD) in shallow trench, to insert dielectric, for example silica again at trenched side-wall and bottom.After inserting dielectric, the megohmite insulant that utilizes the method for cmp (CMP) to grind above-mentioned filling makes the flute surfaces planarization.
After device feature size entered 65 nanometers and following process node, the depth-to-width ratio of isolated groove (Aspect Rate) was usually greater than 4.For the groove of high-aspect-ratio,, normally groove is filled at the processing step of the indoor deposit-etching that hockets of plasma reaction-deposit again in order to strengthen the filling capacity of groove.Fig. 2 A to Fig. 2 F is the device profile schematic diagram of the existing sti trench groove filling process of explanation.Shown in Fig. 2 A, at first etch groove 200, and form cushion oxide layer (lineroxide) (not shown) in flute surfaces at substrate 100; Then, shown in Fig. 2 B, silicon oxide deposition 300 in groove 200; Return the silica 300 of deposit in the ditch groove 200 subsequently, shown in Fig. 2 C; Continuation is silicon oxide deposition 300 in groove 200, shown in Fig. 2 D; And the silica 300 of this deposit of etching once more, shown in Fig. 2 E; Circulate several times like this, until described groove 200 is filled up, shown in Fig. 2 F.
The existing plasma reaction chamber that is used to handle 12 inches big circular slices is subjected to the influence of large area coil self inductance, and the uniform electromagnetic field degree of generation is inconsistent, and the electromagnetic field intensity that the mid portion of coil produces is greater than the electromagnetic field intensity of marginal portion.Be subjected to the influence of the energy dissipation that the collision of electronics and reaction chamber wall causes in addition, make the plasma of generation inconsistent in the density of zone line and marginal portion, the energy of plasma of zone line will be higher than the energy of plasma of marginal portion, the etching and the deposition rate that make plasma will be higher than fringe region to the etching and the deposition rate of central area.Because the capacity volume variance of above-mentioned plasma central area and fringe region, the plasma energy of Waffer edge part a little less than, along with hocketing of deposit and etching technics, material that Waffer edge is partially filled and the material that etches away all are less than wafer central region, therefore, after groove fills up, in wafer edge region spike 400 as shown in Fig. 2 F can appear, make the smooth degree difference of wafer edge region and central area bigger, brought more highly difficult for follow-up wafer planarization.
Summary of the invention
The object of the present invention is to provide a kind of fill method of isolated groove, at large-sized wafer after isolated groove is filled, the thickness of wafer edge region insulating barrier be can increase, thereby the central area of wafer and the consistency and the smooth degree of fringe region thickness of insulating layer improved.
For achieving the above object, the fill method of isolated groove provided by the invention comprises:
Semi-conductive substrate is provided, and described substrate surface has isolated groove;
Carry out first fill process, the deposition megohmite insulant fills up described groove until described megohmite insulant in described groove;
Carry out second fill process, at described megohmite insulant surface deposition one cover layer; And
Carry out the 3rd fill process, deposit another cover layer in described cover surface.
Described second fill process is the high-density plasma chemical vapor deposition method with first sputtering raste, and described the 3rd fill process is the high-density plasma chemical vapor deposition method with second sputtering raste.
Described technological parameter with high-density plasma chemical vapor deposition method of first sputtering raste comprises: rf bias power is 5700～6000W; The flow of hydrogen is 130～300sccm; The flow of oxygen is 180～250sccm.
Described technological parameter with high-density plasma chemical vapor deposition method of second sputtering raste comprises: rf bias power is 6700～8000W; The flow of hydrogen is 130～150sccm; The flow of oxygen is 180～200sccm.
Described first sputtering raste is
Described second sputtering raste is
Described first fill process comprises a high-density plasma chemical vapor deposition method and at least one etching technics at least.
The technological parameter of described depositing technics comprises: rf bias power is 3300～4000W; The flow of hydrogen is 130～200sccm; The flow of helium is 300～5000sccm; The flow of oxygen is 190～300sccm; The flow of silane is 50～150sccm.
The technological parameter of described etching technics comprises: rf bias power is 1100～2000W; Nitrogen fluoride NF
3Flow be 150～200sccm; The flow of hydrogen is 130～300sccm; The flow of helium is 120～200sccm.
Compared with prior art, the present invention has the following advantages:
The fill method of high-aspect-ratio isolated groove adopts HDP-CVD (high-density plasma chemical vapor deposition) technology to add original position (in suit) plasma etching industrial, deposit+sputter by above-mentioned process combination, etching, the processing step of deposit again can realize that the imporosity (void) to high aspect ratio trench quite is filled.Yet be subjected to the influence of the plasma uniformity that etching apparatus produces, the etching-deposition rate of the fringe region of large tracts of land wafer will be lower than the etching-deposition rate of central area.Therefore, utilize above-mentioned technology to fill isolated groove after, spike phenomenon can appear in the isolated groove top of wafer edge region, the thickness of the insulating barrier that fill the groove top will be lower than the groove top thickness of insulating layer of central area, causes the wafer flatness to descend.Isolated groove fill method of the present invention continues original position and carries out the HDP-CVD technology of a low sputtering raste and form a cover layer in wafer surface after carrying out above-mentioned technology HDP-CVD and adding the isolated groove that the original position plasma etching industrial fills up wafer surface; Owing to adopted the HDP-CVD technology of low sputtering raste, guaranteed forming the tectal while, groove top active area can not cause damage because of the corrasion of sputtering technology.Subsequently, carry out the HDP-CVD technology of a high sputtering raste again, form another layer cover layer in above-mentioned cover surface.In the tectal forming process of this layer, owing to used the HDP-CVD technology of high sputtering raste, make and forming the tectal while, the spike of wafer edge region is cut down in the corrasion meeting of sputtering technology significantly, cut down the material that falls and be filled between the spike, further improved the thickness of fringe region.
Method of the present invention has improved the smooth degree in wafer surface center and peripheral zone on the one hand by the HDP-CVD technology of different sputtering rastes of two steps, helps the planarization on subsequent wafer surface; On the other hand, increase the thickness of isolated groove top active area, improved the consistency of wafer central region and fringe region active area thickness, helped guaranteeing the consistency of wafer central region and fringe region device fabrication window.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing in proportion, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, amplified the thickness in layer and zone.
Fig. 1 is the existing system configuration rough schematic view that produces plasma;
Fig. 2 A to Fig. 2 F is the device profile schematic diagram of the existing sti trench groove filling process of explanation;
Fig. 3 A to Fig. 3 C is the generalized section of filling the wafer edge region isolated groove according to the preferred embodiment of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The invention relates to semiconductor integrated circuit manufacturing technology field, particularly about in fabrication of semiconductor device, filling the method for isolated groove.Here need to prove that this specification provides different embodiment that each feature of the present invention is described, but these embodiment utilize special The Nomenclature Composition and Structure of Complexes with convenient explanation, are not limitation of the invention.
Because the depth-to-width ratio of deep-submicron element groove is higher relatively, usually greater than 4.Therefore adopt high-density plasma CVD (Chemical Vapor Deposition) method (High-Density-Plasma CVD, HDP-CVD) add the original position etching technics and in groove, fill insulant, for example silica (can think insulant and silica in the following content of this paper implication and act on identical).HDP-CVD technology is in same reaction chamber, uses gases such as hydrogen that deposit uses with reacting gas and sputter, helium simultaneously, so that synchronously carry out deposit and sputter reaction.Therefore, HDP-CVD technology has the function of deposit and etching concurrently.Specifically, the depositing technics among the HDP-CVD is by silane (SiH
4) and oxygen (O
2) reaction realize that etch process then is by hydrogen (H
2) and the sputter of helium (He) be used for finishing.In the trench fill process, accumulation is dwindled open top along with the carrying out of deposit understood constantly at groove top deposit, influence the further deposition of deposited material, the deposited material that the sputter effect of carrying out synchronously will constantly accumulate etches away, deposition enters channel bottom again, thereby has avoided the generation of hole.The original position etching technics returns carves the megohmite insulant of filling, and groove is further opened, and helps follow-up megohmite insulant deposition.Here by Fig. 2 A to Fig. 2 F explanation said process.
Shown in Fig. 2 A to Fig. 2 F, described schematic diagram is an example, should too much not limit the scope of protection of the invention at this.After forming groove 200 on the substrate 100, carry out trench fill technology.The reacting gas that uses in the HDP-CVD technology comprises the reacting gas SiH that deposit is used
4And O2, and the gas H that uses of sputter
2And He.Helium (He) in the reative cell/hydrogen (H
2) wait the content influence sputtering raste of gas, O2 and SiH
4The content influence deposition rate.The effect that the ratio influence of sputtering raste and deposition rate is filled, and the ratio of sputtering raste and deposition rate and deposited gas SiH
4With O2 and sputter gas H
2With the content of He than relevant.Because deposit and sputtering technology are carried out SiH simultaneously
4With O2 and H
2Content to suitably adjust so that loading reaches best.In the HDP-CVD technology of present embodiment, by adjusting SiH
4With O2 and H
2Be 1:1 with the content of He so that sputtering deposit compares, this technology is applicable to the trench fill technology of high-aspect-ratio, can avoid the generation of top rake and hole phenomenon effectively, reaches best filling effect.
When utilizing HDP-CVD technology to fill silica 300, at first substrate is placed in the vacuum tank of reative cell, and form groove at substrate surface.Be provided with the conductivity partition wall in the vacuum tank of reative cell, the conductivity partition wall is two spaces with the vacuum tank internal insulation, it is that film forming is handled the space that an interior volume forms the plasma span, another space of having disposed radio frequency electrode, and internal configurations has the substrate maintaining body of carrying substrate.Above-mentioned conductivity partition wall has the stripped span and film forming such as makes to handle a plurality of through holes of spatial communication, and have with etc. the stripped span isolate, and pass through the inner space that a plurality of diffusion holes are communicated with film formation space.H
2Supply to from the outside the inner space of conductivity partition wall and material gas SiH with He
4Mix mutually, and be imported into film forming processing space, simultaneously with O by these a plurality of diffusion holes
2Feed the plasma span.Utilize radio frequency electrode that radio-frequency voltage is provided, the reative cell bottom provides rf bias power, in the plasma span, make O2 ionization generate high density oxygen atom plasma, by the plasma generation atomic group, a plurality of holes of this atomic group being passed above-mentioned partition wall import to film forming processing space, handle direct transfer material gas SiH in the space in film forming simultaneously
4(importing respectively) from the top and the side of reative cell.A plurality of holes that this plasma is passed above-mentioned partition wall import to film forming and handle the space, film forming handle this plasma discharge of space and with material gas SiH
4Carry out the chemical vapor deposition reaction, H
2With He and material gas SiH
4Carry out the sputter reaction, H
2Effect be the SiO that too much forms salient angle with deposit
2Reaction reduction again generates SiH
4Feed inert gas He simultaneously and protected, thereby deposit generates silicon oxide film on substrate.Handle space O in film forming
2And SiH
4The chemical equation that reaction generates silicon dioxide film is:
SiH
4+O
2＝SiO
2+H
2O
The scope of the basic technology parameter of above-mentioned HDP-CVD is listed in the table 1, sputtering deposit ratio and O
2/ SiH
4The content ratio can get by these basic technology parameter adjustments.
Table 1
| SiH 4Flow (top) | 20～50sccm |
| SiH 4Flow (side) | 50～150sccm |
| O 2Flow | 190～300sccm |
| H 2Flow | 130～200sccm |
| The He flow | 300～5000sccm |
| Radio-frequency power | 7000～8000W |
| Rf bias power | 3300～4000W |
The method of present embodiment filling groove is that HDP-CVD technology and etching technics hocket, and described etching technics is the original position etching, promptly after carrying out a HDP-CVD technology, continues to carry out etching technics in same reative cell.The purpose of etching is that the silica attenuate of will fill in the groove is so that the expansion groove opening is convenient to continue deposition.Original position was carried out after this etching technics depositing technics in reative cell finished, and depositing technics can be changed into etching technics by changing reaction condition.Adopt the etching gas of NF3 as silica in the present embodiment, its flow is 150～200sccm; Radio-frequency power is introduced from the top and the side of reative cell respectively, and the radio-frequency power of introducing from the top is 2000～3000W, and the radio-frequency power of introducing from the reative cell side is and 6000～7000W.Also will feed H2 and He simultaneously, flow is respectively 150～300sccm and 120～200sccm.
3～4 above-mentioned HDP-CVD technology of hocketing and original position etching technics can realize in isolated groove that just the imporosity fills.
Before address, inhomogeneous because of the plasma that equipment produced, the etching-deposition rate at the fringe region of large tracts of land wafer that causes will be lower than the etching-deposition rate of central area.Behind above-mentioned technology filling isolated groove, spike phenomenon can appear in the groove top of wafer edge region.The silicon oxide layer thickness that the groove top is filled is lower than groove top, central area silicon oxide layer thickness, causes the wafer flatness to descend.Isolated groove fill method of the present invention continues original position and carries out the HDP-CVD technology of twice different sputtering raste and form the cover layer of filling and leading up above-mentioned spike in wafer surface after carrying out above-mentioned technology HDP-CVD and adding the isolated groove that the original position plasma etching industrial fills up wafer surface.
Fig. 3 A to Fig. 3 C is the generalized section of filling the wafer edge region isolated groove according to the preferred embodiment of the present invention.Described schematic diagram is an example, should too much not limit the scope of protection of the invention at this.As shown in Figure 3A, for for simplicity, substrate 110 has comprised the silica of filling in unshowned groove and the groove.For the purpose of outstanding, with the configuration of surface of Waffer edge among the spike arranged side by side 400 presentation graphs 2F.Shown in Fig. 3 B, method of the present invention adopts the HDP-CVD technology with low sputtering raste in position, continue deposit one deck silica as cover layer 500 at the silicon oxide surface of filling, to fill the slit between the spike 400, the thickness of wafer edge region silicon oxide layer is increased, and the height of spike 400 also decreases.The HDP-CVD technology that adopts low sputtering raste is when forming cover layer, and the silicon oxide layer that the groove top will be used to form active area can not cause damage because of the corrasion of sputter.Above-mentioned HDP-CVD technology with low sputtering raste is carried out in same reative cell, in order to obtain required low sputtering raste, with the rf bias power setting of reative cell between 5700～6000W; H
2Flow control at 130～300sccm; The flow of He is 300～500sccm; O
2Flow be 180～250sccm; Deposited gas SiH
4The flow that feeds from the reative cell side is 100～200sccm, and the flow that feeds from the top is 10～20sccm.The sputtering raste that obtains by above-mentioned technological parameter is
Normal deposition rate makes the process of cvd silicon oxide become to take as the leading factor with lower sputter rate, a little less than the reduction effect relatively to spike in the time of formation cover layer 500.
Next shown in Fig. 3 C, continue in above-mentioned cover layer 500 surface deposition silica, to form cover layer 600 carrying out the HDP-CVD technology with high sputtering raste.In this process, owing to used the HDP-CVD technology of high sputtering raste, make forming the tectal while that spike 400 has been cut down in the corrasion of sputter significantly, cuts down the material that falls and continues to be filled between the spike, has further improved the thickness of fringe region.Above-mentioned HDP-CVD technology with high sputtering raste is also carried out in same reative cell, in order to obtain required high sputtering raste, with the rf bias power setting of reative cell between 6700～8000W; H
2Flow control at 130～150sccm; The flow of He is 300～500sccm; O
2Flow be 180～200sccm; Deposited gas SiH
4The flow that feeds from the reative cell side is 50～100sccm, and the flow that feeds from the top is 5～10sccm.The sputtering raste that obtains by above-mentioned technological parameter is
Normal deposition rate makes the process of etching spike 400 become to take as the leading factor with higher sputter rate, and the reduction effect to spike in the time of formation cover layer 600 strengthens greatly, and spike 400 is cut down significantly, has formed comparatively smooth cover layer 600.HDP-CVD technology by different sputtering rastes of two steps has improved the smooth degree in wafer surface center and peripheral zone on the one hand, helps the planarization on subsequent wafer surface; On the other hand, increased Waffer edge isolated groove top thickness of oxide layer, wafer central region and fringe region thickness of oxide layer are reached unanimity, described oxide layer helps guaranteeing the consistency of wafer central region and fringe region device fabrication window as the active area of follow-up formation device.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (7)
1, a kind of fill method of isolated groove comprises:
Semi-conductive substrate is provided, and described substrate surface has isolated groove;
Carry out first depositing technics, the deposition megohmite insulant fills up described groove until described megohmite insulant in described groove; It is characterized in that:
Continue to carry out second depositing technics, at described megohmite insulant surface deposition one cover layer, described second depositing technics is the high-density plasma chemical vapor deposition method with first sputtering raste; And
Carry out the 3rd depositing technics, deposit another cover layer in described cover surface, described the 3rd depositing technics is the high-density plasma chemical vapor deposition method with second sputtering raste, and described second sputtering raste is higher than first sputtering raste.
2, fill method according to claim 1 is characterized in that: described first sputtering raste is 500～600
Min; Described second sputtering raste is 850～950
Min.
3, fill method according to claim 1 and 2 is characterized in that: the technological parameter of described second depositing technics comprises: rf bias power is 5700～6000W; The flow of hydrogen is 130～300sccm; The flow of oxygen is 180～250sccm.
4, fill method according to claim 1 and 2 is characterized in that: the technological parameter of described the 3rd depositing technics comprises: rf bias power is 6700～8000W; The flow of hydrogen is 130～150sccm; The flow of oxygen is 180～200sccm.
5, fill method according to claim 1 is characterized in that: described first depositing technics comprises a high-density plasma chemical vapor deposition method and at least one etching technics at least.
6, fill method according to claim 5 is characterized in that: the technological parameter of described depositing technics comprises: rf bias power is 3300～4000W; The flow of hydrogen is 130～200sccm; The flow of helium is 300～5000sccm; The flow of oxygen is 190～300sccm; The flow of silane is 50～150sccm.
7, fill method according to claim 5 is characterized in that: the technological parameter of described etching technics comprises: rf bias power is 1100～2000W; Nitrogen fluoride NF
3Flow be 150～200sccm; The flow of hydrogen is 130～300sccm; The flow of helium is 120～200sccm.
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|---|---|---|---|
| CNB2006101191463A CN100468687C (en) | 2006-12-05 | 2006-12-05 | Method for filling isolation plough groove |
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| CN100468687C true CN100468687C (en) | 2009-03-11 |
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| CN102024741B (en) * | 2009-09-17 | 2013-03-27 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolation structure |
| CN102915948A (en) * | 2012-10-19 | 2013-02-06 | 上海宏力半导体制造有限公司 | Forming method of a shallow-groove isolation structure |
| CN110144556B (en) * | 2019-04-12 | 2020-08-21 | 北京北方华创微电子装备有限公司 | Method and device for filling sputtered thin film layer in groove |
| CN110211875B (en) * | 2019-06-06 | 2021-11-02 | 武汉新芯集成电路制造有限公司 | Method for manufacturing semiconductor device |
| CN113270394B (en) * | 2021-05-19 | 2024-01-23 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor device |
| CN114420632A (en) * | 2022-03-31 | 2022-04-29 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
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