CN100461298C - Memory - Google Patents
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- CN100461298C CN100461298C CNB2005101063598A CN200510106359A CN100461298C CN 100461298 C CN100461298 C CN 100461298C CN B2005101063598 A CNB2005101063598 A CN B2005101063598A CN 200510106359 A CN200510106359 A CN 200510106359A CN 100461298 C CN100461298 C CN 100461298C
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4061—Calibration or ate or cycle tuning
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4067—Refresh in standby or low power modes
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- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
A memory capable of performing a refresh operation without increasing current consumption is provided. This memory comprises a plurality of memory cells storing data, a delay circuit outputting a first address signal corresponding to the memory cells received from outside for a normal access operation with a delay of a prescribed period, a refresh control circuit outputting a second address signal corresponding to any of the memory cells subjected to a refresh operation of the data and a switching circuit switching and outputting the first address signal output from the delay circuit and the second address signal output from the refresh control circuit.
Description
Technical field
The present invention relates to a kind of storer, particularly suppress to carry out the storer of the renewal of the data of being preserved in the memory cell.
Background technology
In the past, as one of the storer of the more new element of the data of carrying out being preserved in memory cell example, DRAM (Dynamic Random Access Memory: be known dynamic RAM).This solid camera head, for example the spy opens the device of being announced in 2001-No. 229674 communiques.This spy opens among the DRAM in the past that is announced in 2001-No. 229674 communiques, synchronous with the 1st clock signal with given cycle, carry out common access action (reading action or write activity), simultaneously, synchronous with high speed the 2nd clock signal that the period demand of period ratio the 1st clock signal is short, carry out more new element,, between common access action, carry out more new element in existing free time by like this.In addition, in recent years, another example as the storer of the more new element of the data of carrying out being preserved in the memory cell has the caused emulation capacitance variations of a kind of polarised direction with strong dielectric, as the strong dielectric memory of memory component.In this strong dielectric memory, when rewrite action after the memory cell with ferro-electric materials capacitor being read action and write activity, owing to apply given voltage for the memory cell that is connected with selected word line word line in addition, and the amount of polarization that causes ferro-electric materials capacitor reduces, and this interference that causes data to disappear is known.In order to suppress such interference, in the strong dielectric memory in the past, carry out the more new element of the data of being preserved in the memory cell.
But, above-mentioned spy opens among the DRAM that is announced in 2001-No. 229674 communiques, because the 2nd clock signal of the high speed that life cycle employed the 1st clock signal when carrying out common access action is short is carried out more new element, therefore exists current sinking to increase this problem.In addition, even with the correlation technique of the more new element of the DRAM that announced in the above-mentioned patent documentation 1, be used for the more new element of strong dielectric memory, also can produce current sinking increases this same problem.
Summary of the invention
The present invention is in order to solve above-mentioned problem in the past, and one of purpose is to provide a kind of can carry out more new element, and the storer of the electric current that can not increase consumption.
To achieve these goals, the storer of the 1st aspect of the present invention possesses: a plurality of memory cells of storage data; Delay circuit, the 1st address signal that it will be imported from the outside when carrying out common access action corresponding to described memory cell, postpone given during and output; Upgrade control circuit, its output and corresponding the 2nd address signal of described memory cell that carries out the more new element of described data; And commutation circuit, it switches described the 1st address signal of exporting from described delay circuit, with described the 2nd address signal of being exported from described renewal control circuit and output, by in during described the 1st address signal of described delay circuit delays described given, export described the 2nd address signal from described commutation circuit, simultaneously, to carrying out described more new element with the corresponding described memory cell of described the 2nd address signal, described renewal control circuit, comprise the access times testing circuit that detects the access times of described memory cell, described renewal control circuit comprises the access time metering circuit of measurement to the access time of described memory cell.
The storer of the 1st aspect, as mentioned above, by the 1st address signal corresponding to memory cell that will import from the outside when carrying out common access action is set, postpone given during and the delay circuit of output, the renewal control circuit of corresponding the 2nd address signal of memory cell of output and the more new element of carrying out data, and switch from the 1st address signal of delay circuit output, with the commutation circuit of also exporting from the 2nd address signal that upgrades control circuit output, if in passing through the given period of delay circuit delays the 1st address signal, export the 2nd address signal from commutation circuit, simultaneously, with this corresponding memory cell of the 2nd address signal of exporting in carry out more new element, just can produce the free time that does not have common access action by delay circuit, and do not use at a high speed clock signal, simultaneously, in this free time, use and upgrade control circuit and commutation circuit, carry out more new element.By like this, can carry out more new element, and can not increase current sinking.
As optimal way, in the storer of above-mentioned the 1st aspect,, export the 2nd address signal from commutation circuit by in during delay circuit delays the 1st address signal given, simultaneously, to carrying out more new element with the corresponding memory cell of the 2nd address signal.If adopt such formation, just can carry out more new element easily by in the given period of delay circuit delays the 1st address signal.
In this case, many word lines and many bit lines of preferably also possessing the configuration of crossing one another; Memory cell is separately positioned on the position that many word lines and many bit lines intersect; By in during delay circuit delays the 1st address signal given, all memory cells that are connected with corresponding 1 word line of the 2nd address signal are carried out more new element.If adopt such formation, carrying out the more free time of new element in order to produce, and under the situation of delay control 1 address signal, as long as allow the 1st address signal, delay with all memory cells that 1 word line is connected in to carry out the time quantum of new element more just passable, therefore, can suppress the common access action with the corresponding memory cell of the 1st address signal is significantly postponed.
In addition, in this case, preferably allow more new element,, per 1 word line is being carried out successively during access action usually each time all word lines.If adopt such formation, owing to can carry out more new element successively to the memory cell that is connected with each word line, therefore each time usually during access action, easily all memory cells to being connected with all word lines carry out more new element.
As optimal way, in the storer of above-mentioned the 1st aspect, upgrade control circuit, comprise the access times testing circuit that detects the access times of memory cell; According to detect this item of the given number of times of amounting to of access times by the access times testing circuit, export the 2nd address signal from commutation circuit and replace the 1st address signal, it is responded, with the corresponding memory cell of the 2nd address signal in carry out more new element.Adopt such formation, if with above-mentioned given number of times, be set at and be used for avoiding the disappearance of data and carry out the more needed given access times of new element, then can be before the given access times that arrive the disappearance that produces data, therefore the beginning rewrite action can suppress the disappearance of the data of memory cell reliably.
As optimal way, in the storer of above-mentioned the 1st aspect, upgrade control circuit, comprise the access time metering circuit of measurement to the access time of memory cell; According to amounting to this item of given time by the measured access time of access time metering circuit, export the 2nd address signal from commutation circuit and replace the 1st address signal, it is responded, with the corresponding memory cell of the 2nd address signal in carry out more new element.Adopt such formation, if with the above-mentioned given time, be set at and be used for avoiding the disappearance of data and carry out the more needed given access time of new element, just can be before the given access time that arrives the disappearance that produces data, begin more new element, therefore can suppress the disappearance of the data of memory cell reliably.
As optimal way, in the storer of above-mentioned the 1st aspect, also has the address holding circuit that keeps and carry out corresponding the 1st address signal of memory cell of common access action; Delay circuit, the 1st address signal that the address holding circuit is kept postpones and output.If adopt such formation, because can will be at the 1st address signal that begins to be imported before the new element more by the address holding circuit, keep in during new element more, therefore can pass through delay circuit reliably, with the 1st address signal of being imported before more new element begins, more exporting after the new element.
As optimal way, in the storer of above-mentioned the 1st aspect, delay circuit comprises a plurality of delay circuit portion that is connected in series; A plurality of delay circuit portion allows respectively the 1st address signal is each to postpone 1 clock amount and output, by like this, by delay circuit with the 1st address signal postpone given during and output.If adopt such formation, just can be easily by delay circuit with the 1st address signal postpone given during and output.
As optimal way, in the storer of above-mentioned the 1st aspect, commutation circuit comprises the 1st transistor that is transfused to from the 1st address signal of delay circuit, and the 2nd transistor that comes the 2nd address signal of self refresh control circuit; When common access action, the 1st transistor becomes conducting state, and simultaneously, the 2nd transistor becomes cut-off state, by like this, exports the 1st address signal through the 1st transistor; When new element more, the 1st transistor becomes cut-off state, and simultaneously, the 2nd transistor becomes conducting state, by like this, exports the 2nd address signal through the 2nd transistor.If adopt such formation,, easily when common access action and more during new element, switch output the 1st address signal and the 2nd address signal just can pass through commutation circuit.
As optimal way, in the storer of above-mentioned the 1st aspect, also have many word lines and many bit lines of the configuration of crossing one another; Memory cell is configured in respectively on the position corresponding to the point of crossing of many word lines and many bit lines, simultaneously, has with corresponding word lines and corresponding bit lines and is connected the ferro-electric materials capacitor of storage data.If adopt such formation,, be provided with the intersection point type strong dielectric memory of the memory cell that has ferro-electric materials capacitor respectively just can be formed on the intersection point of many word lines and many bit lines.By like this, in the intersection point type strong dielectric memory,, therefore can in the intersection point type strong dielectric memory, carry out more new element, and not increase current sinking owing to can in the free time that delay circuit produced, carry out more new element.
As optimal way, in the storer of above-mentioned the 1st aspect, also possess many word lines and many bit lines of the configuration of crossing one another; Memory cell, be configured in respectively on the position corresponding to the point of crossing of many word lines and many bit lines, and having grid is connected with corresponding word lines, simultaneously, the transistor that a side in the source/drain is connected with corresponding bit lines, and one side's electrode be connected the opposing party's electrode grounding simultaneously, the capacitor of storage data with the opposing party in the transistorized source/drain.If adopt such formation, comprise the capacitor of storing data just can constitute to have, and the DRAM that is used for selecting the transistorized memory cell of this capacitor.By like this, in DRAM,, therefore can in DRAM, carry out more new element, and not increase current sinking owing to can in the free time that delay circuit produced, carry out more new element.
The storer of the 2nd aspect of the present invention has: many word lines and many bit lines of the configuration that crosses one another; Memory cell, it is configured in respectively on the position corresponding to the point of crossing of many word lines and many bit lines, simultaneously, has with corresponding word lines and corresponding bit lines and is connected the ferro-electric materials capacitor of storage data; Delay circuit, the 1st address signal that it will be imported from the outside when carrying out common access action corresponding to memory cell, postpone given during and output; Upgrade control circuit, its output and corresponding the 2nd address signal of memory cell that carries out the more new element of data; And commutation circuit, it switches from the 1st address signal of delay circuit output, with the 2nd address signal and output from upgrading control circuit output, by in during described the 1st address signal of described delay circuit delays described given, export described the 2nd address signal from described commutation circuit, simultaneously, to carrying out described more new element with the corresponding described memory cell of described the 2nd address signal, described renewal control circuit, comprise the access times testing circuit that detects the access times of described memory cell, described renewal control circuit comprises the access time metering circuit of measurement to the access time of described memory cell.
The storer of the 2nd aspect, as mentioned above, by on the point of crossing of many word lines and many bit lines, be provided with in the intersection point type strong dielectric memory of the memory cell that has ferro-electric materials capacitor respectively, the 1st address signal corresponding to memory cell that to import from the outside when carrying out common access action is set, postpone given during and the delay circuit of output, the renewal control circuit of corresponding the 2nd address signal of memory cell of output and the more new element of carrying out data, and switch from the 1st address signal of delay circuit output, with the commutation circuit of also exporting from the 2nd address signal that upgrades control circuit output, if in passing through the given period of delay circuit delays the 1st address signal, export the 2nd address signal from commutation circuit, simultaneously, with this corresponding memory cell of the 2nd address signal of exporting in carry out more new element, just can produce the free time that does not have common access action by delay circuit, and do not use at a high speed clock signal, simultaneously, in this free time, use and upgrade control circuit and commutation circuit, carry out more new element.By like this, can in the intersection point type strong dielectric memory, carry out more new element, and can not increase current sinking.
As optimal way, in the storer of above-mentioned the 2nd aspect,, export the 2nd address signal from commutation circuit by in during delay circuit delays the 1st address signal given, simultaneously, to carrying out more new element with the corresponding memory cell of the 2nd address signal.If adopt such formation, just can carry out more new element easily by in the given period of delay circuit delays the 1st address signal.
In this case, be preferably in, all memory cells that are connected with corresponding 1 word line of the 2nd address signal are carried out more new element by in during delay circuit delays the 1st address signal given.If adopt such formation, carrying out the more free time of new element in order to produce, and under the situation of delay control 1 address signal, as long as allow the 1st address signal, delay with all memory cells that 1 word line is connected in to carry out time of new element more just passable, therefore, can suppress the common access action with the corresponding memory cell of the 1st address signal is significantly postponed.
In addition, in this case, preferably allow more new element,, per 1 word line is being carried out successively during access action usually each time all word lines.If adopt such formation, owing to can carry out more new element successively to the memory cell that is connected with each word line, therefore each time usually during access action, easily all memory cells to being connected with all word lines carry out more new element.
As optimal way, in the storer of above-mentioned the 2nd aspect, upgrade control circuit, comprise the access times testing circuit that detects the access times of memory cell; According to detect this item of the given number of times of amounting to of access times by the access times testing circuit, export the 2nd address signal from commutation circuit and replace the 1st address signal, it is responded, with the corresponding memory cell of the 2nd address signal in carry out more new element.Adopt such formation, if with above-mentioned given number of times, be set at and be used for avoiding the disappearance of data and carry out the more needed given access times of new element, just can be before the given access times that arrive the disappearance that produces data, therefore the beginning rewrite action can suppress the disappearance of the data of memory cell reliably.
As optimal way, in the storer of above-mentioned the 2nd aspect, upgrade control circuit, comprise the access time metering circuit of measurement to the access time of memory cell; According to amounting to this item of given time by the measured access time of access time metering circuit, export the 2nd address signal from commutation circuit and replace the 1st address signal, it is responded, with the corresponding memory cell of the 2nd address signal in carry out more new element.Adopt such formation, if with the above-mentioned given time, be set at and be used for avoiding the disappearance of data and carry out the more needed given access time of new element, just can be before the given access time that arrives the disappearance that produces data, begin more new element, therefore can suppress the disappearance of the data of memory cell reliably.
As optimal way, in the storer of above-mentioned the 2nd aspect, also has the address holding circuit that keeps and carry out corresponding the 1st address signal of memory cell of common access action; Delay circuit, the 1st address signal that the address holding circuit is kept postpones and output.If adopt such formation, because can will be at the 1st address signal that begins to be imported before the new element more by the address holding circuit, keep in during new element more, therefore can pass through delay circuit reliably, with the 1st address signal of being imported before more new element begins, more exporting after the new element.
As optimal way, in the storer of above-mentioned the 2nd aspect, delay circuit comprises a plurality of delay circuit portion that is connected in series; A plurality of delay circuit portion allows the 1st address signal postpone 1 clock amount and output successively respectively, by like this, by delay circuit with the 1st address signal postpone given during and output.If adopt such formation, just can be easily by delay circuit with the 1st address signal postpone given during and output.
As optimal way, in the storer of above-mentioned the 2nd aspect, commutation circuit comprises the 1st transistor that is transfused to from the 1st address signal of delay circuit, and the 2nd transistor that comes the 2nd address signal of self refresh control circuit; When common access action, the 1st transistor becomes conducting state, and simultaneously, the 2nd transistor becomes cut-off state, by like this, exports the 1st address signal through the 1st transistor; When new element more, the 1st transistor becomes cut-off state, and simultaneously, the 2nd transistor becomes conducting state, by like this, exports the 2nd address signal through the 2nd transistor.If adopt such formation,, easily when common access action and more during new element, switch output the 1st address signal and the 2nd address signal just can pass through commutation circuit.
Description of drawings
Fig. 1 is the block diagram of all formations of the intersection point type strong dielectric memory of expression the 1st embodiment of the present invention.
Fig. 2 is the block diagram of the formation of the renewal control circuit, clock forming circuit and the row address buffer memory that are used for the intersection point type strong dielectric memory of the 1st embodiment shown in the key diagram 1.
Fig. 3 is the circuit diagram of circuit structure of renewal control circuit, clock forming circuit and the row address buffer memory of the 1st embodiment shown in the key diagram 2.
Fig. 4 is the voltage oscillogram of the action of the intersection point type strong dielectric memory of explanation the 1st embodiment of the present invention.
Fig. 5 is the block diagram of the integral body formation of the intersection point type strong dielectric memory of expression the 2nd embodiment of the present invention.
Fig. 6 is the block diagram of the integral body formation of the DRAM of the variation of explanation the 2nd embodiment of the present invention.
Embodiment
The contrast accompanying drawing describes embodiments of the present invention below.In addition, in the explanation of following embodiment, to one of storer of the present invention example, only to describing by being arranged on the point type strong dielectric memory that intersects that locational 1 ferro-electric materials capacitor that word line and bit line intersect constitutes memory cell.
(the 1st embodiment)
At first, with reference to Fig. 1～Fig. 3, the formation of the intersection point type strong dielectric memory of the 1st embodiment of the present invention is described.
The intersection point type strong dielectric memory of the 1st embodiment, as shown in Figure 1, possess memory cell array 1, row decoder 2, comprise counter 3 and address with renewal control circuit 5, the row address buffer memory 6 of counter 4, the clock forming circuit 8 that comprises state machine circuit 7, column address buffer memory 9, write amplifier 10, sensor amplifier (read amplifier) 11, input-buffer 12, output buffers 13, column decoder 14, word line source driver 15, voltage generation circuit 16, detecting amplifier (sense amplifier) 17 and bit line Source drive 18.In addition, counter 3 is one of " access times testing circuit " of the present invention example.
In the memory cell array 1,, simultaneously, the memory cell 20 that only is made of single ferro-electric materials capacitor 19 is set on each crossover location with many word line WL and many bit line BL setting that intersects.In addition, ferro-electric materials capacitor 19, include word line WL, bit line BL and be arranged on word line WL and bit line BL between the strong dielectric film (not shown).In addition, word line WL is connected with row decoder 2.In addition, row decoder 2 is connected with row address buffer memory 6.
Here, in the 1st embodiment, upgrade control circuit 5, be used for controlling to the Data Update action of memory cell 20 and be set up.In addition, upgrade the counter 3 of control circuit 5, be used for detecting the access times of all included in the memory cell array 1 memory cells 20 are set up.Specifically, counter 3, each to memory cell array 1 in all included memory cells 20 carry out common access action or more during new element, just carry out+1 counting.In addition, upgrade control circuit 5, this item of given number of times that amounts to the access times that detect counter 3 responds, will as with scheduler signal, the update request signal REFE of H level, the counter-rotating update request signal/REFE of L level of the row address that carries out the word line WL that the memory cell 20 of new element more is connected, export to the commutation circuit 23 of row address buffer memory 6 described later.In addition, the address of upgrading control circuit 5 is with counter 4, is used for detecting the number of times of word line WL more new element each time and is set up.Also promptly, the address is with counter 4, at every turn when given word line WL carries out more new element, will count corresponding to number of times+1 of the more new element of this given word line WL.
In addition, row address buffer memory 6 is used for given row address signal is provided and is set up to row decoder 2.Row decoder 2 at common access action and more in the new element, is used for the corresponding word line WL of given row address signal that row address buffer memory 6 is provided to activate.In addition, row address buffer memory 6 as shown in Figure 2, is made of address latch circuit 21, delay circuit 22 and commutation circuit 23.In addition, this address latch circuit 21 is one of " address holding circuit " of the present invention example.In addition, address latch circuit 21 when carrying out common access action, is imported external address signal from the outside to it, the external address signal that keeps this to import simultaneously.In addition, address latch circuit 21 as shown in Figure 3, is made of 1 DFF (delayed-trigger) circuit 21a.Among the dff circuit 21a of this address latch circuit 21, imported internal clock signals from clock forming circuit 8.
In addition, in the 1st embodiment, delay circuit 22 is connected with address latch circuit 21, is transfused to the external address signal (carrying out the row address of the word line WL of common access action) that is kept by address latch circuit 21 simultaneously.In addition, delay circuit 22 is made of 3 sections dff circuit 22a～22c that are connected in series.In addition, this dff circuit 22a～22c is one of " delay circuit portion " of the present invention example.In addition, among each section dff circuit 22a～22c, be transfused to clock signal clk respectively.In addition, each section dff circuit 22a～22c has the function that allows external address signal postpone 1 clock amount respectively.By like this, delay circuit 22, the external address signal that will be imported from address latch circuit 21 postpones 3 clock amounts and output by 3 sections dff circuit 22a～22c.
In addition, commutation circuit 23 is made of two transmission gate transistor 23a and 23b.In addition, transmission gate transistor 23a is one of " the 1st transistor " of the present invention example, and in addition, transmission gate transistor 23b is one of " the 2nd transistor " of the present invention example.In addition, transmission gate transistor 23a and 23b are made of interconnected p channel transistor of source/drain and n channel transistor respectively.In addition, side in the source/drain of one side's transmission gate transistor 23a of commutation circuit 23, be delayed circuit 22 input external address signals, simultaneously, side in the source/drain of the opposing party's transmission gate transistor 23b, by from upgrading control circuit 5, input as with the scheduler signal of the row address that carries out the word line WL that the memory cell 20 of new element more is connected.In addition, the opposing party in the source/drain of transmission gate transistor 23a is connected with the opposing party in the source/drain of transmission gate transistor 23b.In addition, the grid of the n channel transistor of transmission gate transistor 23a is transfused to access request signal ACCE, and simultaneously, the grid of the p channel transistor of transmission gate transistor 23a is transfused to counter-rotating access request signal/ACCE.In addition, the grid of the n channel transistor of transmission gate transistor 23b is transfused to update request signal REFE, and simultaneously, the grid of p channel transistor is transfused to counter-rotating update request signal/REFE.
In addition, side from the source/drain of transmission gate transistor 23a, with the either party among the side in the source/drain of transmission gate transistor 23b, the either party with external address signal or scheduler signal exports to row decoder 2 as inner row address signal.Also be, commutation circuit 23, allowing transmission gate transistor 23a be in conducting state, simultaneously, allowing transmission gate transistor 23b be under the situation of cut-off state, through transmission gate transistor 23a output external address signal, in addition, allowing transmission gate transistor 23b be in conducting state, simultaneously, allow transmission gate transistor 23a be under the situation of cut-off state, through transmission gate transistor 23b output scheduler signal.By like this, commutation circuit 23 can switch in the external address signal of importing from the outside when carrying out common access action, and carries out the more corresponding scheduler signal of the memory cell 20 of new element, exports.
In addition, clock forming circuit 8 comprises inverter circuit 8a and 8b, and NAND circuit 8c.Inverter circuit 8a is transfused to rwo address strobe signals RAS.In addition, NAND circuit 8c is transfused to the output of clock signal clk and inverter circuit 8a.In addition, inverter circuit 8b is transfused to the output of NAND circuit 8c.Like this, export internal clock signals from inverter circuit 8b to address latch circuit 21.In addition, clock forming circuit 8 and upgrades control circuit 5, column address buffer memory 9, writes amplifier 10 and sensor amplifier 11 is connected as shown in Figure 1.In addition, write amplifier 10 and sensor amplifier 11, be connected with input-buffer 12 and output buffers 13 respectively.In addition, column address buffer memory 9 is connected with column decoder 14.In addition, row decoder 2 is connected with word line source driver 15, and simultaneously, word line source driver 15 is connected with the state machine circuit 7 of voltage generation circuit 16 and clock forming circuit 8.In addition, the bit line BL of memory cell array 1, amplifier 17 is connected with column decoder 14 after testing.In addition, detecting amplifier 17 and writes amplifier 10, sensor amplifier 11 and bit line Source drive 18 and is connected, and simultaneously, bit line Source drive 18 is connected with voltage generation circuit 16 and state machine circuit 7.
Next, contrast Fig. 1～Fig. 4 describes the action of the intersection point type strong dielectric memory of the 1st embodiment of the present invention.In addition, the action of the intersection point type strong dielectric memory of the 1st embodiment is carried out synchronously with 1 clock signal clk importing from the outside.
At first, as shown in Figure 4, the rwo address strobe signals RAS to the inverter circuit 8a of clock forming circuit 8 (with reference to Fig. 3) is imported drops to the L level from the H level.By like this,, simultaneously, the signal of this H level is inputed to NAND circuit 8c from the signal of inverter circuit 8a output H level.In addition, drop to the L level, upgrade the counter 3 of control circuit 5 (with reference to Fig. 1), carry out+1 counting corresponding to rwo address strobe signals RAS.By like this, detect access times by counter 3.Afterwards, in case the clock signal clk of NAND circuit 8c that inputs to clock forming circuit 8 (with reference to Fig. 3) from the L electrical level rising to the H level, just from the signal of NAND circuit 8c output L level.In addition, allow when this rwo address strobe signals RAS is the L level, clock signal clk is from the moment of L level to the H electrical level rising, is access action zero hour.Afterwards, the signal by the L level that will be exported from NAND circuit 8c inputs to inverter circuit 8b, comes from the internal clock signal of inverter circuit 8b output H level.The internal clock signal of this H level inputs to the dff circuit 21a of address latch circuit 21.By like this, address latch circuit 21 keeps the external address signal XA that imports from the outside this moment.
Afterwards, by the external address signal XA that address latch circuit 21 is kept, input to the 1st section dff circuit 22a of delay circuit 22.External address signal XA is postponed 1 clock and output respectively by 3 sections dff circuit 22a～22c.By like this,, external address signal XA is postponed 3 clocks and output the zero hour from access action by the 3rd section dff circuit 22c.By the external address signal XA that dff circuit 22 postpones 3 clocks and output, be imported into the side in the source/drain of transmission gate transistor 23a of commutation circuit 23.At this moment, allow the access enable signal ACCE of grid of the n channel transistor that inputs to transmission gate transistor 23a, rise to the H level, simultaneously, allow the counter-rotating access enable signal/ACCE of grid of the p channel transistor that inputs to transmission gate transistor 23a, drop to the L level.By like this, because transmission gate transistor 23a is a conducting state, therefore, the external address signal XA from delay circuit 22 is exported exports through transmission gate transistor 23a.Therefore, from commutation circuit 23, will input to row decoder 2 (with reference to Fig. 1) corresponding to the inner row address signal XA of external address signal XA.
Afterwards,, activate word line WL corresponding to inner row address signal XA by row decoder 2, simultaneously, through bit line BL with memory cell 20 that word line WL that this has activated is connected in carry out common access action (reading action and write activity).Usually reading in the action of access action, will with the data of being stored in all memory cells 20 that the word line WL that has activated is connected, BL reads in the lump through bit line.In addition, this is read in the action, owing to produced the ruined memory cell 20 of data, therefore after reading action, carries out rewrite action.In this rewrite action, amplified by detecting amplifier 17 after the voltage of the data of being read, through bit line BL the voltage that is amplified has been imposed on the ferro-electric materials capacitor 19 of the former memory cell 20 that data are read out, by carrying out the rewriting of data like this.In addition, usually in the write activity of access action, through bit line BL with all memory cells 20 that the word line WL that has activated is connected in write data in the lump.
In addition, from transmission gate transistor 23a output external address signal XA the time, allow the update request signal REFE of grid of n channel transistor of the opposing party's transmission gate transistor 23b of inputing to commutation circuit 23, drop to the L level, simultaneously, allow the counter-rotating update request signal/REFE of grid of the p channel transistor that inputs to transmission gate transistor 23b, rise to the H level.By like this, transmission gate transistor 23b becomes cut-off state.Therefore, when the side's transmission gate transistor 23a from commutation circuit 23 exports external address signal XA, can be from the opposing party's transmission gate transistor 23b output scheduler signal.
In addition, externally address signal XA postpone 3 clocks during, the access enable signal ACCE of grid that inputs to the n channel transistor of transmission gate transistor 23a remains the L level, simultaneously, the counter-rotating access enable signal/ACCE of grid that inputs to the p channel transistor of transmission gate transistor 23a remains the H level.By like this because transmission gate transistor 23a remain off state, therefore externally address signal XA postpone 3 clocks during in, can be from the transmission gate transistor 23a of commutation circuit 23 to row decoder 2 input inner row address signals.In addition, in this period, wait for the internal column address signal corresponding to external address signal XA, (with reference to Fig. 1) inputs to column decoder 14 from column address buffer memory 9.Therefore, in this period, produced the free time of not carrying out common access action.
In the 1st embodiment, utilize to allow said external address signal XA postpone 3 free times that clock produced, carry out more new element memory cell 20.In addition, more new element access times amount to given number of times the time carry out.Specifically, when detecting the given number of times of amounting to of access times by the counter 3 that upgrades control circuit 5, in access action zero hour, from upgrading control circuit 5 outputs and carrying out more memory cell 20 corresponding scheduler signal RA, the update request signal REFE of H level, the counter-rotating update request signal/REFE of L level of new element.In addition, at this moment, the total of the access times that the counter 3 that upgrades control circuit 5 is counted is reset to " 0 ".Like this, the grid n channel transistor of transmission gate transistor 23b of commutation circuit 23 that is transfused to the update request signal REFE of H level becomes conducting state.In addition, the grid p channel transistor of transmission gate transistor 23b of commutation circuit 23 that has been transfused to the counter-rotating overwrite request signal/REFE of L level becomes conducting state.Therefore because scheduler signal RA is through transmission gate transistor 23b output, therefore from commutation circuit 23 to row decoder 2, input is corresponding to the inner row address signal RA of scheduler signal RA.By like this, will activate corresponding to 1 word line WL of inner row address signal RA by row decoder 2, all memory cells 20 to being connected simultaneously with 1 word line WL that this has activated, BL upgrades through bit line.
In addition, more in new element and the common access action read action and rewrite action is the same carries out.Also promptly, will with the data of being stored in all memory cells 20 that the 1 word line WL that has activated is connected, BL reads in the lump through bit line, simultaneously, amplifies the voltage of the data of being read by detecting amplifier 17.Afterwards, through bit line BL the voltage that is amplified is imposed on the ferro-electric materials capacitor 19 of the former memory cell 20 that data are read out, by carrying out the rewriting of data like this.Come the data of being preserved in the updated stored device unit 20 like this.This is new element more, carries out respectively in the free time that each access action produced usually, simultaneously, per 1 word line WL of the radical amount of word line WL included in the memory cell array 1 is carried out successively.In addition, when carrying out more new element, by the counter 3 that upgrades control circuit 5 access times+1 is counted, simultaneously at every turn, address by upgrading control circuit 5 is with counter 4, will carry out more number of times+1 of the pairing more new element of word line WL of new element and count.Afterwards, all memory cells 20 that are connected of included and all word line WL in the memory cell array 1 are carried out more new element.Afterwards, all memory cells 20 that are connected with all word line WL have been carried out more the address of upgrading control circuit 5 being reset to " 0 " with counter 4 after the new element.Afterwards, repeat common access action once more.Upgrade the counter 3 of control circuit 5,, calculate with the number of times addition of carrying out common access action once more with the number of times of above-mentioned more new element.Afterwards, carry out common access action and do not carry out more new element, up to the more new element of being counted by the counter 3 that upgrades control circuit 5 and usually the number of times of access action amount to given number of times.
In the 1st embodiment, as mentioned above, be provided with: when carrying out common access action, the external address signal XA that will import from the outside postpones and the delay circuit 22 of output, export with the renewal control circuit 5 of the memory cell 20 corresponding rewriting address signal RA of the more new element of carrying out data, suitably switch the external address signal XA that exported from delay circuit 22 with from upgrading scheduler signal RA that control circuit 5 exported and the commutation circuit of exporting 23; Simultaneously, by delay circuit 22 external address signal XA is postponed 3 clocks during in, by with the corresponding memory cell of being exported from commutation circuit 23 20 of scheduler signal RA (internal address signal RA) carry out more new element, can be by delay circuit 22, do not use clock signal at a high speed, and produce the free time that does not have common access action, in this free time, use simultaneously and upgrade control circuit 5 and commutation circuit 23, carry out more new element.By like this, can carry out more new element, and can not increase current sinking.
In addition, in the 1st embodiment, according to detect the given number of times of amounting to of access times by counter 3,23 output scheduler signal RA replace external address signal XA from commutation circuit, simultaneously, with memory cell 20 that the pairing word line WL of this scheduler signal RA is connected in carry out more new element, by like this, if with above-mentioned given number of times, be set at and be used for avoiding the disappearance of data and carry out the more needed given access times of new element, then can before the given access times that arrive the disappearance that produces data, begin more new element.By like this, can suppress the disappearance of the data of memory cell 20 reliably.
(the 2nd embodiment)
Next, with reference to Fig. 5, the formation of the intersection point type strong dielectric memory of the 2nd embodiment of the present invention is described.
The intersection point type strong dielectric memory of the 2nd embodiment, as shown in Figure 5, with above-mentioned the 1st embodiment to intersect point type strong dielectric memory different, use timer 33 replaces the counter 3 (with reference to Fig. 1) of the 1st embodiment in upgrading control circuit 5.In addition, this timer 33 is one of " access time metering circuit " of the present invention example.In addition, timer 33 is used for measuring the access time to memory cell 19.In addition, upgrade control circuit 5,,, export to row decoder 2 the update request signal REFE of scheduler signal RA, H level, the counter-rotating update request signal/REFE of L level according to arriving the given time by the 33 measured access times of timer.Formation outside the intersection point type strong dielectric memory of the 2nd embodiment above-mentioned, with above-mentioned the 1st embodiment to intersect the formation of point type strong dielectric memory identical.
Next, contrast Fig. 3～Fig. 5 describes the action of the intersection point type strong dielectric memory of the 2nd embodiment of the present invention.In the intersection point type strong dielectric memory of the 2nd embodiment, different with above-mentioned the 1st embodiment, by upgrading the timer 33 of control circuit 5, detect and carry out the more moment of new element.Also promptly, timer 33 is measured the access time, and this measured time of accumulative total.By the measured access time of timer 33 amount to the given access time time, identical with the situation of the 1st embodiment shown in Fig. 4, in access action zero hour, from upgrading control circuit 5 outputs and carrying out more memory cell 20 corresponding scheduler signal RA, the update request signal REFE of H level, the counter-rotating update request signal/REFE of L level of new element.By like this, the same with the 1st embodiment shown in Fig. 3, because the transmission gate transistor 23b of commutation circuit 23 becomes conducting state, so scheduler signal RA (inner row address signal RA) exports to row decoder 2 (with reference to Fig. 5) through transmission gate transistor 23b.Therefore,, activate 1 word line WL, simultaneously,, all memory cells 20 that are connected with 1 word line WL that this has activated are carried out more new element through bit line BL corresponding to inner row address signal RA by row decoder 2.In addition, when the total by the measured access time of timer 33 arrives the given time, will be reset to " 0 " by timer 33 total of measured access time.Afterwards, timer 33 with time of new element more, calculates with the time addition of all memory cells 20 being carried out carry out once more after the new element more common access action.Afterwards, by the measured more new element of timer 33 and when the time of access action amounts to the given access time usually, carry out more new element once more.
Action beyond the intersection point type strong dielectric memory of the 2nd embodiment above-mentioned, with above-mentioned the 1st embodiment to intersect the action of point type strong dielectric memory identical.
In the 2nd embodiment, as mentioned above, arrive the given time according to total by the measured access time of timer 33,23 output scheduler signal RA replace external address signal from commutation circuit, simultaneously, to upgrading operation with the corresponding memory cell 20 of this scheduler signal RA, by like this, if with the above-mentioned given time, be set at and be used for avoiding the disappearance of data and carry out the more needed given access time of new element, then can be before the given access time that arrives the disappearance that produces data, the beginning rewrite action.By like this, can suppress the disappearance of the data of memory cell 20 reliably.
In addition the effect of the 2nd embodiment is identical with the effect of above-mentioned the 1st embodiment.
In addition, the embodiment that this is announced is example and can not limits the invention.Scope of the present invention is announced by the scope of claim rather than the explanation of above-mentioned embodiment, and comprises meaning that the scope with claim is equal to and all changes in the scope.
For example, in the above-mentioned embodiment, be illustrated as one of storer of the present invention example with strong dielectric memory, but the present invention is not limited to this, also can be suitable for the present invention for the storer beyond the strong dielectric memory.For example, in the DRAM shown in Fig. 6, also can be suitable for the present invention.Among this DRAM shown in Figure 6, different with above-mentioned the 2nd embodiment, a plurality of memory cells 60 of formation memory cell array 41 are made of capacitor 59a and n channel transistor 59b respectively.In addition, n channel transistor 59b is one of " transistor " of the present invention example.In addition, side's electrode of capacitor 59a is connected with a side in the source/drain of n channel transistor 59b, simultaneously, and the opposing party's electrode grounding.In addition, the opposing party in the source/drain of n channel transistor 59b, BL is connected with bit line, simultaneously, and the grid of n channel transistor 59b, WL is connected with word line.Formation beyond DRAM shown in Fig. 6 above-mentioned is identical with the formation of the strong dielectric memory of above-mentioned the 2nd embodiment.
In addition, in above-mentioned the 1st embodiment, the example that the external address signal of being imported to will carry out common access action the time postpones 3 clocks is illustrated, but the present invention is not limited to this, can also allow external address signal postpone clock number beyond 3 clocks.
In addition, in above-mentioned the 1st embodiment, by upgrading the counter of control circuit, with more the number of times of new element and the number of times addition of common access action are counted, but the present invention is not limited to this, can also only count the number of times of common access action by upgrading the counter of control circuit, and the number of times of count update action not.
In addition, in above-mentioned the 1st embodiment, by upgrading the timer of control circuit, with more the time of new element measures with the time addition of common access action, but the present invention is not limited to this, can also only measure the time of common access action by upgrading the timer of control circuit, and not measure the time of upgrading action.
Claims (17)
1. storer is characterized in that possessing:
A plurality of memory cells of storage data;
Delay circuit, the 1st address signal that it will be imported from the outside when carrying out common access action corresponding to described memory cell, postpone given during and output;
Upgrade control circuit, its output and corresponding the 2nd address signal of described memory cell that carries out the more new element of described data; And
Commutation circuit, it switches described the 1st address signal of exporting from described delay circuit, with described the 2nd address signal of being exported from described renewal control circuit and output,
By in during described the 1st address signal of described delay circuit delays described given, export described the 2nd address signal from described commutation circuit, simultaneously, to carrying out described more new element with the corresponding described memory cell of described the 2nd address signal,
Described renewal control circuit comprises the access times testing circuit that detects the access times of described memory cell,
Described renewal control circuit comprises the access time metering circuit of measurement to the access time of described memory cell.
2. storer as claimed in claim 1 is characterized in that:
Many word lines and many bit lines of also possessing the configuration of crossing one another;
Described memory cell is separately positioned on the position that many described word lines and many described bit lines intersect;
By in during described the 1st address signal of described delay circuit delays described given, all described memory cells that are connected with the corresponding 1 described word line of described the 2nd address signal are carried out described more new element.
3. storer as claimed in claim 2 is characterized in that:
Described more new element to all described word lines, is carried out every described word line when described common access action each time successively.
4. storer as claimed in claim 1 is characterized in that:
According to detect this item of the given number of times of amounting to of described access times by described access times testing circuit, export described the 2nd address signal from described commutation circuit and replace described the 1st address signal, it is responded, with the corresponding described memory cell of described the 2nd address signal in carry out described more new element.
5. storer as claimed in claim 1 is characterized in that:
According to amounting to this item of given time by the measured described access time of described access time metering circuit, export described the 2nd address signal from described commutation circuit and replace described the 1st address signal, it is responded, with the corresponding described memory cell of described the 2nd address signal in carry out described more new element.
6. storer as claimed in claim 1 is characterized in that:
Also possess the address holding circuit, it keeps and corresponding described the 1st address signal of described memory cell that carries out described common access action.
7. storer as claimed in claim 1 is characterized in that:
Described delay circuit comprises a plurality of delay circuit portion that is connected in series;
Described a plurality of delay circuit portion allows respectively described the 1st address signal is each to postpone 1 clock amount and output, by like this, by described delay circuit will described the 1st address signal postpone described given during and export.
8. storer as claimed in claim 1 is characterized in that:
Described commutation circuit comprises the 1st transistor that is transfused to from described the 1st address signal of described delay circuit, and from the 2nd transistor of described the 2nd address signal of described renewal control circuit;
When described common access action, described the 1st transistor becomes conducting state, and simultaneously, described the 2nd transistor becomes cut-off state, by like this, exports described the 1st address signal through described the 1st transistor;
When described more new element, described the 1st transistor becomes cut-off state, and simultaneously, described the 2nd transistor becomes conducting state, by like this, exports described the 2nd address signal through described the 2nd transistor.
9. storer as claimed in claim 1 is characterized in that:
Many word lines and many bit lines of also having the configuration of crossing one another;
Described memory cell, be configured in respectively on the position corresponding to the point of crossing of many described word lines and many described bit lines, and have: grid is connected with corresponding described word line, simultaneously, and the transistor that the side in the source/drain is connected with corresponding described bit line; And one side's electrode be connected with the opposing party in the described transistorized source/drain, the opposing party's electrode grounding is stored the capacitor of described data simultaneously.
10. storer is characterized in that possessing:
Many word lines and many bit lines of crossing one another and disposing;
A plurality of memory cells, it is configured in respectively on the position corresponding to the point of crossing of many described word lines and many described bit lines, simultaneously, comprises with corresponding described word line and corresponding described bit line being connected the ferro-electric materials capacitor of storage data;
Delay circuit, the 1st address signal that it will be imported from the outside when carrying out common access action corresponding to described memory cell, postpone given during and output;
Upgrade control circuit, its output and corresponding the 2nd address signal of described memory cell that carries out the more new element of described data; And
Commutation circuit, it switches from described the 1st address signal of described delay circuit output, with described the 2nd address signal and output from described renewal control circuit output,
By in during described the 1st address signal of described delay circuit delays described given, export described the 2nd address signal from described commutation circuit, simultaneously, to carrying out described more new element with the corresponding described memory cell of described the 2nd address signal,
Described renewal control circuit comprises the access times testing circuit that detects the access times of described memory cell,
Described renewal control circuit comprises the access time metering circuit of measurement to the access time of described memory cell.
11. storer as claimed in claim 10 is characterized in that:
By in during described the 1st address signal of described delay circuit delays described given, all described memory cells that are connected with the corresponding 1 described word line of described the 2nd address signal are carried out described more new element.
12. storer as claimed in claim 11 is characterized in that:
Described more new element to all described word lines, is carried out every described word line when described common access action each time successively.
13. storer as claimed in claim 10 is characterized in that:
Described renewal control circuit comprises the access times testing circuit that detects the access times of described memory cell;
According to detect this item of the given number of times of amounting to of described access times by described access times testing circuit, export described the 2nd address signal from described commutation circuit and replace described the 1st address signal, it is responded, with the corresponding described memory cell of described the 2nd address signal in carry out described more new element..
14. storer as claimed in claim 10 is characterized in that:
Described renewal control circuit comprises the access time metering circuit of measurement to the access time of described memory cell;
According to amounting to this item of given time by the measured described access time of described access time metering circuit, export described the 2nd address signal from described commutation circuit and replace described the 1st address signal, it is responded, with the corresponding described memory cell of described the 2nd address signal in carry out described more new element.
15. storer as claimed in claim 10 is characterized in that:
Also possess the address holding circuit, it keeps and corresponding described the 1st address signal of described memory cell that carries out described common access action.
16. storer as claimed in claim 10 is characterized in that:
Described delay circuit comprises a plurality of delay circuit portion that is connected in series;
Described a plurality of delay circuit portion allows respectively described the 1st address signal is each to postpone 1 clock amount and output, by like this, by described delay circuit will described the 1st address signal postpone described given during and export.
17. storer as claimed in claim 10 is characterized in that:
Described commutation circuit comprises the 1st transistor that is transfused to from described the 1st address signal of described delay circuit, and from the 2nd transistor of described the 2nd address signal of described renewal control circuit;
When described common access action, described the 1st transistor becomes conducting state, and simultaneously, described the 2nd transistor becomes cut-off state, by like this, exports described the 1st address signal through described the 1st transistor;
When described more new element, described the 1st transistor becomes cut-off state, and simultaneously, described the 2nd transistor becomes conducting state, by like this, exports described the 2nd address signal through described the 2nd transistor.
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| US6964950B2 (en) * | 2001-07-25 | 2005-11-15 | Isis Pharmaceuticals, Inc. | Antisense modulation of C-reactive protein expression |
| JP4608235B2 (en) * | 2004-04-14 | 2011-01-12 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device and semiconductor memory system |
| KR100567064B1 (en) * | 2004-04-28 | 2006-04-04 | 주식회사 하이닉스반도체 | Input circuir for a memory device |
| JP4714590B2 (en) | 2006-01-23 | 2011-06-29 | パトレネラ キャピタル リミテッド， エルエルシー | memory |
| JP4195899B2 (en) | 2006-06-16 | 2008-12-17 | 三洋電機株式会社 | Ferroelectric memory |
| JP4272227B2 (en) | 2006-06-16 | 2009-06-03 | 三洋電機株式会社 | Memory and control unit |
| CN101089992B (en) * | 2006-06-16 | 2012-09-05 | 帕特兰尼拉财富有限公司 | Memory |
| JP2008108417A (en) * | 2006-10-23 | 2008-05-08 | Hynix Semiconductor Inc | Low power dram and its driving method |
| JP2009271991A (en) * | 2008-05-07 | 2009-11-19 | Toshiba Corp | Semiconductor storage device |
| CN105448321B (en) * | 2014-08-20 | 2018-12-18 | 华邦电子股份有限公司 | The access method of memory |
| CN110390976B (en) * | 2018-04-19 | 2021-06-08 | 华邦电子股份有限公司 | Memory device and data updating method thereof |
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| KR100682436B1 (en) | 2007-02-15 |
| CN1770321A (en) | 2006-05-10 |
| JP2006092640A (en) | 2006-04-06 |
| US20060067151A1 (en) | 2006-03-30 |
| KR20060051561A (en) | 2006-05-19 |
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