CN100456451C - 三维混合取向技术的结构和方法 - Google Patents

三维混合取向技术的结构和方法 Download PDF

Info

Publication number
CN100456451C
CN100456451C CNB2006100086489A CN200610008648A CN100456451C CN 100456451 C CN100456451 C CN 100456451C CN B2006100086489 A CNB2006100086489 A CN B2006100086489A CN 200610008648 A CN200610008648 A CN 200610008648A CN 100456451 C CN100456451 C CN 100456451C
Authority
CN
China
Prior art keywords
substrate
plane
pfet
lamination
nfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2006100086489A
Other languages
English (en)
Other versions
CN1845309A (zh
Inventor
權五正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Google LLC
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1845309A publication Critical patent/CN1845309A/zh
Application granted granted Critical
Publication of CN100456451C publication Critical patent/CN100456451C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

具有增强的pFET性能且不会降低nFET的性能的半导体器件以及制造方法。该方法包括使用第一平面和方向在基片上形成第一结构和使用第二平面和方向在该基片上形成第二结构。在使用中，该结构包括：使用第一平面和方向(例如(100)/<110>)在基片上形成的nFET叠层；和使用不同于第一平面和方向的第二平面和方向(例如(111)/<112>)在该基片上形成pFET叠层。在所述nFET叠层和pFET叠层之间设有该基片内的隔离区。

Description

三维混合取向技术的结构和方法
技术领域
本发明涉及半导体器件，更具体地说，涉及具有增强的pFET性能且不会降低nFET的性能的半导体器件以及制造方法。
背景技术
场效应晶体管(FET)是集成电路领域中的基本构造块。FET可以分为两种基本结构类型：水平和垂直。水平或横向FET具有在平行于基片的平面的方向(例如水平方向)上从源极到漏极的载流子流，而垂直FET具有在与在其上形成源漏极的基片的平面相垂直的方向上从源极到漏极的载流子流。FET结构可以包括单个栅极(例如用于形成单个沟道)或者一对栅极(例如用于形成一对沟道)，双栅极的形式的优点在于增加了电流传输能力(例如通常大于单栅极形式的两倍)。
FET通常由通过半导体材料互连的源极和漏极电极组成。在源极和漏极电极之间的导通基本在半导体内，在源极和漏极之间的长度是导通沟道。具体地，输出电流与沟道长度成反比，而工作频率与沟道长度的平方成反比。
基本金属氧化物半导体场效应晶体管(MOSFET)结构具有所谓的“扁平设计”。nFET结构是四端子器件，并且由p型半导体基片构成，在该基片中形成了两个n-区、源极电极和漏极电极(例如通过离子注入)。在绝缘体上的金属触点是栅极。重掺杂的多晶硅或者硅化物和多晶硅的组合也可用作栅极电极。
基本器件参数是作为在两种冶金的n-p结之间的距离的通道长度L、沟道宽度W、栅极氧化物厚度t、结深度和基片掺杂。在电压施加给栅极时，源极至漏极电极对应于背对背连接的两个p-n结。仅仅从源极可流到漏极的电流是反向漏极电流。在足够的正偏压施加给栅极以在两个n-区之间形成表面反型层(或沟道)时，通过有电流流过的n-沟道的导通表面来连接源极和漏极。
然而公知的是nFET在基片的水平面上最佳。即，在nFET被制造在100平面和110方向时使在沟道上的电子迁移率最佳。这时典型的扁平结构制造。在另一方面，pFET器件在被制造在100平面和110方向上时具有显著降低的性能特征；即空穴迁移率极大地降低，由此使整个器件的性能劣化。然而，在半导体制造中通常使用十分公知的处理在100平面和110方向上构造nFET和pFET两种结构。
发明内容
在本发明的第一方面，一种制造半导体结构的方法包括：使用第一平面和第一方向在基片上形成第一结构；使用第二平面和第二方向在该基片上形成第二结构；在第一结构和第二结构之间形成隔离区，其中形成第二结构的步骤包括蚀刻基片以形成带角度的侧壁并至少部分地在带角度的侧壁上构造第二结构。
在本发明的另一方面中，一种制造半导体器件的方法包括使用第一平面和第一方向在基片上构造nFET叠层和使用不同于第一平面和第一方向的第二平面和第二方向在该基片上构造pFET叠层。该方法进一步包括在nFET叠层和pFET叠层之间的基片上提供隔离区。其中形成pFET叠层的步骤包括蚀刻基片以形成具有带角度的侧壁的沟槽并且至少部分地在带角度的侧壁上构造pFET叠层。
在本发明的另一方面中，一种半导体结构包括使用第一平面和第一方向在基片上的nFET叠层和使用不同于第一平面和第一方向的第二平面和第二方向在该基片上的pFET叠层。基片内的隔离区提供在nFET叠层和pFET叠层之间。其中pFET叠层至少部分地形成于在该基片中形成的沟槽的带角度的侧壁上。
附图说明
附图1-15说明了在根据本发明在半导体器件中的步骤；和
附图16说明了根据本发明的最终结构和制造过程。
具体实施方式
本发明涉及半导体结构，更具体地说涉及使用三维混合取向技术的半导体结构和制造方法。在本发明的一方面，通过增大pFET的载流子迁移率改善或最佳化pFET的性能，而对nFET的性能没有任何损害。为实现本发明，nFET形成在第一平面/方向上，而使用类似的处理步骤将pFET形成在第二平面/方向上。例如，在本发明的一个非限制性的方面中，nFET将形成在(100)/<110>平面/方向上，而pFET将形成在(111)/<112>平面/方向上。这样，pFET的沟道长度比使用相同的处理的nFET的沟道长度更长。本发明与CMOS技术比如SOI、应变Si、双间隔件等兼容。
附图1所述为根据本发明的开始结构。在这种结构，浅沟槽隔离结构(STI)12形成在具有(100)平面的基片10中。在一个示例性附图中，STI 12的深度在2000
Figure C20061000864800071
-5000
Figure C20061000864800072
之间，这取决于所要求的器件性能。STI 12的深度在SOI处理技术中可以更浅。在所描述的实施例中，nFET将形成在STI 12的侧面上，而pFET将形成在STI 12的相对侧面上。
通过示例性的说明，STI 12可以通过在基片10上淀积衬垫氧化物和衬垫氮化物形成。光掩模或硬掩模形成在衬垫氮化物上，并且蚀刻处理蚀刻穿过所形成的层到达基片上。附加的蚀刻处理蚀刻进基片以形成沟槽。例如，氧化物淀积在沟槽中以填充该沟槽。使用化学机械抛光(CMP)处理使表面平面化。然后清除衬垫氮化物，得到附图1的结构。
附图2表示阱注入过程。在一种实施方式中，p-阱使用硼掺杂，之后形成nFET的一部分。可以以磷对n-阱掺杂，之后形成pFET的一部分。使用在本行业十分公知的过程执行掺杂。
在附图3中，使用十分公知的处理比如热氧化或者化学汽相淀积将氧化物材料14形成在基片10上。在本发明的一方面，氧化物层14大约10
Figure C20061000864800081
至100厚，但本发明也可以设计其它的厚度或尺寸。使用CVD也可以将块材料16比如氮化物淀积在氧化物层14上，例如块材料16可以是200
Figure C20061000864800083
至2000
Figure C20061000864800084
的范围，虽然本发明也可以使用其它的厚度和尺寸。光致抗蚀剂18淀积在块材料16上。在构图之后，仅仅pFET区域打开以用于随后的各向异性蚀刻。
附图4表示块材料16的有选择性的各向异性蚀刻。在这个处理中，蚀刻对于氮化物块层16有选择性，而氧化物层14用作蚀刻停止层。在这个过程中，蚀刻区域20形成在块材料16中。
然后使用干剥离处理剥离光致抗蚀剂层18，例如(附图5).在附图6中，执行间隔件氮化物淀积和蚀刻处理。在这个处理中，间隔件22形成在蚀刻的区域20中以减小间隔件并使要形成pFET的活性区域平滑。如果蚀刻的区域20通过在附图3中的光刻处理可控制则可以跳过形成间隔件氮化物。
参考附图7，然后例如使用湿蚀刻处理清除在蚀刻的区域20中的氧化物层14。这种湿蚀刻处理例如可以利用稀释的HF。然后使用例如KOH或氨水在基片中执行优选的蚀刻处理。这种蚀刻步骤是各向异性的蚀刻，在非限制性的实施例中，蚀刻到200
Figure C20061000864800085
至900
Figure C20061000864800086
的深度，虽然根据器件的要求本发明可以设计其它的蚀刻深度和尺寸。在本发明的一方面中，形成沟槽24的蚀刻区域具有STI 12的平滑过渡；然而，本发明可以设计在STI 12和蚀刻的沟槽24之间存在阶梯的部分。
附图8所示为如参考附图7所讨论的蚀刻几何的一种实施例。在这种非限制性的实施例中，各向异性的湿蚀刻被用于在基片100中蚀刻，形成相对于基片10的平面(100)具有大约57.5°角度的侧壁24a。
在附图9中，使用十分公知的热磷酸蚀刻清除氮化物块材料16。十分公知的是，热磷酸仅仅蚀刻氮化物而不损失氧化物和硅。可以清除氧化物层14。
参考附图10，在氮化物块和氧化物层的蚀刻之后，栅极电介质26形成在基片10的表面上，包括在沟槽24中。栅极电介质26例如可以是氧化物、氮氧化物或高-k材料。在一个实例中，栅极电介质26可以是大约10
Figure C20061000864800091
至100
Figure C20061000864800092
多晶硅28淀积在栅极电介质26上。在高-k材料的情况下，金属电极可以淀积在高-k材料上。
附图11所示为nFET和pFET的开始结构(例如叠层)的构造。在这种处理中，多晶硅28以十分公知的处理(比如光刻和多晶硅RIE)被蚀刻。正如本领域普通技术人员所理解，STI12可用作pFET叠层的对准的基础，即确保pFET叠层的构造形成在成一定角度的侧壁24a上。这样，pFET叠层28a形成在(111)平面和<112>方向上；而nFET28b叠层将同时形成在(100)平面和<110>方向上。
附图12所示为间隔件30的形成。根据特定的要求，间隔件30可以是氮化物或氧化物。间隔件30以本领域普通技术人员十分公知的方法形成，以致在此为完整地理解本发明无需对其做进一步的讨论。作为附图13的步骤的代表，执行延伸注入。在这种处理中，可以给nFET注入磷或砷，而给pFET注入硼。
附图14表示分别在pFET和nFET的叠层28a和28b的侧面上间隔件32的构造的代表实例。为改善器件的性能，也可以设计不同的材料分别被用作28a和28b。对于nFET具有拉伸应力的一些氮化物和对于pFET具有压缩应力的其它氮化物都将是这些实例中的一种。在本发明的一种非限制性方面，间隔件32使用本领域普通技术人员十分公知的方法通过氮化物形成，这种方法公知到以致为完整地理解本发明无需对其做进一步的讨论。附图15表示nFET和pFET的源极/漏极构造。此外，形成源极/漏极区的处理对于本领域技术人员来说是十分公知的，这种方法公知到以致为完整地理解本发明无需对其做进一步的讨论。
附图16所示为根据本发明的器件的最终结构。在附图16中，金属触点34形成到nFET和pFET的源极/漏极区。在一种示例性的处理中，RIE处理被用于对层间电介质35和栅极电介质进行蚀刻。然后淀积金属以填充接触孔，例如钨。作为一种示例性的实例，TiN可用于在钨淀积之前在源极/漏极和金属触点之间形成阻挡材料。如附图16所表示，除了剩余的叠层构造步骤之外，由于在附图6中形成的蚀刻步骤的结果，所得的pFET叠层形成在(111)平面，并且载流子传输方向是<112>方向。此外，nFET叠层形成在(100)平面，并且载流子传输方向是<110>方向。
已经发现pFET的空穴迁移率在(111)平面和<112>方向上优于在(100)平面和<110>方向上，但差于在(110)平面和<110>方向上；而nFET的电子迁移率在(111)平面和<112>方向上差于在(100)平面和<110>方向上，但优于在(110)平面和<110>方向上。因此，在本发明中，为使pFET性能最佳而不降低nFET性能，pFET形成在(111)平面和<112>方向上，而nFET在(100)平面和<110>方向上最佳。
虽然根据示例性的实施例已经描述了本发明，但是本领域的普通技术人员会认识到在附加的权利要求的精神和范围内可以对本发明进行修改。

Claims (16)

1.一种制造半导体结构的方法，包括：
使用第一平面和第一方向在基片上形成第一结构；
使用第二平面和第二方向在该基片上形成第二结构；以及
在第一结构和第二结构之间形成隔离区，
其中形成第二结构的步骤包括蚀刻基片以形成带角度的侧壁并至少部分地在该带角度的侧壁上构造第二结构，
其中形成带角度的侧壁的步骤包括：蚀刻在基片上淀积的氧化物层上淀积的块材料，穿过该氧化物层，并进入基片。
2.权利要求1所述的方法，其中第一结构是nFET的叠层，而第二结构是pFET的叠层。
3.权利要求1所述的方法，其中第一平面和第一方向不同于第二平面和方向，但第一结构和第二结构同时形成。
4.权利要求3所述的方法，其中第一平面是(100)平面，第一方向是<110>方向，而第二平面是(111)平面，第二方向是<112>方向。
5.权利要求1所述的方法，其中形成带角度的侧壁的步骤包括在pFET的活性区域上对基片的各向异性蚀刻。
6.权利要求1所述的方法，其中形成带角度的侧壁的步骤包括蚀刻基片以得到与基片的平面成57.5度的角度。
7.权利要求6所述的方法，其中蚀刻在基片上淀积的氧化物层上淀积的块材料、穿过该氧化物层、并进入基片的步骤进一步包括：
蚀刻在块材料上淀积的光致抗蚀剂，
使用氧化物层作为蚀刻停止层执行块材料的选择性蚀刻以形成经蚀刻的区域；
剥离光致抗蚀剂层；
在经蚀刻的区域中形成第一间隔件；和
将基片各向异性蚀刻到200至900的深度以在具有带角度的侧壁的基片中形成沟槽。
8.权利要求1所述的方法，其中形成第一结构和第二结构的步骤包括：
至少形成分别用于pFET和nFET器件的一个n-阱和一个p-阱；
将栅极电介质淀积在基片的表面上，包括在沟槽中，该沟槽具有相对于基片表面的平面成角度的侧壁，并且该沟槽形成在pFET的活性区域中；
将多晶硅层淀积在栅极电介质上；
蚀刻部分多晶硅层以形成包括在基片表面的平面上的第一结构的nFET叠层和包括在沟槽的带角度的侧壁上的第二结构的pFET叠层；
在nFET叠层和pFET叠层的侧壁上形成第二间隔件；和
分别在nFET叠层和pFET叠层的侧面上对基片中nFET和pFET器件的源极区和漏极区进行掺杂。
9.权利要求8所述的方法，其中pFET叠层在(111)平面和<112>方向上，而nFET叠层在(100)平面和<110>方向上。
10.一种制造半导体器件的方法，包括：
在基片上在第一平面和第一方向上构造nFET叠层；
在该基片上在不同于第一平面和第一方向的第二平面和第二方向上构造pFET叠层；和
在该基片内在nFET叠层和pFET叠层之间提供隔离区，
其中形成pFET叠层的步骤包括蚀刻基片以形成具有带角度的侧壁的沟槽并且至少部分地在带角度的侧壁上构造pFET叠层，
其中形成带角度的侧壁的步骤包括：蚀刻在基片上淀积的氧化物层上淀积的块材料，穿过该氧化物层，并进入基片。
11.权利要求10所述的方法，其中第一平面是(100)平面，第一方向是<110>方向，第二平面是(111)平面，第二方向是<112>方向。
12.权利要求10所述的方法，其中形成带角度的侧壁的步骤包括在pFET的活性区域处使用基础湿化学物对基片进行各向异性蚀刻。
13.如权利要求12所述的方法，其中所述基础湿化学物是KOH或氨水。
14.权利要求10所述的方法，其中带角度的侧壁以与基片的平面成57.5度的角度被蚀刻。
15.权利要求10所述的方法，其中其中蚀刻在基片上淀积的氧化物层上淀积的块材料、穿过该氧化物层、并进入基片的步骤包括：
通过在基片上淀积的氧化物层并使用该氧化物层作为蚀刻停止层对淀积在氧化物层上的块材料进行蚀刻以形成经蚀刻的区域；
在蚀刻块材料之后剥离淀积在该块材料上的光致抗蚀剂；
在经蚀刻的区域中形成第一间隔件；和
使用湿化学物各向异性蚀刻基片到200至900
Figure C2006100086480004C2
的深度以在具有带角度的侧壁的基片中形成沟槽。
16.权利要求10所述的方法，其中形成nFET叠层和pFET叠层的步骤包括：
至少形成分别用于pFET和nFET器件的一个n-阱和一个p-阱；
将栅极电介质淀积在基片的表面上，包括在沟槽中，该沟槽具有相对于基片表面的平面成角度的侧壁，并且该沟槽形成在pFET的活性区域中；
将多晶硅层淀积在栅极电介质上；
使用隔离区作为对准的基础，蚀刻部分多晶硅层，以在基片表面的平面上形成nFET叠层，并在沟槽的带角度的侧壁上形成pFET叠层；
在nFET叠层和pFET叠层的侧壁上形成第二间隔件；
在nFET叠层和pFET叠层的侧面上对基片中的延伸区实施注入；和
分别在所述nFET叠层和pFET叠层的侧面上对基片中nFET和pFET的源极区和漏极区掺杂。
CNB2006100086489A 2005-04-08 2006-02-20 三维混合取向技术的结构和方法 Expired - Fee Related CN100456451C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/907,622 US7288821B2 (en) 2005-04-08 2005-04-08 Structure and method of three dimensional hybrid orientation technology
US10/907,622 2005-04-08

Publications (2)

Publication Number Publication Date
CN1845309A CN1845309A (zh) 2006-10-11
CN100456451C true CN100456451C (zh) 2009-01-28

Family

ID=37064236

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006100086489A Expired - Fee Related CN100456451C (zh) 2005-04-08 2006-02-20 三维混合取向技术的结构和方法

Country Status (2)

Country Link
US (2) US7288821B2 (zh)
CN (1) CN100456451C (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007220734A (ja) * 2006-02-14 2007-08-30 Elpida Memory Inc 半導体装置及びその製造方法
US7494918B2 (en) * 2006-10-05 2009-02-24 International Business Machines Corporation Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof
US7977712B2 (en) * 2008-03-31 2011-07-12 International Business Machines Corporation Asymmetric source and drain field effect structure
US8120072B2 (en) 2008-07-24 2012-02-21 Micron Technology, Inc. JFET devices with increased barrier height and methods of making same
US8232585B2 (en) 2008-07-24 2012-07-31 Micron Technology, Inc. JFET devices with PIN gate stacks
US8278691B2 (en) 2008-12-11 2012-10-02 Micron Technology, Inc. Low power memory device with JFET device structures
US8481372B2 (en) 2008-12-11 2013-07-09 Micron Technology, Inc. JFET device structures and methods for fabricating the same
US9666493B2 (en) 2015-06-24 2017-05-30 International Business Machines Corporation Semiconductor device structure with 110-PFET and 111-NFET curent flow direction
US10833193B2 (en) 2016-09-30 2020-11-10 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device, method of manufacturing the same and electronic device including the device
CN106298778A (zh) 2016-09-30 2017-01-04 中国科学院微电子研究所 半导体器件及其制造方法及包括该器件的电子设备
US11081484B2 (en) 2016-09-30 2021-08-03 Institute of Microelectronics, Chinese Academy of Sciences IC unit and method of manufacturing the same, and electronic device including the same
US10833079B2 (en) 2019-01-02 2020-11-10 International Business Machines Corporation Dual transport orientation for stacked vertical transport field-effect transistors

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6151974A (ja) * 1984-08-22 1986-03-14 Toshiba Corp 半導体装置の製造方法
US5384473A (en) * 1991-10-01 1995-01-24 Kabushiki Kaisha Toshiba Semiconductor body having element formation surfaces with different orientations
US5847419A (en) * 1996-09-17 1998-12-08 Kabushiki Kaisha Toshiba Si-SiGe semiconductor device and method of fabricating the same
US5960271A (en) * 1996-09-18 1999-09-28 Advanced Micro Devices, Inc. Short channel self-aligned VMOS field effect transistor
US6624451B2 (en) * 1997-11-28 2003-09-23 Qinetiq Limited High frequency field effect transistor with carrier extraction to reduce intrinsic conduction
CN1536676A (zh) * 2003-04-04 2004-10-13 ̨������·����ɷ����޹�˾ 具有多方位的绝缘层上覆硅芯片及其制作方法
CN1973374A (zh) * 2004-06-10 2007-05-30 飞思卡尔半导体公司 具有多个半导体层的半导体器件

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3765969A (en) * 1970-07-13 1973-10-16 Bell Telephone Labor Inc Precision etching of semiconductors
US4156879A (en) * 1977-02-07 1979-05-29 Hughes Aircraft Company Passivated V-gate GaAs field-effect transistor
US4193182A (en) * 1977-02-07 1980-03-18 Hughes Aircraft Company Passivated V-gate GaAs field-effect transistor and fabrication process therefor
US4163988A (en) * 1978-01-30 1979-08-07 Xerox Corporation Split gate V groove FET
JPS58106870A (ja) * 1981-12-18 1983-06-25 Nissan Motor Co Ltd パワ−ｍｏｓｆｅｔ
FR2541727B1 (fr) * 1983-02-25 1987-05-15 Renault Procede et dispositif de regulation de la vitesse de rotation a vide d'un moteur a allumage commande dote d'accessoires a fonctionnement intermittent
US5049971A (en) * 1983-10-21 1991-09-17 Hughes Aircraft Company Monolithic high-frequency-signal switch and power limiter device
JPS61180472A (ja) * 1985-02-05 1986-08-13 Mitsubishi Electric Corp 半導体装置
JPS61251185A (ja) * 1985-04-30 1986-11-08 Mitsubishi Electric Corp 半導体レ−ザと変調用電気素子の複合素子
JPS62163376A (ja) * 1986-01-14 1987-07-20 Fujitsu Ltd 半導体記憶装置の製造方法
JPH0215652A (ja) * 1988-07-01 1990-01-19 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH02302044A (ja) * 1989-05-16 1990-12-14 Fujitsu Ltd 半導体装置の製造方法
US5003359A (en) * 1989-12-29 1991-03-26 David Sarnoff Research Center, Inc. Optoelectronic integrated circuit
US5874317A (en) * 1996-06-12 1999-02-23 Advanced Micro Devices, Inc. Trench isolation for integrated circuits
JPH10209178A (ja) * 1997-01-27 1998-08-07 Mitsubishi Electric Corp 電界効果型トランジスタ，およびその製造方法
KR100366701B1 (ko) * 1999-11-09 2003-01-06 삼성전자 주식회사 전계 효과 트랜지스터 채널 구조가 형성된 스캐닝 프로브마이크로스코프의 탐침 및 그 제작 방법
US6956263B1 (en) * 1999-12-28 2005-10-18 Intel Corporation Field effect transistor structure with self-aligned raised source/drain extensions
GB2362755A (en) * 2000-05-25 2001-11-28 Nanogate Ltd Thin film field effect transistor with a conical structure
JP2002359293A (ja) * 2001-05-31 2002-12-13 Toshiba Corp 半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6151974A (ja) * 1984-08-22 1986-03-14 Toshiba Corp 半導体装置の製造方法
US5384473A (en) * 1991-10-01 1995-01-24 Kabushiki Kaisha Toshiba Semiconductor body having element formation surfaces with different orientations
US5847419A (en) * 1996-09-17 1998-12-08 Kabushiki Kaisha Toshiba Si-SiGe semiconductor device and method of fabricating the same
US5960271A (en) * 1996-09-18 1999-09-28 Advanced Micro Devices, Inc. Short channel self-aligned VMOS field effect transistor
US6624451B2 (en) * 1997-11-28 2003-09-23 Qinetiq Limited High frequency field effect transistor with carrier extraction to reduce intrinsic conduction
CN1536676A (zh) * 2003-04-04 2004-10-13 ̨������·����ɷ����޹�˾ 具有多方位的绝缘层上覆硅芯片及其制作方法
CN1973374A (zh) * 2004-06-10 2007-05-30 飞思卡尔半导体公司 具有多个半导体层的半导体器件

Also Published As

Publication number Publication date
CN1845309A (zh) 2006-10-11
US20070224754A1 (en) 2007-09-27
US20060226495A1 (en) 2006-10-12
US7288821B2 (en) 2007-10-30

Similar Documents

Publication Publication Date Title
CN100456451C (zh) 三维混合取向技术的结构和方法
US11075164B2 (en) Semiconductor device including a conductive feature over an active region
KR101243996B1 (ko) 응력이 가해진 ｍｏｓ 디바이스 제조방법
US8779475B2 (en) Semiconductor device and method of manufacturing the same
US10079279B2 (en) FET with local isolation layers on S/D trench sidewalls
US8592916B2 (en) Selectively raised source/drain transistor
US9711417B2 (en) Fin field effect transistor including a strained epitaxial semiconductor shell
US20150179789A1 (en) FinFET DEVICE HAVING A MERGE SOURCE DRAIN REGION UNDER CONTACT AREAS AND UNMERGED FINS BETWEEN CONTACT AREAS, AND A METHOD OF MANUFACTURING SAME
US7910441B2 (en) Multi-gate semiconductor device and method for forming the same
US8659081B2 (en) Transistor with reduced channel length variation
US8048765B2 (en) Method for fabricating a MOS transistor with source/well heterojunction and related structure
CN105742360A (zh) 半导体器件及其制造方法
CN103681346B (zh) 晶体管、半导体器件及其制造方法
CN109801961A (zh) 半导体结构及其形成方法
KR20140015508A (ko) 반도체 장치
US10243073B2 (en) Vertical channel field-effect transistor (FET) process compatible long channel transistors
US20130037867A1 (en) Semiconductor device and manufacturing method thereof
US20130049124A1 (en) Mosfet integrated circuit with improved silicide thickness uniformity and methods for its manufacture
US20090152670A1 (en) Semiconductor device and method of fabricating the same
US10636895B2 (en) Vertical transport field effect transistor on silicon with defined junctions
US6727534B1 (en) Electrically programmed MOS transistor source/drain series resistance
US9614041B1 (en) Multi-gate semiconductor devices with improved hot-carrier injection immunity
US20100123173A1 (en) Semiconductor device and method of manufacturing the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: GOOGLE INC.

Free format text: FORMER OWNER: INTERNATIONAL BUSINESS MACHINES CORP.

Effective date: 20120503

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20120503

Address after: American California

Patentee after: Google Inc.

Address before: American New York

Patentee before: International Business Machines Corp.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090128

Termination date: 20170220

CF01 Termination of patent right due to non-payment of annual fee