CN100452885C - High-speeld code-flow playing and receiving device based on PCI - Google Patents
High-speeld code-flow playing and receiving device based on PCI Download PDFInfo
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Abstract
The present invention relates to a high-speed code stream playing and receiving device based on PCI, which is used for the test analysis of high-speed code streams of digital televisions. The present invention comprises a computer, a code stream playing card and a code stream receiving card, wherein the code stream playing card and the code stream receiving card are respectively composed of a programmable logic element FPGA, a PCI interface chip, an external large-capacity memory FIFO and a peripheral device, the FPGA is used for controlling the PCI state and coordinating the work between the PCI interface chip and the external FIFO, the FPGA of the playing card is mainly configured with a PCI state and logic control module, an NCO circuit module, a data buffering module, an interruption control module, an output clock synthesizing and controlling module, a code rate adjusting module, an output interface selecting module and an interface chip control module, and the FPGA of the receiving card is mainly configured with an input interface selecting module, an input signal processing module, a PCI state module, a logic control module, an interruption control module and a data buffering module. The present invention reasonably uses the functions of the PCI interface chips, and the play and the reception of high speed code streams by computers are realized through the processing operation of the FPGAs. The code rate of transmitted code streams can be as high as 120 Mbps.
Description
Technical field
The present invention relates to the digital TV Broadcasting Techniques field, specifically is that a kind of high-speeld code-flow based on pci (peripheral component interconnect) PCI is play and receiving system.
Background technology
Along with the development of Digital Television and the formulation of Moving Picture Experts Group-2, digital TV field enters the stage that develops rapidly to the Application and Development of digital audio/video and MPEG both at home and abroad.Safeguard in the process of design at source encoding and channel, often need to understand whether conformance with standard of code stream that generates or the code stream that obtains.Sometimes also must obtain its performance aspect coding and transmission to code stream analysis.In processes such as digital television system monitoring or trouble shooting, also need relevant device the code stream that generates or obtain is analyzed.Also have other equipment when modulation, also to need to carry out code stream proving program etc.These work all need the equipment that can receive with broadcast code flow and implement.
At present domestic and international several key instruments and broadcasting equipment manufacturer are developing or are developing this kind equipment, and its hardware designs also has based on the computer PCI interface.But its design principle more complicated, performance is also not ideal enough.All be based on the device of pci interface as domestic well-known blue topological " mpeg 2 transport stream data collecting card BSRC-11 and the transmission card BSTC-11 " that develops of Digital Television thermometrically mechanical discipline manufacturer, its principle design more complicated, on main signal processing module, used the bigger programmable logic device of resource, it can receive or the transmitted stream code check is up to 108Mbps, and the design cost of product is higher on the other hand.Though and that U.S. computer module company is produced code stream broadcast, receiving card design is fairly simple, the function singleness of product can only single transmitting-receiving code stream, does not possess the function that code check is adjusted.
Summary of the invention
The objective of the invention is to overcome the deficiency of prior art, provide a kind of high-speeld code-flow to play and receiving system based on pci (peripheral component interconnect) PCI, utilize broadcast, the reception of computer pci (peripheral component interconnect) pci interface chip control high-speeld code-flow, can be used for the analysis of digital television system high-speeld code-flow, test and monitoring.
Realize that technical scheme of the present invention comprises computer, code flow broadcast card and code stream receiving card, computer is play card and code stream receiving card by pci (peripheral component interconnect) pci interface chip control stream respectively, realizes the broadcast and the collection of code stream.Described code flow broadcast card is made up of programmable logic device FPGA, pci interface chip, outside mass storage FIFO and peripheral components 27M clock source, FPGA initialization and configuration module, AD9851 frequency synthesizer, ASI output module and SPI output module.Described code stream receiving card is made up of programmable logic device FPGA, pci interface chip, outside mass storage FIFO and peripheral assembly 27M clock source, FPGA initialization and configuration module, ASI input module and SPI input module; Wherein,
Programmable logic device FPGA in the code flow broadcast card, interconnect with the pci interface chip in the code flow broadcast card, the outside mass storage FIFO in the code flow broadcast card, be used for control stream and play the pci interface chip state of card, pci interface chip in the coordination code flow broadcast card and the work between the outside mass storage FIFO in the code flow broadcast card;
Programmable logic device FPGA in the code stream receiving card, interconnect with the pci interface chip in the code stream receiving card, the outside mass storage FIFO in the code stream receiving card, the pci interface chip state that is used for control stream receiving card, pci interface chip in the coordination code stream receiving card and the work between the outside mass storage FIFO in the code stream receiving card;
Pci interface chip in the code flow broadcast card is used to simplify the pci bus agreement, the pci bus of complexity is operated changing into simple local bus, cooperates the transmission and the reception of the programmable logic device FPGA realization bit stream data in the code flow broadcast card;
Pci interface chip in the code stream receiving card is used to simplify the pci bus agreement, the pci bus of complexity is operated changing into simple local bus, cooperates the transmission and the reception of the programmable logic device FPGA realization bit stream data in the code stream receiving card;
Peripheral components 27MHZ clock source in the code flow broadcast card, be used for the generation and the shaping of reference clock, generate the system clock of 27MHZ, be the CY7B923 chip in the ASI output module, programmable logic device FPGA in the code flow broadcast card and the pci interface chip in the code flow broadcast card provide stable reference clock;
Peripheral components 27MHZ clock source in the code stream receiving card, be used for the generation and the shaping of reference clock, generate the system clock of 27MHZ, be the CY7B933 chip in the ASI input module, programmable logic device FPGA in the code stream receiving card and the pci interface chip in the code stream receiving card provide stable reference clock;
FPGA initialization and configuration module in the code flow broadcast card, when powering on the needed relevant configuration information of the programmable logic device FPGA in the code flow broadcast card is downloaded to the configuration space of the programmable logic device FPGA in the code flow broadcast card, make the programmable logic device FPGA in the code flow broadcast card can realize desired function;
FPGA initialization and configuration module in the code stream receiving card, when powering on the needed relevant configuration information of the programmable logic device FPGA in the code stream receiving card is downloaded to the configuration space of the programmable logic device FPGA in the code stream receiving card, make the programmable logic device FPGA in the code stream receiving card can realize desired function;
Outside mass storage FIFO in the code flow broadcast card, be used for data cached, to remedy when high code check code stream is play, the DMA processing of computer and the delay of computer-internal data read, by changing read-write speed, the pci interface chip local side in the raising code flow broadcast card is to processing speed of data simultaneously;
Outside mass storage FIFO in the code stream receiving card, be used for data cached, to remedy when high code check code stream receives, the DMA processing of computer and the delay of computer-internal data read, by changing read-write speed, the pci interface chip local side in the raising code stream receiving card is to processing speed of data simultaneously;
The AD9851 frequency synthesizer is used to synthesize the clock onesize with the code stream code check, and will send into clock control module among the programmable logic device FPGA in the code flow broadcast card with the onesize clock signal of code stream code check;
The SPI output module is finished the level conversion of the programmable logic device FPGA output SPI signal in the code flow broadcast card, realizes the SPI conversion of signals is become to be fit to the signal output of cable transmission, improves the antijamming capability of signal in Channel Transmission;
The ASI output module, comprise CY7B923 chip, coupling shaping circuit, this ASI output module becomes to be fit to the signal of cable transmission with the ASI conversion of signals of the output of the programmable logic device FPGA in the code flow broadcast card, the CY7B923 chip realize the 8bit of code word to the conversion of 10bit, insert synchronization character K28.5 and and the string conversion, finish the driving and the coupling of the constant ASI signal for 270MHZ of output speed and export;
The SPI input module, finish the level conversion of input signal, convert the low-voltage differential level signal LVDS of SPI interface input to the Transistor-Transistor Logic level signal, the input interface among the programmable logic device FPGA in code stream receiving card selects module output to meet 11 road signals of SPI signal structure;
The ASI input module, finish the coupling amplification and the shaping of input signal, coupling shaping circuit in the ASI input module is finished the clock of input signal and the recovery of data, CY7B933 chip in the ASI input module is realized conversion, removal synchronization character K28.5 and string and the conversion of the 10bit of code word to 8bit, select module to export 8 tunnel parallel data-signals to input interface, the transmission rate of ASI is constant to be 270MHZ.Because the speed difference of code stream so need an inner FIFO to finish the rate-matched of input signal, utilizes the internal RAM of FPGA to realize.
The main configuration that the present invention plays the programmable logic device FPGA of card comprises PCI state and Logic control module, NCO digital controlled oscillator circuit module, data cache module, clock control module, interruption controls module, exports synthetic control module, the code check adjusting module of reaching of clock, output interface is selected module, interface chip control module.Wherein,
PCI state and Logic control module, the DMA control that realizes the function of the pci interface chip in the code flow broadcast card and finish the pci interface chip in the code flow broadcast card selects signal to deliver to output interface selection module the output interface that address decoding produces; To produce clock control signal and export clock control module to; The continuous impulse that produces is delivered to the write clock of NCO digital controlled oscillator circuit as configuration words;
Data cache module, the FIFO that uses the programmable logic device FPGA inside in the code flow broadcast card to provide, the data of transmitting between the configuration words of buffer memory computer input and the outside mass storage FIFO in computer and code flow broadcast card, and, when device start, different configuration words is transferred to NCO digital controlled oscillator circuit and synthesize and control module with the output clock in conjunction with PCI state and Logic control module;
NCO digital controlled oscillator circuit, computer software converts the new code check of desire adjustment to configuration words and sends into NCO digital controlled oscillator circuit module, NCO digital controlled oscillator circuit module produces a clock signal that meets new code check size according to configuration words information, realize that the adjustable stepping accuracy of code check is 1HZ, and this clock signal is sent into the code check adjusting module;
The code check adjusting module receives the code stream that the outside mass storage FIFO in the code flow broadcast card sends here, realizes that the multi code Rate of Chinese character of single program source is play;
The code check adjusting module, the clock signal of code stream that the outside mass storage FIFO in the reception code flow broadcast card sends here and the input of NCO digital controlled oscillator circuit module circuit, realize the multi code Rate of Chinese character broadcast of single program source,, with the precision arbitrary bit rate output of 1HZ promptly by changing the code check of source code flow;
Clock control module, the synthetic clock of clock control signal control AD9851 frequency synthesizer according to input, the clock signal that the AD9851 frequency synthesizer is synthetic outputs to the outside mass storage FIFO in the code flow broadcast card, as the clock of the outside mass storage FIFO sense data from code flow broadcast card;
Synthetic and the control module of output clock, computer software analysis is obtained the code check size of code stream and converts thereof into corresponding configuration words to send into the synthetic and control module of output clock, this module realizes configuration words is write the AD9851 frequency synthesizer, and control AD9851 chip is exported corresponding clock to clock control module;
The interruption controls module, with the half-full state of the outside mass storage FIFO in the code flow broadcast card as interrupt signal, realize communicating by letter between external hardware and the computer software, when simultaneous computer software initiates this interrupt signal as computer the sign of transfer of data;
Output interface is selected module, according to the selection input control signal of computer settings, finishes from ASI interface or SPI interface transmission signal;
The interface chip control module, the transmission rate of ASI is constant to be 270MHZ, and the stream rate of output is different, need to realize rate-matched, select the data of module output, outside mass storage FIFO in the code flow broadcast card and the communication between the CY7B923 chip to carry out logic control output interface with the outside mass storage FIFO in the code flow broadcast card;
The main configuration of the programmable logic device FPGA of code stream receiving card of the present invention comprises input interface selection module, the input signal processing module, PCI state and Logic control module, interruption controls module, the data cache module module, the purposes of each configuration module and signal transmission relation are as follows:
Input interface is selected module, according to a selection control input signals of computer settings, finishes receiving ASI input signal or SPI input signal;
The input signal processing module is analyzed the interface input signal of choosing, and it is write outside mass storage FIFO in the code stream receiving card, receives the start and stop time of data simultaneously according to the input control signal control of computer settings;
Data cache module is carried out buffer memory to data, guarantee data in code stream receiving card outside mass storage FIFO and the computer-internal memory between stable DMA transmit;
The interruption controls module, with the half-full state of the outside mass storage FIFO in the code stream receiving card as interrupt signal, realize communicating by letter between external hardware and the computer software, when simultaneous computer software initiates this interrupt signal as computer the sign of transfer of data;
PCI state and Logic control module, the DMA control that realizes the function of the pci interface chip in the code stream receiving card and finish the pci interface chip in the code stream receiving card selects signal to send into input interface selection module the input interface that address decoding produces; The enable signal that produces is delivered to the input signal processing module.
The configuration that the present invention has used powerful special-purpose pci interface chip and reasonably designed programmable logic device FPGA has realized directly putting and receive code stream with the calculating machine sowing.Make it compared with prior art, it is simple to have hardware circuit design, and perfect in shape and function is functional, advantage and the high-speed transfer that has realized bit stream data that equipment cost is low.The code stream code check of its transmission is up to 120Mbps, can satisfy the processing of the synthetic high code check transport stream of multichannel, can be at software down auxiliary, when realizing code stream play, receives, code stream is detected, analyze.Therefore, the present invention has purposes widely in installation, debugging, the detection of digital television system with aspect safeguarding.
Description of drawings
Fig. 1: overall structure figure of the present invention
Fig. 2: the cut-away view of code flow broadcast card of the present invention
Fig. 3: the internal structure flow chart of code check adjusting module of the present invention
Fig. 4: the cut-away view of code stream receiving card of the present invention
Fig. 5: the present invention tests schematic diagram
Embodiment
Referring to Fig. 1, internal structure of the present invention comprises code flow broadcast card, and code stream receiving card and computer, computer are play card, code stream receiving card by periphery interconnection pci interface chip control stream respectively, realize the broadcast and the reception of data.
Referring to Fig. 2, the formation of code flow broadcast card of the present invention comprises pci interface chip, outside mass storage FIFO, programmable logic device FPGA, and SPI output module, the ASI output module, peripheral components 27MHZ clock source, AD9851 chip, FPGA initialization and configuration module.The internal configurations of programmable logic device FPGA comprises PCI state and Logic control module, data cache module, the interruption controls module, synthetic and the control module of output clock, clock control module, NCO digital controlled oscillator circuit, code check adjusting module, output interface is selected the pio chip control module, and each purposes and signal transmission relation of forming module is as follows:
Pci interface chip, the pci bus operation of complexity is changed into simple local bus operation, simplify the pci bus agreement, pci bus interface chip strong functions guarantees the flexibility of circuit design and the stability of performance simultaneously, finishes the superiority that more reveals it aspect the high-speed data processing.Pci interface chip is selected the PLXPCI9054 chip that can carry out the DMA transfer function for use, cooperates programmable logic device FPGA to realize the transmission of bit stream data.
PCI state and Logic control module, the DMA control that realizes the function of the pci interface chip in the code flow broadcast card and finish the pci interface chip in the code flow broadcast card guarantees the stable high-speeld code-flow of accurately playing.Mainly finish the control that comprises between the pci bus interface, the control of address and data, address decoding, the DMA transmission course of data and the control of state.Wherein address decoding produces output interface selection signal and exports output interface selection module to, produces clock control signal and exports clock control module to, produces consecutive pulses and delivers to the write clock of NCO digital controlled oscillator circuit as configuration words.
Data cache module, the FIFO that uses the programmable logic device FPGA inside in the code flow broadcast card to provide carries out buffer memory to the data of input.This FIFO is in conjunction with PCI state and logic control, realize that the different configuration words of earlier computer being sent here transfers to NCO circuit and the synthetic and control module of output clock separately, is exclusively used in the data between the outside mass storage FIFO that is buffered in computer and the code flow broadcast card then.
Outside mass storage FIFO, when realizing the broadcast of high code check code stream, for the DMA that remedies computer handles and the delay of computer-internal data read, it is data cached to need a jumbo external memory storage, by changing read-write speed, improve the pci interface chip local side simultaneously to processing speed of data.
The interruption controls module as interrupt signal, realizes communicating by letter between external hardware and the computer software with the half-full state of the outside mass storage FIFO in the code flow broadcast card.The time tag of data output initiated interrupt signal by simultaneous computer software as computer.
Synthetic and the control module of output clock, obtain the code check size of code stream and convert thereof into corresponding configuration words to send into this module by computer software analysis, this module realizes that the control configuration words writes the AD9851 frequency synthesizer, and control AD9851 frequency synthesizer is exported corresponding clock to clock control module.
The AD9851 frequency synthesizer module is used to synthesize and code stream code check clock of a size, and will send into clock control module with code stream code check clock signal of a size.
Clock control module, the synthetic clock of clock control signal control AD9851 frequency synthesizer according to input, this clock signal is outputed to outside mass storage FIFO in the code flow broadcast card, as the clock of the outside mass storage FIFO sense data from code flow broadcast card.
NCO digital controlled oscillator circuit, computer software converts the new code check of desire adjustment to configuration words and sends into NCO digital controlled oscillator circuit, NCO digital controlled oscillator circuit produces a clock signal that meets new code check size according to configuration words information, and the output clock is delivered to the code check adjusting module.Code stream will be exported from external interface with this code check, and this circuit realizes that the adjustable stepping accuracy of code check is 1HZ.
Output interface is selected module, realizes a selection control input signals according to computer settings, finishes from ASI interface or SPI interface transmission signal.
The SPI output module, finish the level conversion of the programmable logic device FPGA output SPI signal in the code flow broadcast card, to export the Transistor-Transistor Logic level conversion of signals and become low-voltage differential level signal (LVDS) output, the SPI conversion of signals is become to be fit to the signal output of cable transmission, and improve the antijamming capability of signal in Channel Transmission.
The interface chip control module, the transmission rate of ASI is constant to be 270MHZ, and the stream rate of output is different, need to realize rate-matched, select the data of module output, outside mass storage FIFO in the code flow broadcast card and the communication between the CY7B923 chip to carry out logic control output interface with the outside mass storage FIFO in the code flow broadcast card;
ASI output module, this ASI output module become to be fit to the signal of cable transmission with the output of the programmable logic device FPGA in code flow broadcast card ASI conversion of signals.Comprise CY7B923 chip, coupling shaping circuit.Wherein the CY7B923 chip realize the 8bit of code word to the conversion of 10bit, insert synchronization character K28.5 and and the string conversion, finish the driving and the coupling of the constant ASI signal for 270MHZ of output speed and export.
Peripheral components 27MHZ clock source, the generation of reference clock and shaping, generate the system clock of 27MHZ, be the CY7B923 chip in the ASI output module, programmable logic device FPGA in the code flow broadcast card and the pci interface chip in the code flow broadcast card provide stable reference clock.
FPGA initialization and configuration module, when powering on the needed relevant configuration information of the programmable logic device FPGA in the code flow broadcast card is downloaded to the configuration space of the programmable logic device FPGA in the code flow broadcast card, make the programmable logic device FPGA in the code flow broadcast card can realize desired function.
The code check adjusting module realizes that the multi code Rate of Chinese character of single program source is play, and promptly by changing the code check of source code flow, is the arbitrary bit rate output of 1HZ with the precision with code stream.Described code stream adjustment is that the TS code stream that will import carries out the synchronous head detection behind buffer memory, TS stream " packing " is become the Continuous Flow of a bag of every 188Byte, with the bag is that unit carries out the PCR detection, extract the PCR value in the TS stream, and several subtraction of this PCR value and counter generation are got new PCR value insert again during TS flows.The input clock that NCO digital controlled oscillator circuit is produced inserts the TS stream hollow bag of having revised PCR information, produces new TS stream.And then extract PCR value in the new TS stream, and the number of the generation of this PCR value and counter is done add operation, carry out the PCR information modification second time, at last the PCR information that obtains is inserted again during TS flows, finish the code check adjustment of code stream.
As shown in Figure 3, the internal configurations of described code check adjusting module comprises: the first inner FIFO (A), the synchronous head detection module, the PCR detection module, subtracter, PCR insert module, the second inner FIFO (B), empty packet generation device and empty bag insert module, the 3rd inner FIFO (C), adder sum counter.The purposes and the signal transmission relation of each configuration are as follows:
[1] first inner FIFO (A): be to provide by the programmable logic device FPGA inside in the code flow broadcast card, use this inside FIFO (A) that the TS of input is flow to row cache, with the high clock of a 27MHZ readout clock as the first inner FIFO (A), read TS stream, for postorder is handled raising speed.
[2] synchronous head detection module: TS stream is made up of the bag of TS one by one, and each TS bag is made up of the data of 188Byte, and the synchronizing signal that implies in the TS stream of this module with input extracts, and is equivalent to that TS stream is processed into a string continuous TS and wraps.The output of TS after synchronous head detects is divided into two-way, and one the tunnel is used for PCR detects, and another road inputs to the modification that the PCR insert module is finished PCR information.
[3] PCR detection module: extract the PCR value in the TS stream.The form of TS stream meets Moving Picture Experts Group-2, wherein the information in each TS bag packet header is all fixed, the PCR detection module knows whether contain PCR information in this bag by detecting TS bag header packet information, if contain PCR information in the TS bag, then extract its PCR value, and export it to subtracter and adder.
[4] subtracter: the counting subtraction of the counter generation that PCR value and the reference clock that extracts in the TS stream is 27MHZ is also exported the result as new PCR value.
[5] PCR insert module: is the TS stream signal that unit detects input with the bag, removes the PCR value in the TS stream PCR territory, the new PCR value that will import again is inserted in the PCR territory in the TS stream, and the TS that obtains finishing the modification of PCR information flows and exports.
[6] second inner FIFO (B): be to provide by the programmable logic device FPGA inside in the code flow broadcast card, use this inside FIFO (B), TS to input flows to row cache, the input clock that produces with NCO digital controlled oscillator circuit is as the readout clock of the second inner FIFO (B) simultaneously, TS stream is read and sent into sky packet generation device with the full signal of sky of the second inner FIFO (B).
[7] empty packet generation device: output meets the data flow that has sky information of TS packet format, i.e. the empty bag of output.
[8] empty bag insert module:, when the half-full signal of the second inner FIFO (B) is effective, be the TS stream output of unit, otherwise the empty bag of output is finished the insertion of empty bag with input with the bag according to the full signal of sky of the second inner FIFO (B) of input.
[9] the 3rd inner FIFO (C): be to provide, use this inside FIFO (C) that the new TS of sky bag insert module output is flow to row cache by the programmable logic device FPGA inside in the code flow broadcast card.The signal of output is divided into two-way: the one tunnel enters the PCR detection module is used to extract PCR information; Another road transfers to the PCR insert module, finishes the modification of PCR information.
[10] adder: the number of the counter generation that the PCR value that extracts in the TS stream and reference clock are 27MHZ is done add operation and the result is sent as new PCR value.
[11] counter:, in this counting input summer and subtracter that produces, be used to adjust the PCR value with the counting clock of reference clock 27MHZ as counter.
Referring to Fig. 4, the formation of code stream receiving card of the present invention comprises the ASI input module, SPI input module, programmable logic device FPGA, outside mass storage FIFO, pci interface chip, peripheral components 27MHZ clock source, FPGA initialization and configuration module.The internal configurations of programmable logic device FPGA comprises: input interface is selected module, input signal processing module, PCI state and Logic control module, interruption controls module, data cache module.Described outside mass storage FIFO, pci interface chip, peripheral components 27M clock source are identical with the respective modules of code flow broadcast card with the purposes of modules such as FPGA initialization and configuration.Other purposes and data transmission relations of respectively forming module are as follows:
ASI input module: mainly finish the coupling amplification and the shaping of input signal, the interface coupling network circuit of ASI input module is finished the clock of input signal and the recovery of data, the CY7B933 chip of ASI input module is realized conversion, removal synchronization character K28.5 and string and the conversion of the 10bit of code word to 8bit, exports 8 tunnel parallel data-signals.The transmission rate of ASI is constant to be 270MHZ, and the speed of code stream is different, so need a FIFO to finish the rate-matched of input signal, utilizes the internal RAM of programmable logic device FPGA to realize.
The SPI input module: finish the level conversion of input signal, the low-voltage differential level signal (LVDS) that SPI is imported converts the Transistor-Transistor Logic level signal to, and output meets 11 road signals of SPI signal structure.
Input interface is selected module: realize a selection control input signals according to computer settings, finish receiving ASI input signal or SPI input signal.
Input signal processing module: finish the interface input signal of choosing is analyzed, it is write outside mass storage in the code stream receiving card, enable the control signal input according to of computer settings simultaneously and realize when control begins or stop to receive data.
Data cache module: data are carried out buffer memory, guarantee data in code stream receiving card outside mass storage FIFO and the computer-internal memory between stable DMA transmit.
Interruption controls module: as interrupt signal, realize communicating by letter between external hardware and the computer software with the half-full state of the outside mass storage FIFO in the code stream receiving card.When simultaneous computer software initiates this signal as computer the sign of transfer of data.
PCI state and Logic control module: the DMA control that realizes the function of the pci interface chip in the code stream receiving card and finish the pci interface chip in the code stream receiving card guarantees to stablize, accurately receive high-speeld code-flow.Mainly finish the control that comprises between the pci bus interface, the control of address and data, address decoding, the DMA transmission course of data and the control of state.Wherein address decoding produces input interface selection signal and sends into input interface selection module, produces enable signal and delivers to the input signal processing module.
The course of work of the present invention is as follows:
The present invention is by configuration that reasonably designs programmable logic device FPGA and the power that utilizes the pci (peripheral component interconnect) pci interface chip, the data that realization will be stored in the computer send from external interface continuously by predetermined form, or receive the continuous bit stream that comes from external interface and be stored in the computer.
The course of work that its code stream is play is: at first finished the initialization of hardware by computer; Then under the control of the pci interface chip in code flow broadcast card, bit stream data in the computer-internal memory block transmits with the outside mass storage FIFO of dma mode in code flow broadcast card, what wherein the DMA of data transmission was adopted is the piece transmission means, the block size of each transmission is half of outside mass storage FIFO amount of capacity in the code flow broadcast card, half-full sign with outside mass storage FIFO feeds back to computer as interrupt source signal simultaneously, computer is by the DMA transmission of the interrupt signal control data received, implementation is whenever to receive once to interrupt, transmit a secondary data with dma mode, because the speed of external interface dateout is less than 27MBps, and the speed of the past outside mass storage FIFO write data of computer is 27MBps, among the outside mass storage FIFO data are arranged all the time, can guarantee external interface dateout continuously, the PCI of FPGA control around here state is coordinated the work between pci interface chip and the external FIFO; Generate and code stream code check clock of a size by the AD9851 frequency synthesizer circuit then, control this clock sense code flow data from outside mass storage FIFO continuously by clock control module, and send into code check adjusting module among the FPGA, the code check adjusting module realizes that code stream is that the arbitrary bit rate size of 1HZ is exported to output interface module with the stepping accuracy; The module of selecting output interface realizes that code stream is to export with the ASI form or with the SPI form.
The course of work that its code stream receives is: at first finished the initialization of hardware by computer; Then send read write command by the programmable logic device FPGA of the pci interface chip in the computer control code stream receiving card in code stream receiving card, FPGA inside begins outside mass storage FIFO write data in code flow broadcast card by instruction decoding notice input signal processing module, and with the half-full sign of outside mass storage FIFO as interrupt source signal, send into computer through pci interface chip, in order to realize the communication between outside mass storage FIFO and the computer.Under the control of pci interface chip, data among the outside mass storage FIFO write the computer-internal memory in the mode of DMA, what wherein the DMA of data transmission was adopted is the piece transmission means, the block size of each transmission is half of outside mass storage FIFO amount of capacity, computer is by the DMA transmission of the interrupt signal control data received, implementation is whenever to receive once to interrupt, transmit a secondary data with dma mode, because the speed of external interface input data is less than 27MBps, and the speed of the past outside mass storage FIFO read data of computer is 27MBps, all the time can not overflow among the outside mass storage FIFO, can guarantee that external interface imports data continuously by complete reception, the PCI of FPGA control around here state is coordinated the work between pci interface chip and the outside mass storage FIFO.
Fig. 5 is that the present invention is used for code stream test transmission schematic diagram.When the TS stream that transmits in to communication network with the present invention is tested, this device can be inserted the node of desiring to test, by ASI interface or SPI interface TS stream is collected in the computer, utilize corresponding software to realize the code stream information of gathering is analyzed then, thus the code stream information that acquisition needs or desire detects; When needs add test source toward the node of testing, then the code stream that is stored in the computer can be played out, this device is supported ASI signal format and the output of SPI signal format respectively, and can change the code check of output code flow as required arbitrarily, and the precision of changeable code check reaches 1Hz/s.
Claims (4)
1. the high-speeld code-flow based on PCI is play and receiving system, comprises computer, code flow broadcast card and code stream receiving card, and computer is play card, code stream receiving card by the pci interface chip control stream respectively, realizes the broadcast and the reception of code stream; Described code flow broadcast card is made up of programmable logic device FPGA, pci interface chip, outside mass storage FIFO and peripheral components 27MHZ clock source, FPGA initialization and configuration module, AD9851 frequency synthesizer, ASI output module and SPI output module; Described code stream receiving card is made up of programmable logic device FPGA, pci interface chip, outside mass storage FIFO and peripheral components 27MHZ clock source, FPGA initialization and configuration module, ASI input module and SPI input module; Each purposes and signal transmission relation of forming module is as follows:
Programmable logic device FPGA in the code flow broadcast card, interconnect with the pci interface chip in the code flow broadcast card, the outside mass storage FIFO in the code flow broadcast card, be used for control stream and play the pci interface chip state of card, pci interface chip in the coordination code flow broadcast card and the work between the outside mass storage FIFO in the code flow broadcast card;
Programmable logic device FPGA in the code stream receiving card, interconnect with the pci interface chip in the code stream receiving card, the outside mass storage FIFO in the code stream receiving card, the pci interface chip state that is used for control stream receiving card, pci interface chip in the coordination code stream receiving card and the work between the outside mass storage FIFO in the code stream receiving card;
Pci interface chip in the code flow broadcast card is used to simplify the pci bus agreement, the pci bus of complexity is operated changing into simple local bus, cooperates the transmission and the reception of the programmable logic device FPGA realization bit stream data in the code flow broadcast card;
Pci interface chip in the code stream receiving card is used to simplify the pci bus agreement, the pci bus of complexity is operated changing into simple local bus, cooperates the transmission and the reception of the programmable logic device FPGA realization bit stream data in the code stream receiving card;
Peripheral components 27MHZ clock source in the code flow broadcast card, be used for the generation and the shaping of reference clock, generate the system clock of 27MHZ, be the CY7B923 chip in the ASI output module, programmable logic device FPGA in the code flow broadcast card and the pci interface chip in the code flow broadcast card provide stable reference clock;
Peripheral components 27MHZ clock source in the code stream receiving card, be used for the generation and the shaping of reference clock, generate the system clock of 27MHZ, be the CY7B933 chip in the ASI input module, programmable logic device FPGA in the code stream receiving card and the pci interface chip in the code stream receiving card provide stable reference clock;
FPGA initialization and configuration module in the code flow broadcast card, when powering on the needed relevant configuration information of the programmable logic device FPGA in the code flow broadcast card is downloaded to the configuration space of the programmable logic device FPGA in the code flow broadcast card, make the programmable logic device FPGA in the code flow broadcast card can realize desired function;
FPGA initialization and configuration module in the code stream receiving card, when powering on the needed relevant configuration information of the programmable logic device FPGA in the code stream receiving card is downloaded to the configuration space of the programmable logic device FPGA in the code stream receiving card, make the programmable logic device FPGA in the code stream receiving card can realize desired function;
Outside mass storage FIFO in the code flow broadcast card, be used for data cached, to remedy when high code check code stream is play, the DMA processing of computer and the delay of computer-internal data read, by changing read-write speed, the pci interface chip local side in the raising code flow broadcast card is to processing speed of data simultaneously;
Outside mass storage FIFO in the code stream receiving card, be used for data cached, to remedy when high code check code stream receives, the DMA processing of computer and the delay of computer-internal data read, by changing read-write speed, the pci interface chip local side in the raising code stream receiving card is to processing speed of data simultaneously;
The AD9851 frequency synthesizer is used to synthesize the clock onesize with the code stream code check, and will send into clock control module among the programmable logic device FPGA in the code flow broadcast card with the onesize clock signal of code stream code check;
The SPI output module is finished the level conversion of the programmable logic device FPGA output SPI signal in the code flow broadcast card, realizes the SPI conversion of signals is become to be fit to the signal output of cable transmission;
The ASI output module, comprise CY7B923 chip, coupling shaping circuit, this ASI output module becomes to be fit to the signal of cable transmission with the ASI conversion of signals of the output of the programmable logic device FPGA in the code flow broadcast card, the CY7B923 chip realize the 8bit of code word to the conversion of 10bit, insert synchronization character K28.5 and and the string conversion, finish the driving and the coupling of the constant ASI signal for 270MHZ of output speed and export;
The SPI input module is finished the level conversion of input signal, and the input interface among the programmable logic device FPGA in code stream receiving card selects module output to meet 11 road signals of SPI signal structure;
The ASI input module, finish the coupling amplification and the shaping of input signal, coupling shaping circuit in the ASI input module is finished the clock of input signal and the recovery of data, CY7B933 chip in the ASI input module is realized conversion, removal synchronization character K28.5 and string and the conversion of the 10bit of code word to 8bit, selects module to export 8 tunnel parallel data-signals to input interface.
2. high-speeld code-flow according to claim 1 is play and receiving system, the configuration that it is characterized in that the programmable logic device FPGA of described code flow broadcast card comprises PCI state and Logic control module, NCO digital controlled oscillator circuit, data cache module, clock control module, interruption controls module, exports synthetic control module, the code check adjusting module of reaching of clock, output interface is selected module, the interface chip control module, the purposes of each configuration module and signal transmission relation are as follows:
PCI state and Logic control module, the DMA control that realizes the function of the pci interface chip in the code flow broadcast card and finish the pci interface chip in the code flow broadcast card selects signal to deliver to output interface selection module the output interface that address decoding produces; The clock control signal that produces exports clock control module to; The continuous impulse that produces is delivered to the write clock of NCO digital controlled oscillation circuit as configuration words;
Data cache module, the FIFO that uses the programmable logic device FPGA inside in the code flow broadcast card to provide, the data of transmitting between the configuration words of buffer memory computer input and the outside mass storage FIFO in computer and code flow broadcast card transfer to NCO digital controlled oscillator circuit respectively with different configuration words when device start and the output clock synthesizes and control module;
NCO digital controlled oscillator circuit, the configuration words information of sending here according to computer produces a clock signal that meets new code check size, and the clock signal that will meet new code check size is sent into the code check adjusting module;
The code check adjusting module receives the code stream that the outside mass storage FIFO in the code flow broadcast card sends here, realizes that the multi code Rate of Chinese character of single program source is play;
Clock control module, the synthetic clock of clock control signal control AD9851 frequency synthesizer according to input, the clock signal that the AD9851 frequency synthesizer is synthetic outputs to the outside mass storage FIFO in the code flow broadcast card, as the clock of the outside mass storage FIFO sense data from code flow broadcast card;
Synthetic and the control module of output clock realize that the control configuration words writes the AD9851 frequency synthesizer, and control AD9851 chip is exported corresponding clock to clock control module;
The interruption controls module, with the half-full state of the outside mass storage FIFO in the code flow broadcast card as interrupt signal, realize communicating by letter between external hardware and the computer software, when simultaneous computer software initiates this interrupt signal as computer the sign of transfer of data;
Output interface is selected module, according to the selection input control signal of computer settings, finishes from ASI interface or SPI interface transmission signal;
The interface chip control module selects the data of module output, outside mass storage FIFO in the code flow broadcast card and the communication between the CY7B923 chip to carry out logic control to output interface;
3. high-speeld code-flow according to claim 1 is play and receiving system, the configuration that it is characterized in that the programmable logic device FPGA of described code stream receiving card comprises input interface selection module, the input signal processing module, PCI state and Logic control module, the interruption controls module, data cache module, the purposes of each configuration module and signal transmission relation are as follows:
Input interface is selected module, according to a selection control input signals of computer settings, finishes receiving ASI input signal or SPI input signal;
The input signal processing module is analyzed the interface input signal of choosing, and it is write outside mass storage FIFO in the code stream receiving card, receives the time started and the dwell time of data simultaneously according to the input control signal control of computer settings;
Data cache module is carried out buffer memory to data, guarantee data in code stream receiving card outside mass storage FIFO and the computer-internal memory between stable DMA transmit;
The interruption controls module, half-full state with the outside mass storage FIFO in the code stream receiving card is an interrupt signal, realize communicating by letter between external hardware and the computer software, the time tag of transfer of data initiated this interrupt signal by simultaneous computer software as computer;
PCI state and Logic control module, the DMA control that realizes the function of the pci interface chip in the code stream receiving card and finish the pci interface chip in the code stream receiving card selects signal to send into input interface selection module the input interface that address decoding produces; The enable signal that produces is delivered to the input signal processing module.
4. high-speeld code-flow according to claim 2 is play and receiving system, it is characterized in that described code check adjusting module comprises the inner first inner FIFO, the second inner FIFO, the 3rd inner FIFO, the synchronous head detection module, the PCR detection module, the PCR insert module, subtracter and adder, counter, empty packet generation device and empty bag insert module; Wherein:
[1] first inner FIFO, be to provide by the programmable logic device FPGA inside in the code flow broadcast card, use this first inner FIFO that the TS of input is flow to row cache, and read TS stream as the readout clock of the first inner FIFO, be the processing raising speed of back with the high clock of a 27MHZ;
[2] synchronous head detection module extracts implicit synchronizing signal in the TS stream of input, TS stream is processed into a string continuous TS bag back divides two-way output, and one the tunnel is used for PCR detects, and another road inputs to the modification that the PCR insert module is finished PCR information;
[3] PCR detection module extracts the PCR value in the TS stream, and exports it to subtracter and adder;
[4] subtracter, the counting subtraction of the counter generation that the PCR value that extracts in the TS stream and reference clock are 27MHZ, and the result sent as new PCR value;
[5] PCR insert module is the TS stream signal that unit detects input with the bag, removes the PCR value in the TS stream PCR territory, and the new PCR value that will import again is inserted in the PCR territory in the TS stream, and the TS that acquisition PCR information has been revised flows also and exports;
[6] second inner FIFO, be to provide by the programmable logic device FPGA inside in the code flow broadcast card, use this second inner FIFO that the TS of PCR insert module output is flow to row cache, use the readout clock of the input clock of NCO digital controlled oscillator circuit generation simultaneously, TS stream is read and sent into sky with the full signal of sky of the second inner FIFO and wrap insert module as the second inner FIFO;
[7] empty packet generation device, output meets the data flow that has sky information of TS packet format;
[8] empty bag insert module when the half-full signal of the second inner FIFO is effective, is the TS stream output of unit with input with the bag, otherwise the empty bag of output;
[9] the 3rd inner FIFO, be to provide by the programmable logic device FPGA inside in the code flow broadcast card, use the 3rd inner FIFO that the TS of sky bag insert module output is flow to row cache, the signal of exporting is divided into two-way: the one tunnel enters the PCR detection module extracts PCR information; Another road transfers to the PCR insert module, finishes the modification of PCR information;
[10] adder is done add operation with the numerical value that counter produced that the PCR value extracted and reference clock are 27MHZ, and is sent the result defeated as new PCR value
[11] counter as counting clock, in this counting input summer and subtracter that produces, is used to adjust the PCR value with reference clock 27MHZ.
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