CN100448104C - 堆叠芯片柔性组件 - Google Patents

堆叠芯片柔性组件 Download PDF

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Publication number
CN100448104C
CN100448104C CNB038271508A CN03827150A CN100448104C CN 100448104 C CN100448104 C CN 100448104C CN B038271508 A CNB038271508 A CN B038271508A CN 03827150 A CN03827150 A CN 03827150A CN 100448104 C CN100448104 C CN 100448104C
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chip
chips
assembly
flexible
carrier
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CN1839518A (zh
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理查德·P·沃兰特
凯文·S·佩特拉尔卡
乔治·F·沃尔克
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International Business Machines Corp
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International Business Machines Corp
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Abstract

本发明描述一种三维封装，其包括多个折叠的集成电路芯片(100、110、120)，其中至少一个芯片提供用于到所述堆叠的附加芯片的电连接的互连路径，且至少一个芯片(130)设置有到衬底(500)、封装或印刷电路板的额外互连布线。此外，本发明还描述了一种提供互连芯片的柔性布置的方法，所述互连芯片被折叠为三维布置，从而当安装到衬底、二级封装或印刷电路板上时消耗更少的空间。

Description

堆叠芯片柔性组件
技术领域
本发明总地涉及堆叠芯片(stacking chip)和改进的从该堆叠芯片结构的热去除(thermal extraction)，更特别地，涉及互连芯片，其电学上形成封装上***(system-on-a-package，SOP)或附着到另一SOP，同时物理上折叠为显著减少最终组件的覆盖区(footprint)的三维布置。
背景技术
随着***变得更复杂，对具有多功能的集成电路的需求增大，使得需要分开地制造不同功能的芯片且将它们组装成***或子***。例如，会需要将处理器模块逻辑电路、存储芯片和无线收发器组装为最终产品。加工这些芯片不允许将它们同时构建在单个芯片上。因此需要单独地封装每个芯片，随后将芯片组装在含有电连接的印刷电路板(PCB)上。本示例导致在PCB上三个单独的芯片占用宝贵的空间。还应注意，每个芯片产生废热，该废热必须被去除从而保持芯片有效且可靠地运行。
本领域公知，在较小晶片(die)组成的封装中产率通常高得多。因此使用多个小晶片，使得较小的高产率芯片互连从而将它们各自的功能结合在单个封装中，这将是非常有利的。
如本发明中稍后将描述的，封装之间的互连有利地由柔性线(flexiblewire)提供，其中各种金属/聚合物组合的柔性和强度已被证明用于多种应用，例如在材料研究协会的2000年材料研究协会讨论会的会议文集第629卷第FF5.10.1-FF10.1.10页发表的Jin-Won Choi等人的文章“Adhesion Strength andPeeling Angle Measured on the Polyimide/Cr interfaces”中。该文章描述了在BPDA-PDA聚酰亚胺上制造的聚酰亚胺/Cr/Cu结构的使用、以及粘合强度与剥离角度(peeling angle)之间的相互关系。已确定，不依赖于金属膜或聚酰亚胺衬底的塑性弯曲(plastic bending)，T剥离测试期间粘合强度随剥离角而增大。
在亚利桑那州钱德勒的网络URL为http://www.rogerscorporation.com的Rogers公司发表的标题为“Maximizing Flex Life in Flexible Printed Circuits”的关于材料属性的文章中，描述了通过完全利用材料的柔性(flexibility)从而在制造期间适应封装，来最大化印刷电路的抗挠寿命(flex life)的方法。
IPC Expo 2003上介绍的Tad Bergstresser等人的“Adhesiveless Copper onPolyimide Substrate with Nickel-Chromium Tiecoat”(网络URL为http://www.circuiTree.com/CDA/ArticleInformation/features/BNP_ Features_ Item/0，2133，100993.0O.html)这另一公开中，论述了具有镍-铬结合层(tiecoat)时聚酰亚胺衬底上的铜的特性。热老化、高压室暴露和暴露于镀金之后，测量剥离强度且与其它粘合层构造的结果比较。与没有粘合层相比，NiCr粘合层充当铜与聚酰亚胺之间的阻挡物(barrier)且减小热老化之后的粘附损失(adhesion loss)。NiCr粘合层显著改善从中性钾金氰化物浴(potassium gold cyanide bath)电镀之后的粘合保持。其性能与具有铬粘合层的样品相当且好于具有蒙耐合金(monel)粘合层的样品。镀金之后的剥离损失由铜底切(undercut)引起，在铜-聚酰亚胺界面处的该铜底切由镀液的成分导致。
通常的堆叠晶片应用要求芯片被薄化到50至125μm的范围。这导致特定的操作要求以及特定的加工以处理翘曲。当一个芯片置于另一个上时该通常的堆叠晶片布置还要求高定位精度，否则的话，会以电故障告终。与堆叠芯片应用相关的其它问题包括过多的环氧树脂覆盖键合焊盘(bonding pad)以及必须应用特定的衬底设计规则(design rule)和用于线键合的环路高度(loop height)以防止短路。本发明解决这些和其它问题同时仍提供许多相同的好处，例如减小的空间、节省重量和甚至增强的性能。
发明内容
因此，本发明的目的是提供含有折叠成三维布置的至少两个芯片的电完整***或者子***。
本发明的另一目的是提供一种用于将热去除元件集成到该三维布置中的方法。
本发明的再一目的是提供一种组件，其包括封装成最终封装的多个芯片、PCB、或转换器(transposer)，其中所述多个芯片被预连接，让至少一个芯片接触该封装。
本发明的又一目的是提供将被结合在柔性芯片布置中的不同衬底材料和/或晶体取向制成的芯片。
本发明的又一目的是实现作为较小晶片或芯片的函数的增加的产率。
本发明的又一目的是提供最大化整个或部分芯片的功能冗余度的芯片布置。
本发明的这些和其它目的通过包括多个堆叠芯片的三维柔性封装实现，所述封装包括至少两个集成电路芯片，其中它们中的至少一个提供用于到另外的芯片的电连接的互连路径且至少一个芯片具有到外部封装或PCB的另外的互连布线。
在本发明的一个方面中，提供一种柔性结构和一种互连折叠为三维布置的芯片的方法，当安装到外部封装或PCB上时所述三维布置消耗更小的空间(aerial space)。热传导膜(membrane)或导管(conduit)折叠到所述组件中从而提供用于去除废热的装置。
所述三维扩展芯片布置被附于硅载体(silicon carrier)或一些其它封装上***(SOP)以显著减小每个布置所利用的SOP有效区(real estate)的量且大大扩展该SOP的能力。该堆叠结构不需要所述衬底的过度薄化。200至300μm厚的衬底能被便利地使用。
在本发明的另一方面中，对垂直定位精度没有要求；仅要求用于形成该柔性互连的通常的x、y定位，其用标准处理设备实现。当将该柔性芯片布置线键合到该封装时，线键合(wire bonding)在一个层面(level)进行。与其它堆叠芯片布置不同，不需要防止多层面回路的短路的特殊接地规则(ground rule)。在一实施例中，所述多个堆叠芯片以非平行的芯片布置排列。
附图说明
包括在说明书中且构成说明书的一部分的附图示出本发明的当前优选实施例，且与上面给出的概要描述以及下文给出的优选实施例的详细描述一起用来说明本发明的原理。
图1-3示出横截面图，显示单独的晶片或芯片在具有释放层(releaselayer)的临时载体上的定位。还示出由柔性电介质层形成的电互连，该柔性电介质层还用于将芯片彼此物理附着，同时允许芯片以各种构造在彼此上的折叠；
图4示出具有前述互连柔性电介质的芯片的平面图；
图5示出添加有另一芯片的三维组件，所述另一芯片用作到最终封装、载体、或者PCB的界面；
图6和7是折叠芯片的横截面图，其中增加的热导管蜿蜒通过该芯片组件；
图8是折叠组件的横截面图，传热材料被引入到该封装中；
图9至11示出各种实施例，显示组件如何连接到封装、载体或PCB；
图12示出附着到衬底或PCB的柔性折叠多芯片组件的***阵列。
具体实施方式
图1示出释放层20沉积在其上的临时载体10的横截面图。释放层的目的是使得能够在其上附着集成电路芯片100、110、120和与芯片有关的其它构造，后者在后面的步骤与临时载体分开。优选地，临时芯片载体10是透明衬底例如石英、硼硅酸盐或能经受BEOL工艺温度的某些相似类型材料，尽管如本领域技术人员公知，其它材料也能被使用。释放层20优选为旋涂(spin-on)有机绝缘层，例如聚酰亚胺。释放工艺在Arjavalingam等人的美国专利No.5,258,236“Multi-layer Thin Film Structure and Parallel ProcessingMethod for Fabricating Same”中作了描述。芯片100、110和120可包含任何结构、器件、或者模块，例如完全集成的电路或者彼此互连或附着到公共模块的微机电***(MEMS)。
图2示出图1的相同截面，具有毯式沉积在其上的电介质层30。电介质材料优选为柔性且具有良好的介电特性。这样的材料的示例包括聚酰亚胺或苯并环丁烯(BCB)。具有层30的目的在于物理连接各种芯片或模块100、110、120，且通过将形成在其中的导电线等提供用于互连的媒质(medium)。它还用作组件的最终构造的机械支承。
图3示出置于柔性层30中或其上的互连线40和柱(stud)(下文也称为通路(via))50的添加。互连优选由导电材料例如铝或铜制成，从而提供各个芯片100、110和120之间的足够的电连接。金属线优选定标至容纳所要求的必需的信号和功率。它们还被成形为提供与实现将芯片折叠为其最终组件所要求的弯曲有关的最佳可靠性。因此，有利的是以矩形横截面来构造该互连，使曲率半径(radius of curvature)与较薄的维度一致。举例来说，互连被构造为30μm宽但仅2μm深或厚。以此方式，它们更可能容易地弯曲同时仍具有大的横截面积。理想地，在它们的最终组装期间它们被形成或弯曲仅一次。
图4是图3的平面图。其中更详细地示出形成在柔性层30内的多个平行互连40，其将各个芯片100、110和120互连。
图5示出通过柔性电介质层30物理连接且通过各互连线40电连接的四个芯片100、110、120和130的平面图。此外，图5示出芯片130设置有键合焊盘60，其被制成用于能够将它们连接到载体、封装或用于提供到最终组件的电连接的任何其它装置。
图6示出芯片如何通过选择性去除释放层20而从载体10释放从而允许它们被折叠以形成堆叠组件的横截面图。
与现有技术三维组件对比，所述现有技术三维组件例如为立方体存储器，其中芯片以刚性结构一个堆叠在另一个上，芯片总是面对一个方向，在本发明中，芯片实际上被这样折叠使得例如组件的第一芯片110将实际上面对第二芯片100的底部；组件的第三芯片120的底部将面对第二芯片100的顶部，等等。此外，因为以离散(discrete)、柔性互连的方式提供互连，所以整个组件允许芯片之间的一定量的移动。互连40的长度部分由芯片折叠的顺序(order)确定。举例来说，将芯片100连接至芯片110的互连40优选地短于连接芯片110和120的互连。这示出在图7中，图7示出完全折叠布置的全部三个芯片。
图8示出与图7所示的布置类似的布置。其中描绘了也称为散热器(thermal sink)的热传导层或管道(pipeline)300的增加，其也折叠到堆叠中从而提供用于去除各种芯片产生的废热的有效装置。导热体300能连接至封装外部的热交换器(未示出)。另外，组件的构造期间可将热传导通路200引入到互连层面(interconnect level)从而允许芯片的某些内部部分与散热层300之间的直接热接触。
图9是与图5所示相同的结构在将芯片100和120接连折叠到110上之后的顶视图。另外，图9示出折叠组件可如何线键合到载体或封装500。沿芯片130的周边的线键合焊盘60通过离散的线520在焊盘510处被连接到封装500，从而提供到二级封装，即硅衬底500的必要互连。本领域从业者将意识到，衬底500通常设置有各种布线平面(wiring plane)从而互连形成各种组件的全部芯片。每个堆叠组件的各芯片130设置有它们自己的不同的覆盖区，从一个组件到另一个组件其可以变化。
图10示出更紧凑的组件，当芯片110配置有球栅格阵列(BGA)或C4(受控塌陷芯片连接器，也称为“焊料球”)互连***500时其是可行的。这允许该堆叠直接键合到载体600，消除了图9所示的芯片130的额外覆盖区。在本示例中，示出芯片110具有到用于柔性互连的背面的直通连接(through connection)。芯片110可以以传统方式配置，其中柔性互连在如图11所示BGA或C4的芯片面上连接。
图12示出如何使用柔性芯片布置650来扩展能力和减小硅载体700或类似SOP装置上所需要的空间量。此相同的概念可利用如前所述的其它连接方法实施。SOP装置可含有其它芯片、单级或多级互连布线以及需要大量有效区的无源元件例如电感器、变压器和电容。通过结合SOP和柔性芯片堆叠，能够很大地增强整体***的功能。此布置使得能够将各种芯片功能和材料集成到单个封装中，否则将需要将被连接在一起的多个SOP或类SOP装置。为了清楚起见并将焦点保持在本发明的目的上，载体700的互连、无源器件和其它元件未示出。
鉴于阅读前述描述之后毫无疑问地许多替换和修改对本领域普通技术然员来说是明显的，所以应该理解，以示例方式显示和说明的特定实施例无意被认为是限制。因此，对优选实施例的细节的参考无意限制权利要求的范围，权利要求本身仅陈述本发明的必要特征。
工业实用性
本发明用于无线通讯领域，更特别地，用于所有电话机等。

Claims (18)

1.一种柔性芯片堆叠芯片组件，包括：
多个芯片(100、110、120)，其折叠在彼此之上且通过离散绝缘互连(40)彼此柔性连接；以及
一个芯片(130)，其安装在芯片载体(500)上且柔性连接到所述多个芯片(100、110、120)之一，提供所述多个芯片与所述芯片载体(500)上的焊盘(510)之间的电连接。
2.如权利要求1所述的柔性芯片堆叠芯片组件，其中所述离散绝缘互连由铝或铜制成。
3.如权利要求1所述的柔性芯片堆叠芯片组件，其中所述互连的长度由所述多个芯片折叠的顺序确定。
4.如权利要求1所述的柔性芯片堆叠芯片组件，还包括折叠在所述多个芯片中的热导管从而提供用于去除所述多个芯片产生的废热的装置。
5.如权利要求4所述的柔性芯片堆叠芯片组件，其中所述多个芯片中的至少一个芯片物理连接到所述热导管。
6.如权利要求1所述的柔性芯片堆叠芯片组件，其中所述多个芯片的第一芯片的底表面面对所述多个芯片中的第二芯片的底表面，同时所述多个芯片中的第三芯片的底部面对所述多个芯片中的所述第二芯片的顶部。
7.如权利要求1所述的柔性芯片堆叠芯片组件，其中所述多个芯片(100、110、120)布置为所述多个芯片彼此平行定位。
8.如权利要求1所述的柔性芯片堆叠芯片组件，其中所述芯片载体(500)为硅衬底、封装上***、转换器、或印刷电路板。
9.如权利要求1所述的柔性芯片堆叠芯片组件，其中所述多个芯片非平行排列。
10.一种柔性芯片堆叠芯片组件，包括：
多个芯片(100、110、120)，其柔性折叠在彼此之上且通过柔性离散绝缘互连(40)彼此连接，其中最底部的芯片(110)设置焊料球(550)的栅格阵列来进行所述多个芯片与芯片载体(600)上的焊盘的电接触。
11.如权利要求10所述的柔性芯片堆叠芯片组件，还包括热导管，其蜿蜒在所述多个芯片之间。
12.如权利要求11所述的柔性芯片堆叠芯片组件，其中所述多个芯片(100、110、120)中的至少一个芯片物理接触所述热导管。
13.一种多芯片组件的阵列，包括：
多个柔性堆叠芯片组件，所述组件中的每个分别包括多个芯片(100、110、120)，所述多个芯片折叠到彼此之上且通过柔性离散绝缘的互连彼此连接，其中所述多个柔性堆叠芯片组件的一个组件中的至少一个芯片附于芯片载体(500)。
14.如权利要求13所述的多芯片组件的阵列，其中所述芯片载体(500)为硅衬底、封装上***、多芯片模块或转换器。
15.如权利要求13所述的多芯片组件的阵列，还包括折叠在所述多个芯片内的热导管，从而提供用于去除所述多个芯片产生的废热的装置。
16.一种形成柔性芯片堆叠芯片组件的方法，包括步骤：
将多个芯片(100、110、120)折叠在彼此之上，通过柔性离散绝缘互连(40)将所述多个芯片(100、110、120)中的一个芯片连接到另一个；以及
将至少一个芯片安装在芯片载体(500)上，所述至少一个芯片电耦接到所述多个芯片从而提供所述多个芯片与所述芯片载体(500)上的焊盘(510)之间的电连接。
17.一种提供柔性芯片堆叠芯片组件的方法，包括步骤：
将多个芯片(100、110、120)折叠在彼此之上，通过柔性离散绝缘互连将所述多个芯片(100、110、120)中的一个芯片连接到另一个，其中所述多个芯片(100、110、120)中的最底部的芯片(110)设置焊料球栅格阵列来进行所述多个芯片与芯片载体(500)上的焊盘(510)之间的电接触。
18.一种构造多芯片组件的阵列的方法，包括步骤：
提供多个柔性堆叠芯片组件，所述组件中的每个分别包括多个芯片(100、110、120)，所述多个芯片折叠在彼此之上且通过柔性离散绝缘互连彼此连接，其中所述多个柔性堆叠芯片组件的一个组件中的至少一个芯片附于芯片载体(500)。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103523739A (zh) * 2013-11-05 2014-01-22 华进半导体封装先导技术研发中心有限公司 环境mems传感器三维柔性基板封装结构及制作方法
CN104465548A (zh) * 2014-12-10 2015-03-25 华进半导体封装先导技术研发中心有限公司 一种三维柔性封装结构及其注塑成型方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7759167B2 (en) * 2005-11-23 2010-07-20 Imec Method for embedding dies
KR100726892B1 (ko) 2006-03-17 2007-06-14 한국과학기술원 3차원 칩 적층 패키지 모듈 및 이의 제조방법
KR101519440B1 (ko) * 2007-10-04 2015-05-13 삼성전자주식회사 구성 가능한 수직 입출력 라인을 가지는 적층된 반도체 장치 및 그 방법
US7473618B1 (en) 2008-04-22 2009-01-06 International Business Machines Corporation Temporary structure to reduce stress and warpage in a flip chip organic package
WO2013087101A1 (en) * 2011-12-14 2013-06-20 Reinhardt Microtech Gmbh Substrate-supported circuit parts with free-standing three-dimensional structures
EP2938265B1 (en) * 2012-12-28 2023-02-15 Philips Image Guided Therapy Corporation Intravascular ultrasound imaging apparatus
US20140224882A1 (en) * 2013-02-14 2014-08-14 Douglas R. Hackler, Sr. Flexible Smart Card Transponder
US9984962B2 (en) * 2015-08-31 2018-05-29 Arizona Board Of Regents On Behalf Of Arizona State University Systems and methods for hybrid flexible electronics with rigid integrated circuits
KR102497583B1 (ko) 2015-10-27 2023-02-10 삼성전자주식회사 유연한 연결부를 갖는 반도체 장치 및 그 제조방법
EP3206229B1 (en) 2016-02-09 2020-10-07 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Methods of manufacturing flexible electronic devices
CN115565890B (zh) * 2022-12-07 2023-04-18 西北工业大学 一种折叠式多芯片柔性集成封装方法及柔性集成封装芯片

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933810A (en) * 1987-04-30 1990-06-12 Honeywell Inc. Integrated circuit interconnector
JP2002009230A (ja) * 2000-06-20 2002-01-11 Seiko Epson Corp 半導体装置
CN1396657A (zh) * 2001-07-11 2003-02-12 日本电气株式会社 减小尺寸的堆叠式芯片大小的组件型半导体器件
US20030080438A1 (en) * 2001-10-29 2003-05-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor module
US6572387B2 (en) * 1999-09-24 2003-06-03 Staktek Group, L.P. Flexible circuit connector for stacked chip module

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2985484B2 (ja) * 1992-03-19 1999-11-29 株式会社日立製作所 半導体装置とその製造方法
US5028983A (en) * 1988-10-28 1991-07-02 International Business Machines Corporation Multilevel integrated circuit packaging structures
US5239448A (en) * 1991-10-28 1993-08-24 International Business Machines Corporation Formulation of multichip modules
US5198965A (en) * 1991-12-18 1993-03-30 International Business Machines Corporation Free form packaging of specific functions within a computer system
FR2704690B1 (fr) * 1993-04-27 1995-06-23 Thomson Csf Procédé d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procédé et application à l'interconnexion de pastilles en trois dimensions.
US6121676A (en) * 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
JP3611957B2 (ja) * 1997-10-29 2005-01-19 日東電工株式会社 積層型実装体
JPH11249215A (ja) * 1998-03-06 1999-09-17 Olympus Optical Co Ltd フレキシブルプリント配線基板を有するカメラ
JP2000088921A (ja) * 1998-09-08 2000-03-31 Sony Corp 半導体装置
JP3879803B2 (ja) * 1999-03-25 2007-02-14 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP2001085608A (ja) * 1999-09-17 2001-03-30 Sony Corp 半導体装置
EP1156705B1 (en) * 1999-10-01 2006-03-01 Seiko Epson Corporation Wiring board, semiconductor device and method of producing, testing and packaging the same, and circuit board and electronic equipment
JP3721893B2 (ja) * 1999-10-20 2005-11-30 セイコーエプソン株式会社 半導体装置、ならびに電子機器
JP4135284B2 (ja) * 1999-12-07 2008-08-20 ソニー株式会社 半導体モジュールおよび電子回路装置
JP3855594B2 (ja) * 2000-04-25 2006-12-13 セイコーエプソン株式会社 半導体装置
JP2002009229A (ja) * 2000-06-20 2002-01-11 Seiko Epson Corp 半導体装置
JP2002270759A (ja) * 2001-03-14 2002-09-20 Matsushita Electric Ind Co Ltd 半導体チップ及びマルチチップモジュール
US7071547B2 (en) * 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933810A (en) * 1987-04-30 1990-06-12 Honeywell Inc. Integrated circuit interconnector
US6572387B2 (en) * 1999-09-24 2003-06-03 Staktek Group, L.P. Flexible circuit connector for stacked chip module
JP2002009230A (ja) * 2000-06-20 2002-01-11 Seiko Epson Corp 半導体装置
CN1396657A (zh) * 2001-07-11 2003-02-12 日本电气株式会社 减小尺寸的堆叠式芯片大小的组件型半导体器件
US20030080438A1 (en) * 2001-10-29 2003-05-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103523739A (zh) * 2013-11-05 2014-01-22 华进半导体封装先导技术研发中心有限公司 环境mems传感器三维柔性基板封装结构及制作方法
CN104465548A (zh) * 2014-12-10 2015-03-25 华进半导体封装先导技术研发中心有限公司 一种三维柔性封装结构及其注塑成型方法

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