CN100445854C - Vertical assigned mode LCD device and manufacturing method of its array base plate - Google Patents
Vertical assigned mode LCD device and manufacturing method of its array base plate Download PDFInfo
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- CN100445854C CN100445854C CNB2006101179071A CN200610117907A CN100445854C CN 100445854 C CN100445854 C CN 100445854C CN B2006101179071 A CNB2006101179071 A CN B2006101179071A CN 200610117907 A CN200610117907 A CN 200610117907A CN 100445854 C CN100445854 C CN 100445854C
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- liquid crystal
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- pixel electrode
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- slit
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 238000002161 passivation Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 229910004205 SiNX Inorganic materials 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 12
- 230000008520 organization Effects 0.000 abstract 1
- 238000002834 transmittance Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 50
- 239000010408 film Substances 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- -1 and when OFF state Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- MEYZYGMYMLNUHJ-UHFFFAOYSA-N tunicamycin Natural products CC(C)CCCCCCCCCC=CC(=O)NC1C(O)C(O)C(CC(O)C2OC(C(O)C2O)N3C=CC(=O)NC3=O)OC1OC4OC(CO)C(O)C(O)C4NC(=O)C MEYZYGMYMLNUHJ-UHFFFAOYSA-N 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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Abstract
The invention discloses a liquid crystal device with vertical distribution model and manufacturing methods for its array substrate. The liquid crystal device with vertical distribution model includes a color film top substrate, a bottom array substrate, a liquid crystal layer between the top substrate and bottom substrate. There are pixel electrodes on the bottom array substrate surface. A number of slits forms on the pixel electrodes, between which there is a regional vertical electric field. By the reservation of semiconductor layer, vertical electric field can be formed in the slit area. At the open state, liquid crystal molecular horizontal organization will also occur, improve the open state transmittance of LCD devices.
Description
Technical field
The present invention relates to the method that a kind of liquid crystal indicator and array base palte thereof are made, particularly relate to the manufacture method of the liquid crystal indicator and the array base palte thereof of vertical alignment mode.
Background technology
LCD is to utilize the variation that is clipped in electric field intensity on the liquid crystal molecule, and the power that changes the orientation control printing opacity of liquid crystal molecule is come display image.Liquid crystal indicator is made of backlight module, polaroid, array infrabasal plate, color film (CF) upper substrate and the layer of liquid crystal molecule that is clipped between the upper and lower base plate usually.A large amount of pixel electrodes is arranged on the array base palte, and the electric field intensity change modulates between the public electrode on the CF substrate and the pixel electrode of infrabasal plate the orientation of liquid crystal molecule.
(VA pattern) liquid crystal indicator of vertical alignment mode uses negative liquid crystal, and when OFF state, liquid crystal molecule is arranged perpendicular to upper and lower base plate, so can obtain black preferably attitude, realizes higher contrast ratio.In order to obtain visual angle preferably, the liquid crystal indicator of vertical alignment mode adopts the mode of multidomain usually at present, and this display mode is called as " Multi-Domain Vertical AlignmentMode " (MVA pattern).Mainly by realizing in the surface of color film or array base palte making projection or slit.When pixel is applied voltage, these projectioies or slit cause potential surface that rugged change takes place, liquid crystal molecule just is orientated to different directions under the electric field action of this rugged change, thereby realized multidomain (domain), as disclosed 4 farmlands (Domain) structure as shown in Figure 1 in the European patent EP 0884626.
In present array base palte manufacturing process, generally include following steps: on glass substrate, form the grid layer pattern; On grid layer, form insulating layer film and semiconductor tunic then; Keep the semiconductor layer at thin film transistor (TFT) (TFT) device place, etch away other regional semiconductor materials; Form drain electrode and source electrode line pattern; Form the passivation protection layer above the drain electrode, and on the passivation protection layer, etch contact hole; Form the pixel electrode pattern that has slit at substrate surface at last; By the vertical alignment mode liquid crystal indicator of said method realization, as shown in Figure 2, at slit 29 places; because missing pixel electrode 27; and be insulating protective layer 26 below the slit 29, therefore no conductive layer does not have vertical electric field in this zone; thereby no matter be OFF state or ON state; liquid crystal molecule 31 all keeps original state basically, and arrange on vertical substrate 2 surfaces, shows as black attitude on showing; the width of black line is bigger, and this will certainly reduce transmitance greatly.
Summary of the invention
The technical matters that the present invention solves provides a kind of liquid crystal indicator of the vertical alignment mode that can improve the ON state transmitance and the manufacture method of array base palte thereof.
The present invention is achieved in that the liquid crystal indicator of vertical alignment mode comprises a color film upper substrate, an array infrabasal plate, is filled in the layer of liquid crystal molecule between the upper and lower base plate, described array infrabasal plate surface is formed with pixel electrode, remain with semiconductor layer below a plurality of slits of formation on the pixel electrode, wherein said pixel electrode.
Another technical scheme of the present invention is achieved in that the manufacturing method of array base plate of the liquid crystal indicator of vertical alignment mode, comprises the steps: to provide a substrate; On described substrate, form the grid layer pattern; On described grid layer, form dielectric film and semiconductor layer; The etching semiconductor layer; Form drain electrode and source electrode line pattern; Form the passivation protection layer above the drain electrode, and on the passivation protection layer, etch contact hole; Form the pixel electrode pattern that has slit at substrate surface; Wherein keep the semiconductor layer of pixel region during the etching semiconductor layer, described slit is connected with drain line by contact hole.
Based on above-mentioned design, the liquid crystal indicator of vertical alignment mode of the present invention is owing to kept semiconductor layer below the pixel electrode, therefore, pixel electrode slit place has also possessed with the same current potential of pixel electrode, be formed with vertical electric field, the liquid crystal molecule that is in slit areas during ON state also can the occurred level orientation.Though because the direction of orientation difference of the liquid crystal molecule of slit both sides, can cause the middle stria that has a black of slit, but its black line that brings with respect to the slit of existing structure seems very tiny, has improved the ON state transmitance of liquid crystal indicator greatly, thereby has increased aperture opening ratio.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not construed as limiting the invention.
Description of drawings
Fig. 1 is the dot structure synoptic diagram in the existing MVA pattern;
Fig. 2 is the orientation synoptic diagram that the pixel electrode slit is in liquid crystal molecule under the electric field in the existing MVA pattern;
Fig. 3 is the dot structure synoptic diagram of the embodiment of the invention;
Fig. 4 is the schematic cross-section of infrabasal plate in the embodiment of the invention;
Fig. 5 is the orientation synoptic diagram that the pixel electrode slit is in liquid crystal molecule under the electric field in the vertical alignment mode of the present invention;
Fig. 6 A-6F is the schematic flow sheet of array base palte of the making vertical alignment mode liquid crystal indicator of the embodiment of the invention.
Among the figure:
1. color film upper substrate 11. projectioies or slit (Rib)
2. array infrabasal plate 20. substrates 21. gate lines 22. dielectric films
23. semiconductor layer 24. drain lines 25. source electrode lines 26. passivation protection layers
27. pixel electrode 28. contact holes 29. slits
30. thin film transistor (TFT) (TFT) 301. conducting channels
3. layer of liquid crystal molecule 31. liquid crystal molecules
Embodiment
The invention will be further described below in conjunction with accompanying drawing and exemplary embodiments.
Fig. 3 is the dot structure synoptic diagram of the embodiment of the invention; Fig. 4 is the schematic cross-section of infrabasal plate in the embodiment of the invention; Fig. 5 is the orientation synoptic diagram that the pixel electrode slit is in liquid crystal molecule under the electric field in the vertical alignment mode of the present invention.
With reference to figure 3; Fig. 4; Fig. 5; the liquid crystal indicator of vertical alignment comprises a color film upper substrate 1; one thin film transistor (TFT) array infrabasal plate 2; be filled in the layer of liquid crystal molecule 3 between upper and lower base plate 1 and 2; array infrabasal plate 2 surfaces are formed with pixel electrode 27; pixel electrode can be formed by indium tin oxide (ITO); form a plurality of slits 29 on the pixel electrode 27; the surface of color film upper substrate 1 is formed with a plurality of projectioies or slit 11 (does not illustrate; please refer to Fig. 1); and it is parallel relative with slit 29 dislocation on pixel electrode 27 surfaces; slit 29 places remain with semiconductor layer 23; can realize by reservation semiconductor layer 23 below pixel electrode 27; at this moment; be followed successively by passivation protection layer 26 below the pixel electrode 27; semiconductor layer 23; dielectric film 22; glass substrate 20; pixel electrode 27 is connected with drain line 24 by the contact hole on the passivation protection layer 26 28; at this moment; slit 29 zones are owing to remain with semiconductor layer 23; therefore; pixel electrode slit place has also possessed with the same current potential of pixel electrode, is formed with vertical electric field.
Fig. 6 A～6F is the schematic flow sheet of array base palte of the making vertical alignment mode liquid crystal indicator of the embodiment of the invention.
The manufacture method of the array base palte of vertical alignment mode liquid crystal indicator comprises the steps:
At first, with reference to figure 6A, one substrate 20 is provided, as a transparent glass substrate, on substrate 20, form first metal conducting layer, as the good Al of electric conductivity, Ta or Cr metal level, utilize traditional exposure, development and the above-mentioned metal level of etching manufacturing process patternization to form a gate line 21 then, gate line 21 has a teat to be made for the usefulness of thin film transistor (TFT) gate electrode.
Next, with reference to figure 6B, in order to prevent that grid layer pattern and other layer patterns are short-circuited, and produce corresponding thin film transistor (TFT) (TFT) 30 devices, after gate line 21 etchings are finished, utilize film technique, as the CVD film forming, growth dielectric film 22 is as the SlNx film, and semiconductor layer 23, semiconductor layer 23 can be made of a-Si lower floor and n+a-Si upper strata.
Next, with reference to figure 6C, in order to keep semiconductor layer 23 or n+a-Si layer at pixel region, produce the conducting channel 301 at thin film transistor (TFT) 30 device places simultaneously, use the GTM technology at conducting channel 301 places, realization etches away the semiconductor layer 23 beyond the pixel region, only carves disconnected n+a-Si layer simultaneously at conducting channel 301 places.
With reference to figure 6D, after the island is carved and is finished, on substrate 20, carry out the sputter (sputter) of drain electrode layer, form second metal level, as the good Al of electric conductivity, Ta or Cr metal level, by after single exposure, development, the etching, on above-mentioned metal level, etch the pattern of drain line 24 and source electrode line 25 then, realize the Ohmic contact of drain line 24 and semiconductor layer 23 simultaneously.
With reference to figure 6E, in order to protect pattern and the TFT device 30 on second metal level, after drain line 25 etchings are finished, generate one deck insulation passivation protection layer 26 on substrate 20 surfaces, as the SiNx layer, and on passivation protection layer 26, etch contact hole 28.
Next; with reference to figure 6F; form a transparency conducting layer at passivation protection layer 26 upper surface and sidewall; as indium tin oxide layer (ITO); as pixel electrode; the contact hole 28 that conductive layer comes out by the above-mentioned steps etching is connected with drain line 24, by single exposure, development, etching, forms at least 1 slit 29 at conductive layer.
In the prior art, the array base palte of liquid crystal indicator only keeps the semiconductor layer at film transistor device 30 places usually, and the embodiment of the invention is except TFT device place, the semiconductor layer of pixel electrode area also keeps, and be connected with drain line, therefore, pixel electrode slit place has also just possessed with the same current potential of pixel electrode.Pixel electrode slit place also possesses vertical electric field, and when ON state, this part liquid crystal molecule also can be orientated by occurred level, thereby has improved the ON state transmitance of liquid crystal indicator, has increased aperture opening ratio.
Effect of the present invention, can obtain following result in order better to illustrate by simulation to liquid crystal indicator:
Model configuration is:
Pixel size: 100um*300um; The thick 4.0um of liquid crystal cell;
Rib height: 1.4um; Rib width: 10um
Pixel electrode slit width: 10um;
Distance between Rib and the pixel electrode slit: 20um
The light intensity of supposing incident light is 1
| Common MVA pattern | Adopt VA pattern of the present invention | |
| Dark attitude light leak | 0.00129 | 0.00127 |
| The ON state light intensity | 0.228 | 0.252 |
| Contrast | 177 | 200 |
By above result as can be known, the ON state transmitance of the liquid crystal indicator of structure of the present invention can improve 10%, and contrast also can corresponding improve more than 10%.
The above only is the preferred embodiments of the present invention, and all equivalences of being done within the scope of the invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (7)
1. the liquid crystal indicator of a vertical alignment mode comprises
One color film upper substrate;
An array infrabasal plate;
One layer of liquid crystal molecule is filled between the upper and lower base plate;
Described array infrabasal plate surface is formed with pixel electrode, forms a plurality of slits on the pixel electrode;
Described color film upper substrate surface is provided with projection or slit, and described projection or slit are relative with the slit dislocation on the described pixel electrode;
It is characterized in that remaining with semiconductor layer below the described pixel electrode layer.
2. liquid crystal indicator according to claim 1 is characterized in that described semiconductor layer is made of a-Si of lower floor and upper strata n+a-Si.
3. liquid crystal indicator according to claim 1 is characterized in that described pixel electrode material is an indium tin oxide.
4. the manufacturing method of array base plate of the liquid crystal indicator of a vertical alignment mode comprises the steps:
One substrate is provided;
On described substrate, form the grid layer pattern;
On described grid layer, form dielectric film and semiconductor layer;
The etching semiconductor layer;
Form drain electrode and source electrode line pattern;
Form the passivation protection layer above the drain electrode, and on the passivation protection layer, etch contact hole;
Form the pixel electrode pattern that has slit at substrate surface;
Wherein keep the semiconductor layer of pixel region during the etching semiconductor layer, described slit is connected with drain line by contact hole.
5. manufacture method according to claim 4 is characterized in that described dielectric film is the SiNx layer.
6. manufacture method according to claim 4 is characterized in that described semiconductor layer is made of a-Si of lower floor and upper strata n+a-Si.
7. manufacture method according to claim 4 is characterized in that described passivation protection layer is the SiNx layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101179071A CN100445854C (en) | 2006-11-02 | 2006-11-02 | Vertical assigned mode LCD device and manufacturing method of its array base plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101179071A CN100445854C (en) | 2006-11-02 | 2006-11-02 | Vertical assigned mode LCD device and manufacturing method of its array base plate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1967361A CN1967361A (en) | 2007-05-23 |
| CN100445854C true CN100445854C (en) | 2008-12-24 |
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| CNB2006101179071A Expired - Fee Related CN100445854C (en) | 2006-11-02 | 2006-11-02 | Vertical assigned mode LCD device and manufacturing method of its array base plate |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101441379B (en) * | 2008-11-17 | 2010-06-09 | 上海广电光电子有限公司 | Multiple-domain vertical orientating type liquid crystal display device and its manufacture method |
| CN102566158B (en) * | 2011-12-05 | 2014-12-17 | 深圳市华星光电技术有限公司 | Liquid crystal substrate and method for making same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6759281B1 (en) * | 1999-04-26 | 2004-07-06 | Samsung Electronics Co., Ltd. | Method of making a display switch having a contact hole through a passivation layer and a color filter |
| CN1530696A (en) * | 2003-03-13 | 2004-09-22 | ������������ʽ���� | Liquid-crystal displaying device and electronic apparatus |
| CN1677179A (en) * | 2004-03-31 | 2005-10-05 | 富士通显示技术株式会社 | Liquid crystal display device |
| CN1687834A (en) * | 2005-05-12 | 2005-10-26 | 友达光电股份有限公司 | Multi-zone vertical alignment nematic type liquid crystal display panel and driving method thereof |
-
2006
- 2006-11-02 CN CNB2006101179071A patent/CN100445854C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6759281B1 (en) * | 1999-04-26 | 2004-07-06 | Samsung Electronics Co., Ltd. | Method of making a display switch having a contact hole through a passivation layer and a color filter |
| CN1530696A (en) * | 2003-03-13 | 2004-09-22 | ������������ʽ���� | Liquid-crystal displaying device and electronic apparatus |
| CN1677179A (en) * | 2004-03-31 | 2005-10-05 | 富士通显示技术株式会社 | Liquid crystal display device |
| CN1687834A (en) * | 2005-05-12 | 2005-10-26 | 友达光电股份有限公司 | Multi-zone vertical alignment nematic type liquid crystal display panel and driving method thereof |
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| CN1967361A (en) | 2007-05-23 |
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Owner name: NANJING CEC PANDA LCD TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: SVA (GROUP) CO., LTD. Effective date: 20110621 |
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Effective date of registration: 20110621 Address after: 210038 Nanjing economic and Technological Development Zone, Jiangsu Province, Hengyi Road, No. 9, No. Patentee after: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd. Address before: 200233, Shanghai, Yishan Road, No. 757, third floor, Xuhui District Patentee before: SVA OPTRONICS |
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