CN100440732C

CN100440732C - Circuit for indipendently regulating rise and down boundary time of signal

Info

Publication number: CN100440732C
Application number: CNB2003101143714A
Authority: CN
Inventors: 夏濬
Original assignee: Etron Technology Inc
Current assignee: Etron Technology Inc
Priority date: 2003-11-14
Filing date: 2003-11-14
Publication date: 2008-12-03
Anticipated expiration: 2023-11-14
Also published as: CN1617447A

Abstract

The present invention relates to a circuit capable of independently adjusting the rising edge time and falling edge time of a signal. The circuit comprises a first delay element, a second delay element, a logic-functional element and a logic/functional element, wherein each delay element has an input section and an output section, and each input section is connected to a common input signal; the logic-functional element has two input sections and one output section, one input section is connected to an input signal, the other input section is connected to the output section of the first delay element, the output section is composed of a rise delay signal, and a controlled rising edge delay exists between the rising edge of the input signal and the rising edge of the rise delay signal; the logic/functional element has two input sections and one output section, one input section is connected to the input signal, the other input section is connected to the output section of the second delay element, the output section is composed of a fall delay signal, and a controlled falling edge delay exists between the falling edge of the input signal and the falling edge of the fall delay signal. In addition, the present invention also discloses a device combining the rise delay signal and the fall delay signal to a common delay output signal.

Description

A kind of circuit that can independently adjust the rise and fall border time of a signal

Technical field

The present invention is a kind of about input buffer circuit, refers to a kind of circuit that can independently adjust the rise and fall border time of a signal especially.

Background technology

Great majority are input to integrated circuit, and (integrated circuit, IC) the signal adjustment (signal conditioning) that must pass through of Zhuan Zhi input signal is handled.See also figure one, represent an IC device 10.In the system that this utmost point is simplified, an input: the input signal SIGNAL 14 that the stitch of receiving system 10 outsides is imported.One input circuit is also referred to as input buffer circuit, is made up of inverter I1 22 and inverter I2 26 at IC device 10.Wayside signaling SIGNAL_IC 18 is produced behind input circuit by input signal SIGNAL 14.

Inverter I1 22 and inverter I2 26 are made of transistor (transistor) device.These transistor units do not show on the figure, require a bit of time transition status.Be called as time of delay or border time of delay these change-over times.The sequential chart of figure one is represented the waveform of typical SIGNAL 14 and SIGNAL_IC 18.The transformation of SIGNAL 14 from the low state to the high state produces a rising border (rising edge).SIGNAL_IC 18 is this rising border and then, therefore has similar rising border.In the time delay of 18 of SIGNAL 14 and the SIGNAL_IC border time delay (rising edge time delay) that is defined as rising, be expressed as Tr in the circuit.In like manner, decline border time delay (falling edge time delay) is expressed as Tf.

In the utilization of many input circuits, the border time delay is an epochmaking parameter.Particularly installing or double data rate (double data rate as asynchronous (asynchronous), DDR) dynamic random access memory (Dynamic Random Access Memory, DRAM) in Zhuan Zhi the system, the important operation of device is exactly the time of boundary transition.In other words, rising border time delay and decline border time delay need be carefully controlled.Prior the considering of the present invention is essential independent control rising border time delay Tr and decline border time delay Tf.Tradition utilizes the very not suitable independent edges that is used to provide of buffer circuits to postpone control.The control method that many borders that are fit to this simple inverter circuit postpone is well-known in this field.Yet these methods can not accomplish to make rising border time delay and decline border time delay to be changed independently.For instance, it is not to cause rising border time delay to descend that attempt increases decline border time delay, and rising border time delay is risen.

Several previous and input buffer borders postpone the invention of relevant method and circuit just like United States Patent (USP) case numbers 6,294,939 by described a kind of method and the circuit of Mr. McClure in order to cushion as data input.Utilize different paths to increase or lower border conduction (propagation).Yet this circuit is designed to leach noise from input data, and rise and fall postpone to be designed to equate.United States Patent (USP) case numbers 6,313,681 by Mr.'s Yoshikawa disclosed one diverse delay circuit, one delay element includes a comparator (competitor), is used in each positive delay path (positive delay path) and the negative delay path (negative delay path).United States Patent (USP) case numbers 6,069,511 is by in disclosed method of Mr. Mohan and the circuit, by rate of change (slew rate) control signal rising/fall time.

Summary of the invention

Main purpose of the present invention provides a kind of efficient and circuit that can make in a large number, with the rising and the arrangement of time of fall delay border of independent control one signal.

Secondary objective of the present invention provides a kind of circuit, includes to be used for rising or the delay individual delay element on decline border.

Another purpose of the present invention is to utilize different reverser groups, and control is risen or the decline border postpones to reach.

Another object of the present invention is to utilize increases inverter, increases uneven size between electric capacity or inverter and control length of delay in the inverter group.

It is a kind of in conjunction with rising delay signal and the fall delay signal device to common delay output signal that a further object of the present invention is to provide.

For reaching above-mentioned purpose, the invention provides a kind of rising and the circuit of fall delay border time that can independently control a signal.This circuit at first includes one first delay element and one second delay element.Each delay element all has an input and an output.Next includes a logical AND function (AND function), has two input and outputs, and an input of this logical AND function is connected to input signal, and another input is connected to the output of this first delay element.The output of this logical AND function is made up of a rising delay signal, has an in check rising border to postpone between the rising border of the rising border of input signal and rising delay signal.Comprise a logic OR (OR function) at last, two inputs and an output are arranged.One of them input is connected to input signal, and another input is connected to the output of this second delay element.The output of this logic OR is made up of a decline inhibit signal, has a controlled decline border to postpone between the decline border of the decline border of input signal and fall delay signal.Realize a kind of device in conjunction with rising delay signal and the common delay output signal of fall delay signal to.

For reaching above-mentioned purpose, the invention provides a kind of rising and the fall delay border time method that can independently control a signal.This method includes: at first produce one first inhibit signal according to an input signal, produce one second inhibit signal according to this input signal, the generation of first inhibit signal and second inhibit signal is to utilize different inverter group.Produce a logical AND signal according to this input signal and first inhibit signal.This logical AND signal is made up of a rising delay signal, and this rising delay signal has a controlled rising border to postpone between the rising border of the rising border of input signal and rising delay signal.At last, produce a logic OR signal according to this input signal and second inhibit signal.This logic OR signal is made up of a decline inhibit signal, and this fall delay signal has a controlled decline border to postpone between the decline border of the decline border of input signal and fall delay signal.

Description of drawings

Fig. 1 is the prior art key diagram for input buffer circuit;

Fig. 2 can independently control the rising of a signal and the preferred embodiment of fall delay border time for of the present invention;

Fig. 3 is the specific embodiment for delay element of the present invention;

Fig. 4 is the delay element of making for the uneven transistor ratio of utilizing inverter;

Fig. 5 is the delay element for utilizing extra inverter to make;

Fig. 6 is the delay element for utilizing the node capacitor device to make;

Fig. 7 and Fig. 8 are the specific embodiments in conjunction with rising delay signal and the common delay output signal device of fall delay signal to for device of the present invention;

Embodiment

Preferred embodiment of the present invention discloses a kind of rising and the circuit of fall delay border time that can independently control a signal.More and then disclose to change the technology of the time of delay of each individual delay element.Disclose a kind of specific embodiment of, delay output signal device common at last in conjunction with rising delay signal and fall delay signal to.Clearly, the personage who is familiar with skill of the present invention can use and extend the present invention, and these do not break away from claim scope of the present invention.

See also Fig. 2, this is a preferred embodiment of the present invention, represents that several key characters of the present invention will be described in detail following.The present invention includes a circuit 30, can independently control the rising of an input signal 50 and the arrangement of time on fall delay border.This circuit 30 more includes one first delay element 34 and one second delay element 38.Each first delay element 34 and one second delay element 38 all have an input and an output.The input of each delay element is connected to a common input signal input signal 50.

A key character of the present invention is that two

delay elements

34,38 provide two individual delays paths to conduction (propagation) signal input signal 50.Behind first delay element, the 34 fixed delay T1, produce output DR 54.The arrangement figure of time represents the typical run state of circuit of the present invention.Input signal, input signal 50 expression be by the conversion of low state to high state, follows by high state to low state again.The operating condition of this first delay output DR 54 reflected input signals 50, but comprise one in order to comprise the fixedly T1 delay on rising and decline border.Second delay element 38 produces and exports DF 58 after postponing fixedly T2.The arrangement figure of time represents the typical run state of DF 58 signals.The operating condition of this second delay output DF 58 reaction input signals 50, but comprise one in order to comprise the fixedly T2 delay on rising and decline border.Further, since T1 and T2 are separate, just can select different length of delays, as shown in the figure.

Secondly, another key character of the present invention is a logical AND function 42, and logical AND function 42 includes two inputs and an output, and one of them input is connected to input signal input signal 50, and another imports first delay element output DR 54.The output of logical AND function 42 is made up of a RISE-DELAYED signal 62.See also sequential chart, rising delay signal 62 has an in check rising border to postpone T1 between the rising border of the rising border of input signal 50 and rising delay signal 62.Logical AND function 42 postpones the output that T1 only is used in rising delay signal 62 with the rising border.The decline border of output rising delay signal 62 is adjusted by input signal 50, and the delay that logic of propositions and function 42 is produced is enough little, and can ignore.

At last, the another key character of the present invention is a logic OR 46, and logic OR 46 includes two inputs and an output, and one of them input is connected to input signal input signal 50, and another imports second delay element output DF 58.The output of logic OR 46 is made up of a decline inhibit signal 66.Shown in sequential chart, logic OR 46 makes at the decline border of DF 58 delay T2 and is adjusted by output fall delay signal 66.The rising border of DF 58 postpones T2 and can be left in the basket, and fall delay signal 66 has an in check decline border to postpone T2 between the decline border of the decline border of input signal 50 and fall delay signal 66.

This circuit is particularly suitable for input buffering and memory or the adjustment of other digital controlled signal (conditioning).Particularly being used in the control signal of DDR DARM device, can be that the best of circuit of the present invention is implemented situation.Drawing controller or other DRAM device such as EDO or SDRAM also can and be benefited via this input adjustment.

See also Fig. 3, this is a preferred embodiment of delay element of the present invention.Circuit 30 among Fig. 3, expression is used for realizing delay element 34 and the preferable occupation mode of 38 inverter group among Fig. 2.Among Fig. 3 other element of circuit with Fig. 2 be the same.Circuit 30, the first delay elements of please consulting again among Fig. 3 34 are made of an inverter group, include six inverters here, are expressed as I1 71 to I6 76.Second delay element 38 is made of another inverter group, includes six inverters here, is expressed as I7 77 to I12 82.The inverter group that this preferred embodiment discloses is to use six inverters, and certainly, the inverter group of other any numeral can be implemented too.Main notion is to provide two in fact enough long individual delays at input signal 50 and output 58 of DR 54, DF.

Perhaps, the delay element idea that is made of an inverter group can extend in many aspects.See also Fig. 4, first delay element 34 and second delay element 38 can use uneven transistor ratio in an inverter group, to specify its length of delay.If the manufacturing of integrated circuit (IC) apparatus is to adopt the CMOS processing procedure, then each I1 includes a pair of transistor to the inverter of I12, is meant a nmos pass transistor and a PMOS transistor especially.Because in NMOS and the different mobility of PMOS device volume material, the PMOS transistor is bigger than the volume of nmos pass transistor usually.For instance, if ratio is transferred to 2: 1, then the nmos pass transistor of 3 microns of width, 1 micron of length will require the PMOS transistor of 6 microns of width, 1 micron of length, to reach the balance conversion.Under 2: 1 the ratio, inverter will be changed symmetrically on paper, and obtain identical delay in the transfer process that rises and descend.

In this embodiment, to include uneven transistor right for latter two inverter I5 75 of first delay element and I6 76.The NMOS W/L of inverter I5 75 is approximately 1: 20 than PMOS W/L ratio.The NMOS W/L of inverter I6 76 is approximately 20: 1 than PMOS W/L ratio.The inverter I5 75 of linkage disequilibrium and I6 76 roughly can slow down the rising boundary transition of DR 54.In this method, first postpones 34 can specify a slow especially rising boundary transition.In like manner, latter two inverter I11 81 and the I12 82 of second delay element can comprise a special ratios, in order to slow down the decline boundary transition.

See also Fig. 5, Fig. 5 represents to increase the second method that delay element postpones.In this method, additionally at six inverter I91 in the I96 delay element, increase by two inverter I7 116 and I8 120.This idea can extend to increase any number inverter in existing inverter group, postpone or second delay path needed time of delay to specify first.See also Fig. 6, Fig. 6 represents to increase the third method that delay element postpones.In this embodiment, capacitor C1 104 to C3 112 is added in the node of inverter string.This capacitor is added to parasitic capacitance.This additional capacitors load delay inverter conversion, and increase the path that is deferred to from input signal 50 to signal output signal output 100.

See also Fig. 7 and Fig. 8.This is an a kind of preferred embodiment in conjunction with rising delay signal 240 and fall delay signal 244 to one common delay output signal devices of the present invention.Present embodiment is an extension of new concept of the present invention, and an extra benefit is provided.This circuit 200 at first includes the element of Fig. 2 preferred embodiment, particularly uses one first delay element 210, and one second delay element 214.Each delay element refers to be connected to a common input signal: input signal 220.Secondly, use a logical AND function 232.An input of logical AND function 232 is connected to input signal 220, and another input is connected to the output DR 224 of first delay element 210.The output of logical AND function 232 is made up of a rising delay signal 240, has a controlled rising border to postpone T1 between the rising border of the rising border of input signal 220 and rising delay signal 240.At last, use a logic OR 236.236 1 inputs of logic OR are connected to input signal 220, and another input is connected to the output DF 228 of second delay element.The output of logic OR 236 includes a decline inhibit signal 244, has an in check decline border to postpone T2 between the decline border of the decline border of input signal 220 and fall delay signal 244.

The most important thing is that a kind of device in conjunction with rising delay signal 240 and fall delay signal 244 is added into circuit 200.This coupling apparatus by a latch 252 form particularly a kind of S-R latch (latch) 252 in conjunction with inverter I1 248.This specific embodiment of the present invention has showed the new concept of an extension: use two

delay elements

210 and 214 and gate 232 and 236.Rising delay signal 240 and fall delay signal 244 can be according to being combined into an output signal 256 preferable time of delay.Especially, the setting of S-R latch 252 (Set) end is connected to rising delay signal 240, and the replacement of S-R latch 252 (Reset) end is connected to fall delay signal 244 via inverter I1 248.S-R latch 252 output output signals 256.For being familiar with this skill personage, there are many technology to reach in conjunction with inhibit signal.Using the S-R flip-flop is a kind of example of binding signal.

See also Fig. 8, sequential chart as shown in Figure 7.The arrangement of time of input signal 200, first delay element output DR 224, rising delay signal, second delay element output DF 288 and fall delay signal 244 is just with shown in Figure 2 the same.Yet, more sequential charts of output signal signal 256.Because unique configuration, circuit 200 guarantees that rising delay signal 240 and fall delay signal 244 possible bonding states have " 00 ", " 01 " to reach " 11 " three kinds." 10 " state is impossible.Because fall delay signal 244 uses inverter I1 248, so possible S-R state has " 01 ", " 00 " to reach " 10 ", and the S-R latch will guarantee that output signal signal 256 has the rising border to postpone T1 and the decline border postpones T2, as shown in the figure.

Advantage of the present invention is done a summary.The present invention realizes efficient and can make an in a large number circuit, and this circuit can independently be controlled the rising and the arrangement of time of fall delay border of a signal.This circuit uses individual delay element to postpone to set up rising border and decline border.Rising and fall delay can reach the purpose of control via different inverter group.The delay of inverter group can be by increasing inverter, increase capacitor and using uneven transistor size to specify.At last, realize a kind of device in conjunction with rising delay signal and the common delay output signal of fall delay signal to.

Shown in specific embodiment.The novel circuit that can independently control signal rising and fall delay border provides a kind of efficient new selection.

The above only is a preferred embodiment of the present invention, is not to be used for limiting practical range of the present invention, and is all according to equalization variation and modification that the present invention did, is all the contained lid of claim of the present invention.

The figure number explanation:

10-IC device 14-input signal

18-wayside signaling 22 26-phase inverters

30-circuit 34-first delay element

The 38-second delay element 42-logical AND function

46-logic OR 50-input signal

54-first delay element output DR 58-second delay element output DF

62-rising delay signal 66-fall delay signal

71-82-inverter 91-100-inverter

116 120-inverters, 104 108 112-capacitors

200-circuit 210-first delay element

The 214-second delay element 220-input signal

The output DF of output DR 228-second delay element of 224-first delay element

232-logical AND function 236-logic OR

240-rising delay signal 244-fall delay signal

248-inverter 252-latch

The 256-output signal

Claims

1, a kind of delay circuit can independently be controlled a signal and rise and the arrangement of time of fall delay border, and this circuit includes:

One first delay element and one second delay element, each delay element all have input and output, and wherein the input of this each delay element is connected to an input signal.

One logical AND function has two input and outputs, and wherein an input is connected to this input signal, and another input is connected to the output of this first delay element; The output of this logical AND function is made up of a rising delay signal, has a controlled rising border to postpone between the rising border of the rising border of this input signal and this rising delay signal;

And a logic OR, two input and outputs are arranged, wherein an input is connected to this input signal, and another input is connected to the output of this second delay element; The output of this logic OR is made up of a decline inhibit signal, has a controlled decline border to postpone between the decline border of the decline border of input signal and this fall delay signal;

It is characterized in that wherein this first and second delay element is made up of an inverter group respectively, and at least one inverter in described inverter group uses uneven transistor right.

2, delay circuit as claimed in claim 1 is characterized in that: wherein this input signal comprises a control signal in order to the control figure circuit arrangement.

3, delay circuit as claimed in claim 1 is characterized in that: wherein at least one node in the connected node of each inverter is connected with capacity load in this inverter group.

4, delay circuit as claimed in claim 1 is characterized in that: wherein this in check rising and decline border postpone to have different delay numerical value, postpone the inverter quantity of numerical value decision in each this inverter group according to this.

5, delay circuit as claimed in claim 1 is characterized in that: wherein this in check rising and decline border postpone to have different delay numerical value, postpone the unbalance factor of the PMOS of the inverter of numerical value decision in this inverter group to NMOS according to this.

6, delay circuit as claimed in claim 1 is characterized in that: this circuit also comprise a kind of in conjunction with this rising delay and this fall delay signal to generate the device of a common delay output signal.

7, delay circuit as claimed in claim 6 is characterized in that: described is a latch in conjunction with this rising delay and this fall delay signal with the device that generates a common delay output signal, and it has the end of setting, reset end and three links of output; Wherein this rising delay signal is connected to this setting end, and the fall delay signal is connected to this replacement end, and delay output signal is connected to this output.

8, a kind of independent control one signal rises and fall delay border time method, and this method includes:

Produce one first inhibit signal according to an input signal;

Produce one second inhibit signal according to this input signal; Wherein this first inhibit signal and this second inhibit signal are to be produced by different inverter group;

Produce a logical AND signal according to this input signal and this first inhibit signal, wherein this logical AND signal is made up of a rising delay signal, has a controlled rising border to postpone between the rising border of this input signal and the rising border of this rising delay signal;

And produce a logic OR signal according to this input signal and this second inhibit signal, wherein this logic OR signal more includes a decline inhibit signal, has a controlled decline border to postpone between the decline border of this input signal and the decline border of fall delay signal; It is characterized in that at least one inverter in the described inverter group uses uneven transistor to constituting.

9, independent control one signal as claimed in claim 8 rises and fall delay border time method, and it is characterized in that: wherein this input signal comprises a control signal in order to the control figure circuit arrangement.

10, independent control one signal as claimed in claim 8 rises and fall delay border time method, it is characterized in that: wherein in this inverter group in the connected node of each inverter at least one node be connected to capacity load.

11, independent control one signal as claimed in claim 8 rises and fall delay border time method, it is characterized in that: wherein this in check rising and decline border postpone to have different delay numerical value, postpone the inverter quantity of numerical value decision in each this inverter group according to this.

12, independent control one signal as claimed in claim 8 rises and fall delay border time method, it is characterized in that: wherein this in check rising and decline border postpone to have different delay numerical value, postpone the unbalance factor of the PMOS of the inverter of numerical value decision in this inverter group to NMOS according to this.