CN100438500C - Transmission method for fixed-length data packet - Google Patents

Abstract

The present invention provides a method for transmitting a data packet with fixed length. The method comprises: A, correctness judgment is carried out in the process of inputting data of a data packet with fixed length; corresponding marking bits are set according to judgment results, and the data packet with fixed length and marking bits is written in a first-level cache; B, the data packet with fixed length in the first-level cache is read out, and judgement is formed according to corresponding marking bits; the data packet with fixed length is then written in a second-level cache or is directly discarded. A data packet with fixed length and marking bits thereof are processed by the same cache by transmiting the data packet with fixed length by the method provided by the present invention. The present invention effectively avoids transmission errors of data packets due to the uncorrespondence of data packets and marking bits. Meanwhile, the present invention adopts the same cache for processing, and simplifies the process of discarding erroneous data packets by a data packet with fixed length and the internal logic for processing data.

Description

A kind of transmission method of fixed-length data bag

Technical field

The present invention relates to a kind of data transmission method, be specifically related to a kind of transmission method of fixed-length data bag.

Background technology

In data communication field, between router and the router, and the transmission of data in the plate between this body of router, it is unavoidable to make a mistake in transmission course, whether each device within each equipment, the equipment between the veneer, in the plate all can detect in the data transmission procedure according to the data verification method in the transmission course makes mistakes, if detecting this packet makes mistakes, usually need abandon known mistake bag, with this wrong bag termination, in order to avoid continue to transmit back one-level device or equipment are impacted.So abandoning erroneous packets in the transmission course just becomes application-specific integrated circuit ASIC (Application Special Integrated Circuit)/on-site programmable gate array FPGA (Field Programmable Gate Array) and must carry out an important component part of data processing.

In the prior art, the transmission method of packet mainly may further comprise the steps: after 1) receiving packet, these data are carried out buffer memory; 2) in the process of buffer memory, the correctness of packet is judged, judge whether this bag is wrong; 3) be surrounded by mistake if find this, produce bag error flag position, if bag is correct, produce bag accurate indication position, will wrap error flag position and accurate indication position simultaneously and be cached in the flag bit buffer queue, each flag bit is a bag in the corresponding data buffer memory all; 4) in the time of read data packet, remove to read the flag bit of this bag in the flag bit buffer memory of arriving, if be correct, then this bag is sent out, if for wrong, then reading this bag from buffer memory, this bag abandons.Fig. 1 shows the processing block diagram of data pack transmission method in the prior art.

There is following defective in the transmission method of packet in the prior art: that is exactly that data pack buffer and bag correct and wrong sign buffer memory must be corresponding one by one, if correspondence does not once take place, mistake has taken place, so all bags are not corresponding with its flag bit, after mistake has taken place, can recover never, and self can not detect.This situation exists too for the fixed-length data bag.

Summary of the invention

In view of this, main purpose of the present invention is to provide a kind of transmission method of fixed-length data bag, is used to solve fixed-length data bag transmission course flag bit and the not corresponding data transmission fault problem that causes of packet.

For achieving the above object, the invention provides following technical scheme:

A kind of transmission method of fixed-length data bag wherein, is expanded one with the data bit width of described fixed-length data bag, is used to deposit the flag bit of fixed-length data bag, and described method is further comprising the steps of:

A, in the data input process of fixed-length data bag, carry out correctness and judge,, corresponding marker bit is set, and the fixed-length data bag that will be provided with flag bit writes level cache according to judged result;

B, the fixed-length data bag in the level cache is read, and judged, then correct fixed-length data bag is write L2 cache or the fixed-length data bag of mistake is directly abandoned according to corresponding marker bit;

C, the fixed-length data bag in the L2 cache is begun to read in order from packet header.

Described flag bit is arranged on the bag tail of fixed-length data bag.

Described flag bit comprises accurate indication position and error flag position.

Described step B further comprises:

B1, with the fixed-length data bag in the level cache from the bag tail to the packet header reading of data;

B2, judge, as be then execution in step B3 of accurate indication position according to corresponding marker bit, otherwise, directly abandon;

B3, with the fixed-length data bag from the bag tail to packet header write L2 cache.

Utilize method transmission fixed-length data bag provided by the invention, fixed-length data bag and its flag bit are adopted same caching process, avoided the not corresponding data packet transmission mistake of bringing of packet and flag bit effectively, simultaneously, adopt same caching process to simplify the internal logic that the fixed-length data bag abandons the flow process and the data processing of misdata bag.

Description of drawings

Fig. 1 is the processing block diagram of data pack transmission method in the prior art;

Fig. 2 is fixed-length data bag of the present invention and its flag bit storage mode schematic diagram;

Fig. 3 is fixed-length data bag transfer process figure of the present invention.

Embodiment

The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.

Because the fixed-length data bag is packet header and the bag tail that can accurately locate a packet, so metadata cache can be divided into different zones according to the size of packet.

Do not make a mistake when judging in order to solve the flag bit packet corresponding with it, cause irrecoverable error, one of the data bit width expansion of fixed-length data bag can be used for preserving flag bit, store together with the fixed-length data bag, concrete storage mode as shown in Figure 2.

As shown in Figure 2: one of data-bus width expansion is used for depositing flag bit, each fixed-length data bag and its flag bit all are one to one like this, even there is the processing of a fixed-length data bag to make a mistake, also can not influence the processing of next fixed-length data bag.

For data packet transmission, have only and to judge after the bag tail of a packet is received whether this packet is correct, so for the flag bit of fixed-length data bag, only the flag bit corresponding to this fixed-length data bag bag tail just has practical meaning.How to read the fixed-length data bag and the fixed-length data bag of mistake just abandoned and become a difficult problem.If read from the packet header of fixed-length data bag, packet leading portion content has sent out, if the back segment content has been found mistake, this packet just can not abandon.So the present invention reads earlier from the bag tail of fixed-length data bag, and judges its flag bit, if be the accurate indication position, then this fixed-length data bag is sent out, if be the error flag position, then directly abandon.Export by normal order in order to guarantee correct fixed-length data bag data, then when reading, reads the upper level buffer memory when this correct fixed-length data bag from bag tail to packet header, when writing the next stage buffer memory, the data content of reading is earlier begun to write from afterbody, and when the fixed-length data bag data in the next stage buffer memory are exported, read in order from packet header, so just can guarantee that the data of fixed-length data bag are exported in the normal order.

Be illustrated in figure 3 as the transmission method flow chart of fixed-length data bag of the present invention, concrete steps are as follows:

Step 1: the input of fixed-length data bag data, and judge whether it is correct.In the transmission course of packet, whether each device within each equipment, the equipment between the veneer, in the plate all can detect in the data transmission procedure according to the data verification method in the transmission course makes mistakes.

Step 2: according to judged result, corresponding marker bit is set, and the fixed-length data bag is write level cache.The data bit width of each fixed-length data bag is all expanded a flag bit that is used to deposit this fixed-length data bag, therefore, can for each fixed-length data bag corresponding accurate indication position or error flag position be set according to the judged result in the step 1.In data transmission procedure, have only and could judge after the bag tail of a packet is received whether it is correct, therefore,, flag bit is arranged on the bag tail of fixed-length data bag for fixed-length data Bao Eryan.Simultaneously, the fixed-length data bag that is provided with corresponding flag bit is write level cache.

Step 3: the fixed-length data bag in the level cache is read from bag tail to packet header, and judged whether its flag bit is correct.Owing in the data transmission procedure, have only and to confirm after whole the receiving of a packet whether this bag makes mistakes, therefore,, can wrap tail from it and begin to read for the fixed-length data Bao Eryan that is provided with corresponding flag bit.When the flag bit of reading is the error flag position, then the fixed-length data bag of mistake directly can be abandoned; When the flag bit of reading is the accurate indication position, then it is write L2 cache.When writing L2 cache, the correct fixed-length data bag that will from level cache, read from the bag tail to packet header write L2 cache.The fixed-length data bag read from bag tail to packet header can solve after a part sends out before the packet, a back part is found the problem that can't abandon when wrong.Simultaneously, when writing L2 cache, the fixed-length data bag is write the fixed-length data bag data that can guarantee the L2 cache from bag tail to packet header and be normal order.

Step 4: the fixed-length data bag data in the L2 cache are begun output from packet header.Because that is deposited in the L2 cache is correct fixed-length data bag, and order is normal sequence, therefore, the fixed-length data bag data in the L2 cache are begun from packet header to export can guarantee that correct fixed-length data bag data export in the normal order.

The above only is process of the present invention and method embodiment, in order to restriction the present invention, all any modifications of being made within the spirit and principles in the present invention, is not equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (4)

1, a kind of fixed-length data package transmission method is characterized in that, the data bit width of described fixed-length data bag is expanded one, is used to deposit the flag bit of fixed-length data bag, and described method is further comprising the steps of:

A, in the data input process of fixed-length data bag, carry out correctness and judge,, corresponding marker bit is set, and the fixed-length data bag that will be provided with flag bit writes level cache according to judged result;

B, the fixed-length data bag in the level cache is read, and judged, then correct fixed-length data bag is write L2 cache or the fixed-length data bag of mistake is directly abandoned according to corresponding marker bit;

C, the fixed-length data bag in the L2 cache is begun to read in order from packet header.

2, method according to claim 1 is characterized in that, described flag bit is arranged on the bag tail of fixed-length data bag.

3, method according to claim 2 is characterized in that, described flag bit comprises accurate indication position and error flag position.

4, method according to claim 3 is characterized in that, described step B further comprises:

B1, with the fixed-length data bag in the level cache from the bag tail to the packet header reading of data;

B2, judge, as be then execution in step B3 of accurate indication position according to corresponding marker bit, otherwise, directly abandon;

B3, with the fixed-length data bag from the bag tail to packet header write L2 cache.

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