CN100437936C - Method for making wear-resistant dielectric layer - Google Patents
Method for making wear-resistant dielectric layer Download PDFInfo
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- CN100437936C CN100437936C CNB2005100521279A CN200510052127A CN100437936C CN 100437936 C CN100437936 C CN 100437936C CN B2005100521279 A CNB2005100521279 A CN B2005100521279A CN 200510052127 A CN200510052127 A CN 200510052127A CN 100437936 C CN100437936 C CN 100437936C
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- layer
- dielectric layer
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- silicon nitride
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- 238000000034 method Methods 0.000 title claims description 63
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005516 engineering process Methods 0.000 claims abstract description 21
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 37
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 21
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 238000004381 surface treatment Methods 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000007598 dipping method Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims 3
- 238000007747 plating Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 98
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 13
- 239000000463 material Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 230000010148 water-pollination Effects 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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Abstract
In the present invention, firstly, a substrate which comprises a plurality of connecting pads is provided; then, plasma auxiliary chemical vapor deposition technology is at least implemented in a high frequency-low frequency plasma interlace mode so that a dielectric layer is deposited on the surface of the substrate; finally, aeolotropism etching technology is implemented so that a plurality of openings corresponding to the connecting pads are formed in the dielectric layer, and the side walls of each opening are outwards inclined.
Description
Technical field
The present invention relates to a kind of method of making dielectric layer, particularly relate to a kind of high frequency-low frequency plasma interlace mode that utilizes and carry out plasma enhanced chemical vapor deposition technology, to make the method for wear-resistant dielectric layer.
Background technology
In the making of semiconductor element and microcomputer electric component; dielectric layer is mainly in order to provide functions such as insulation and protection; therefore along with the purposes difference, the selection of dielectric layer must be considered size, structural strength and the dielectric layer of dielectric constant itself and the stress problem of other material etc.The material of general Chang Zuowei dielectric layer mainly comprises silica and silicon nitride etc.; wherein silica is because dielectric constant is higher; and the stress between silica and semi-conducting material-(for example silicon base) is less; therefore be commonly used for the material of the gate dielectric of emphasizing dielectric property; and on the other hand; silicon nitride is used the usefulness as the protective layer of semiconductor element and microcomputer electric component always because material structure own is fine and close, and is therefore also higher for resistance to wear and hydrophilic requirement.
Yet because the stress of silicon nitride and semi-conducting material is higher, therefore utilize the thickness of the silicon nitride layer of depositing operation making to have certain restriction, otherwise very easily produce be full of cracks (crack) or peel off problems such as (peeling).Generally speaking, the thickness of silicon nitride layer is in case greater than more than several microns, and its stress promptly is higher than 1000MPa, and the thickness of therefore general silicon nitride layer all is lower than 1 micron.
Because the heavily stressed problem of silicon nitride layer is the problem of demanding urgently overcoming in the silicon nitride deposition process, Given this, the applicant is according to the experience of semiconductor technology for many years, plan provides a kind of manufacture method of wear-resistant dielectric layer, with the stress of effective reduction dielectric layer, and increase the resistance to wear and the hydrophily of dielectric layer simultaneously.
Summary of the invention
Therefore, main purpose of the present invention is providing a kind of method of making wear-resistant dielectric layer, to overcome the insurmountable difficult problem of prior art.
According to claim of the present invention, the manufacture method for a kind of wear-resistant dielectric layer comprises the following steps.One substrate at first is provided, and this substrate comprises a plurality of elements, and a plurality of connection gasket is arranged at the surface of this substrate and is electrically connected with these elements.Then carry out a plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition at least, PECVD) technology, with in surface deposition one dielectric layer of this substrate, and this plasma strengthens chemical vapor deposition method and utilizes one high frequency-low frequency plasma interlace mode to carry out.At last form a mask pattern in the surface of this dielectric layer, and carry out an anisotropic etching process, to form a plurality of openings corresponding to these connection gaskets in this dielectric layer, these openings expose these connection gaskets, and the sidewall of each opening is outward-dipping shape.
Because the present invention utilizes high frequency-low frequency plasma interlace mode to carry out plasma enhanced chemical vapor deposition technology, therefore deposit the dielectric layer of high rigidity and low stress.Further in dielectric layer, form opening simultaneously with outward-dipping sidewall, use the step coverage that promotes follow-up diffusion barrier layer and crystal seed layer, and then produce well-formed's solder projection, so can effectively promote the rate of finished products and the reliability of follow-up packaging technology.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
Fig. 1 to Fig. 8 is the schematic diagram of the manufacture method of a preferred embodiment wear-resistant dielectric layer of the present invention.
The simple symbol explanation
10 substrates, 12 elements
14 connection gaskets, 16 connectors
18 surface dielectric layer, 20 first silicon oxide layers
22 silicon nitride layers, 24 second silicon oxide layers
26 mask patterns, 28 openings
30 projection bottom metal layers, 32 diffusion barrier layers
34 crystal seed layers, 36 mask patterns
38 solder projections
Embodiment
Please refer to Fig. 1 to Fig. 8.Fig. 1 to Fig. 8 is the schematic diagram of the manufacture method of a preferred embodiment wear-resistant dielectric layer of the present invention.As shown in Figure 1, at first provide a substrate 10, and substrate 10 comprises a plurality of elements 12, and a plurality of connection gasket 14 is arranged at the surface of substrate 10, and utilizes a connector 16 to be electrically connected with element 12 respectively, wherein element 12 is semiconductor element or microcomputer electric component etc.In addition, the surface of substrate 10 also comprises a surface dielectric layer 18.Then surface dielectric layer 18 is carried out a process of surface treatment,, increase the adhesive force between the dielectric layer (scheming not show) of surface dielectric layer 18 and follow-up formation simultaneously to remove the organic pollution that adheres on the surface dielectric layer 18 and particulate etc.In present embodiment, process of surface treatment comprises the following steps:
(1) carries out a cleaning, tentatively remove organic pollution and particulate on the surface dielectric layer 18;
(2) carry out a plasma and clean (plasma cleaning) technology, further remove organic pollution;
(3) carry out a plasma etching (plasma etching) technology, increase the surface cleanliness and the surface roughness of surface dielectric layer 18; And
(4) carry out a plasma surface treatment (plasma surface treatment) technology, promote the activity of surface dielectric layer 18, to increase the tack of subsequent dielectric layer.
As shown in Figure 2, carry out a depositing operation, form one first silicon oxide layer 20 with the surface in surface dielectric layer 18 and connection gasket 14, wherein first silicon oxide layer 20 is a stress-buffer layer.As shown in Figure 3, then carry out a plasma enhanced chemical vapor deposition (plasma enhanced chemical vapordeposition, PECVD) technology, with in surface deposition one silicon nitride layer 22 of first silicon oxide layer 20, wherein plasma enhanced chemical vapor deposition technology utilization one high frequency-low frequency plasma interlace mode carries out, and in present embodiment, the frequency of the high-frequency plasma of plasma enhanced chemical vapor deposition technology is 13.56MHz, and the frequency of low frequency plasma is then between 150 to 400KHz.Because hydrogen content is less, under thickness reached situation more than 2 to 3 microns, its stress still can be maintained under the 100MPa by the formed silicon nitride layer of high frequency-low frequency plasma interlace mode 22, simultaneously and have a characteristic of high rigidity and abrasion performance.In addition, for increasing hydrophily, can form one second silicon oxide layer 24 again in the surface of silicon nitride layer 22 according to need, wherein second silicon oxide layer 24 can utilize modes such as deposition, coating or immersion to form.
Method of the present invention is in utilizing high frequency-low frequency plasma interlace mode to carry out plasma enhanced chemical vapor deposition technology, on surface dielectric layer 18, to form silicon nitride layer 22, use the hardness that promotes silicon nitride layer 22 and reduce stress, simultaneously in the foregoing description, comprise first silicon oxide layer 20 under the silicon nitride layer 22, and the top of silicon nitride layer 22 also comprises second silicon oxide layer 24, yet method of the present invention does not limit office in this.For instance, surface dielectric layer 18 also can not established in the surface of substrate 10, and first silicon oxide layer 20 is formed directly in the surface of substrate 10, or constitute a single dielectric layer by silicon nitride layer 22, and directly silicon nitride layer 22 is arranged on substrate 10 or the surface dielectric layer 18, and first silicon oxide layer 20 is not set.
Above-mentioned is the preferred embodiment of the manufacture method of wear-resistant dielectric layer of the present invention, and the present invention also further provides the method for follow-up making dielectric layer opening and solder projection.As shown in Figure 4, form a mask pattern 26 in the surface of second silicon oxide layer 24, for example a photoresist pattern.As shown in Figure 5, then carry out an anisotropic etching process, a dry etching process is for example removed second silicon oxide layer 24, silicon nitride layer 22 and first silicon oxide layer 20 of not masked pattern 26, exposes connection gasket 14 to form a plurality of openings 28, to use.Thickness that it should be noted that mask pattern 26 depends on the thickness of first silicon oxide layer 20, silicon nitride layer 22 and second silicon oxide layer 24, to avoid causing the problem of over etching or undercut.In addition, see through control of process parameters, the for example flow of etching gas and composition, and the isoparametric control of voltage, the sidewall of opening 28 is export-oriented skewed, to promote the step coverage of subsequent thin film, simultaneously in present embodiment, the sidewall slope angle between 60 the degree to 90 the degree, and with between 60 the degree to 80 the degree serve as preferred.
As shown in Figure 5, then remove mask pattern (figure do not show), and further carry out a surface activation technology, an oxygen gas plasma treatment process for example is to improve the hydrophily on second silicon oxide layer, 24 surfaces.As shown in Figure 6, on the sidewall of second silicon oxide layer 24, opening 28 and connection gasket 14, form a projection bottom metal layer (under bump metallurgy layer, UBM layer) 30, wherein projection bottom metal layer 30 comprises a diffusion barrier layer (diffusion barrier layer) 32 and one crystal seed layer (seedlayer) 34.In present embodiment, diffusion barrier layer 32 utilizes the sputter mode to form with crystal seed layer 34, but is not limited thereto.In addition, diffusion barrier layer 32 can be a single layer structure or pair of lamina structure, and the visual barriering effect of its material is selected tungsten (W), tungsten titanium (TiW), tantalum/tantalum nitride (Ta/TaN) and titanium/titanium nitride materials such as (Ti/TiN) for use.Form a mask pattern 36, for example a photoresist pattern subsequently in surface in crystal seed layer 34.Wherein mask pattern 36 exposes opening 28 and opening 28 marginal positions, uses to define the solder projection position of (figure does not show).
As shown in Figure 7, then utilize coating technique, for example carry out an electroplating technology or an electroless plating, the surface of the crystal seed layer 34 that covers in not masked pattern 36 becomes to grow a plurality of solder projections 38.As shown in Figure 8, remove mask pattern 36 at last, and remove the crystal seed layer 34 and diffusion barrier layer 32 that is not covered by solder projection 38.
From the above, the present invention utilizes high frequency-low frequency plasma interlace mode to carry out plasma enhanced chemical vapor deposition technology, can deposit the silicon nitride layer of high rigidity and low stress, further form opening simultaneously with outward-dipping sidewall in silicon nitride layer, use the step coverage that promotes follow-up diffusion barrier layer and crystal seed layer, and then produce well-formed's solder projection, so can effectively promote the rate of finished products and the reliability of follow-up packaging technology.
Compared to prior art, the present invention has following advantage:
(1) utilizes high frequency-low frequency plasma interlace mode to carry out plasma enhanced chemical vapor deposition technology, can effectively reduce the hydrogen content of silicon nitride layer, increase resistance to wear by this and reduce stress.
(2) opening of dielectric layer has the opening of outward-dipping sidewall, so follow-up diffusion barrier layer and crystal seed layer have the excellent step spreadability.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (23)
1. the manufacture method of a wear-resistant dielectric layer comprises:
One substrate is provided, and this substrate comprises:
A plurality of elements are arranged in this substrate;
A plurality of connection gaskets are arranged at the surface of this substrate and are electrically connected with these elements; And;
One surface dielectric layer is located at the surface of this substrate and is exposed these connection gaskets;
Carry out a process of surface treatment, and this process of surface treatment comprises a plasma etch process at least;
At least carry out a plasma and strengthen chemical vapor deposition method, with in surface deposition one dielectric layer of this surface dielectric layer, and this plasma strengthens chemical vapor deposition method and utilizes one high frequency-low frequency plasma interlace mode to carry out; And
Form a mask pattern in the surface of this dielectric layer, and carry out an anisotropic etching process, to form a plurality of openings corresponding to these connection gaskets in this dielectric layer, these openings expose these connection gaskets, and the sidewall of each opening is outward-dipping shape.
2. the method for claim 1, wherein this process of surface treatment carries out a cleaning and a plasma cleaning before also being included in this plasma etch process in regular turn.
3. the method for claim 1, wherein this process of surface treatment carries out a plasma process of surface treatment after also being included in this plasma etch process.
4. the method for claim 1, wherein this dielectric layer is a silicon nitride layer.
5. the method for claim 1, wherein this dielectric layer is a composite dielectric layer.
6. method as claimed in claim 5, wherein this composite dielectric layer comprises a silicon nitride layer and one silica layer, and this silicon nitride layer strengthens chemical vapor deposition method and utilizes this high frequency-low frequency plasma interlace mode to form by this plasma.
7. method as claimed in claim 5, wherein this composite dielectric layer comprises one first silicon oxide layer, a silicon nitride layer and one second silicon oxide layer from the bottom to top in regular turn, and this silicon nitride layer strengthens chemical vapor deposition method and utilizes this high frequency-low frequency plasma interlace mode to form by this plasma.
8. the method for claim 1, wherein respectively the angle of inclination of the sidewall of this opening between 60 to 90 degree.
9. the method for claim 1 also is included in and this dielectric layer is carried out a surface activation technology after forming these openings.
10. the method for claim 1 also is included in and forms the step of making a plurality of solder projections behind these openings.
11. method as claimed in claim 10, the step of wherein making these solder projections comprises:
Form a projection bottom metal layer in this dielectric layer surface;
Form a mask pattern in the surface of this projection bottom metal layer, this mask pattern exposes these openings;
Utilize plating mode to grow these solder projections; And
Remove this mask pattern and this projection bottom metal layer that is not covered by these solder projections.
12. method as claimed in claim 11, wherein this projection bottom metal layer comprises a diffusion barrier layer and a crystal seed layer.
13. the manufacture method of a wear-resistant dielectric layer comprises:
One substrate is provided;
Carry out a process of surface treatment; And
Carry out a plasma and strengthen chemical vapor deposition method, with in surface deposition one silicon nitride layer of this substrate, and this plasma strengthens chemical vapor deposition method and utilizes one high frequency-low frequency plasma interlace mode to carry out.
14. method as claimed in claim 13, wherein the surface of this substrate also comprises a surface dielectric layer.
15. method as claimed in claim 13, wherein this process of surface treatment comprises the following steps:
Carry out a cleaning;
Carry out a plasma cleaning;
Carry out a plasma etch process; And
Carry out a plasma process of surface treatment.
16. method as claimed in claim 13 comprises that also this silicon nitride layer of deposition forms one first silicon oxide layer prior to the surface of this substrate before.
17. method as claimed in claim 13, also be included in the deposition this silicon nitride layer after, form one second silicon oxide layer in the surface of this silicon nitride layer.
18. method as claimed in claim 13, wherein this substrate also comprises a plurality of elements, and a plurality of connection gasket is arranged at the surface of this substrate and is electrically connected with these elements.
19. method as claimed in claim 18, also be included in form this silicon nitride layer after, in silicon nitride layer, form the step of a plurality of openings corresponding to these connection gaskets.
20. method as claimed in claim 19 also is included in and carries out a surface activation technology after forming these openings.
21. method as claimed in claim 19, the step that wherein forms these openings comprises:
Form a mask pattern in the surface of this silicon nitride layer, this mask pattern exposes this silicon nitride layer that corresponds to these connection gaskets; And
Carry out an anisotropic etching process, remove not this silicon nitride layer of being protected by this mask pattern forming these openings, exposing these connection gaskets, and the sidewall of each opening is outward-dipping shape.
22. method as claimed in claim 19, wherein respectively the angle of inclination of the sidewall of this opening is spent between 60 to 90.
23. method as claimed in claim 19 also is included in and forms the step of making a plurality of solder projections behind these openings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100521279A CN100437936C (en) | 2005-02-25 | 2005-02-25 | Method for making wear-resistant dielectric layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100521279A CN100437936C (en) | 2005-02-25 | 2005-02-25 | Method for making wear-resistant dielectric layer |
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| CN1825545A CN1825545A (en) | 2006-08-30 |
| CN100437936C true CN100437936C (en) | 2008-11-26 |
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| CNB2005100521279A Expired - Fee Related CN100437936C (en) | 2005-02-25 | 2005-02-25 | Method for making wear-resistant dielectric layer |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200826233A (en) | 2006-12-15 | 2008-06-16 | Touch Micro System Tech | Method of fabricating metal interconnects and inter-metal dielectric layer thereof |
| CN108389780B (en) * | 2018-02-26 | 2019-04-30 | 清华大学 | Silicon nitride film and preparation method thereof |
| CN114000123A (en) * | 2021-11-02 | 2022-02-01 | 浙江光特科技有限公司 | Preparation of SiO2Method, chip and device for thin film |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6136388A (en) * | 1997-12-01 | 2000-10-24 | Applied Materials, Inc. | Substrate processing chamber with tunable impedance |
| US20040157450A1 (en) * | 2001-12-21 | 2004-08-12 | Bojkov Christo P. | Waferlevel method for direct bumping on copper pads in integrated circuits |
| US20040235220A1 (en) * | 2003-05-22 | 2004-11-25 | Renesas Technology Corp. | Flip chip mounting method |
| CN1581425A (en) * | 2003-07-30 | 2005-02-16 | 友达光电股份有限公司 | Method for remaking etching suspension layer |
-
2005
- 2005-02-25 CN CNB2005100521279A patent/CN100437936C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6136388A (en) * | 1997-12-01 | 2000-10-24 | Applied Materials, Inc. | Substrate processing chamber with tunable impedance |
| US20040157450A1 (en) * | 2001-12-21 | 2004-08-12 | Bojkov Christo P. | Waferlevel method for direct bumping on copper pads in integrated circuits |
| US20040235220A1 (en) * | 2003-05-22 | 2004-11-25 | Renesas Technology Corp. | Flip chip mounting method |
| CN1581425A (en) * | 2003-07-30 | 2005-02-16 | 友达光电股份有限公司 | Method for remaking etching suspension layer |
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