CN100435013C - Electro-optical device substrate, electro-optical device, electronic device, and projection display device - Google Patents

Electro-optical device substrate, electro-optical device, electronic device, and projection display device Download PDF

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CN100435013C
CN100435013C CNB2006101002211A CN200610100221A CN100435013C CN 100435013 C CN100435013 C CN 100435013C CN B2006101002211 A CNB2006101002211 A CN B2006101002211A CN 200610100221 A CN200610100221 A CN 200610100221A CN 100435013 C CN100435013 C CN 100435013C
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model
pixel
interlayer insulating
insulating film
film
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CN1945412A (en
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平林幸哉
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

In a liquid crystal panel substrate having a layered film structure of interlayer insulation films and metal layers alternately formed on a semiconductor substrate provided with a transistor region for pixel selection thereon, to provide a configuration for achieving a uniform polishing rate without thickening of the interlayer insulation film to be polished. A liquid crystal panel substrate is provided with a shading film 12, a second interlayer insulation film 11, a wiring film 10, a pixel electrode, and a connecting plug 15. A lower dummy pattern A composed of the first metal layer and an upper dummy pattern B composed of the second metal layer are formed on the periphery of input terminal pads 26 in the non-pixel region. Since the surface level of the third interlayer insulation film 13 formed on the dummy patterns A and B is raised, excessive polishing is prevented at the position. As a result, a uniform polishing rate is achieved in CMP treatment.

Description

Electro-optical device substrate, electro-optical device, electron device and projection display apparatus
The application is dividing an application of following application:
Denomination of invention: electro-optical device substrate, electro-optical device, electron device and projection display apparatus
The applying date: on June 16th, 1998
Application number: 200310113109.8
The present invention relates to a kind of substrate that is used for electro-optical device, as the reflective liquid crystal board substrate, particularly relate to a kind of electro-optical device substrate that comprises pixel region, this pixel region is formed on the element region that is used to select pixel.
As described below, the applicant has disclosed the structure of liquid crystal board substrate, liquid crystal board and projection display apparatus in the Japanese patent application No.8-279388 of application on October 22nd, 1966.As shown in figure 17, adopt the reflective liquid crystal plate to comprise: along systematic optical axis L as the projection display apparatus (liquid crystal projector) of light valve 0The light source of placing 110; The polarized light lighting unit 100 that comprises integral lens 120 and polarized light converter 130; Be used for by S polarized light reflecting surface 201, reflection is by the polarized electromagnetic beam beam splitter 200 of the S polarized electromagnetic beam of polarized light lighting unit 100 emissions; Spectroscope 412 is used for isolating blue light components (B) from the light that the S polarized light reflecting surface 201 of polarized beam splitter 200 reflects; Be used to modulate the reflective liquid crystal light valve 300B of the blue light components (B) of separation; Spectroscope 413 is used for isolating red light component (R) by after the spectroscope 412 separation blue lights by reflection from light beam; Be used to modulate the reflective liquid crystal light valve 300R of the red light component (R) of separation; Be used to modulate reflective liquid crystal light valve 300G by the residue green component (G) of spectroscope 413; Comprise the projection optical system 500 that is used for the projecting lens of optical projection to the screen 600 that will be synthetic, wherein be synthesized by spectroscope 413,412 and polarized electromagnetic beam beam splitter 200 in the backhaul pathways of light component at them of in three reflective liquid crystal light valve 300R, 300G and 300B, modulating.As being used as reflective liquid crystal light valve 300R, 300G and 300B with the reflective liquid crystal plate 30 shown in the cut-open view among Figure 18.
Reflective liquid crystal plate 30 comprises that sticking with glue agent is fixed on by the reflective liquid crystal board substrate 31 on glass or the ceramic bearing substrate 32 that constitutes; Glass substrate 35, this substrate have by electrically conducting transparent (ITO) film constitute to electrode (public electrode) 33, be positioned at incident light one side, and relative with reflective liquid crystal board substrate 31 gap arranged, this substrate 31 is sealed by the framework that is made of seal 36; And (SH) liquid crystal 37 of known twisted-nematic (TN) liquid crystal or super homeotropic alignment (superhomeotropic), liquid crystal molecule homeotropic alignment under not alive state therein, liquid crystal is sealed in the space of being sealed by seal 36 between reflective liquid crystal board substrate 31 and the glass substrate 35.
Figure 19 is the layout planimetric map of the amplification of the reflective liquid crystal board substrate 31 of use in the reflective liquid crystal plate 30.Reflective liquid crystal board substrate 31 comprises the rectangular pixels district (viewing area) 20 that has pixel electrode, and this pixel electrode is arranged to matrix 14 as shown in figure 18; Be positioned at the right side of pixel region 20 and the grid line drive circuit of left hand external (Y driver) 22R and 22L, be used to scan grid line (scan electrode or line electrode); Be positioned at the precharge/test circuit 23 of the upside outside of pixel electrode 14, be used for data line (signal electrode or row electrode); Be positioned at the picture intelligence sample circuit 24 of outside, pixel electrode 14 bottom side, be used for providing picture intelligence to data line according to pictorial data; Seal area 27 with frame shape is positioned at the outside of grid line driver 22R and 22L, precharge/test circuit 23 and picture intelligence sample circuit 24, is used to place seal 36; Arrange along the bottom, and a plurality of terminal pads 26 that link to each other with soft band lead 39 (flexible tape wiring) by therebetween anisotropic conductive film (ACF) 38; Data line driver circuit between terminal pads array 26 and seal area 27 (X driver) 21 is used for providing picture intelligence according to pictorial data to data line; Be positioned at trunk connection end pad (so-called silver point (siver point)) 29R and the 29L on next door, data line driver circuit 21 two ends, be used for to electrode 33 is powered on glass substrate 35.
Be positioned at peripheral circuit (the grid line drive circuit 22R and the 22L of seal area 27 inside, precharge/test circuit 23 and picture intelligence sample circuit 24) have a barrier film 25 (with reference to Figure 18), so that shielding incident light, this barrier film 25 is the same with the pixel electrode 14 of top layer.
Figure 20 is the local amplification view of the pixel region 20 of reflective liquid crystal board substrate 31, and Figure 21 is the cut-open view of being done along the A-A ' line among Figure 20.In Figure 21, numeral 1 expression has the monocrystalline silicon P on the limit of 20mm --Semiconductor chip (N --Semiconductor chip also can).The device that numeral 2 is illustrated in semiconductor chip 1 forms the P type well region that the upper surface (first type surface) in the district (MOSFET etc.) upward forms, numeral 3 expression field oxide films (so-called LOCOS), it is that isolating device forms in the district for the negator at semiconductor chip 1 forms.P type well region 2 shown in Figure 21 forms the public well region of pixel region 20, and be used to make peripheral circuit (grid line drive circuit 22R and 22L, precharge/test circuit 23, picture intelligence sample circuit 24 and datawire driver 21) the P type well region 2 ' (with reference to Figure 22) of device keep apart, wherein pixel region 20 for example is provided with the picture element matrix of 768 * 1024 size.
Field oxide film 3 has two openings in the zoning of each pixel.The grid 4a process that is made of polysilicon or metal silicide forms at the gate insulating film 4b of opening central authorities; The N that the both sides of grid 4a form on P type well region 2 + Source region 5a and N +Drain region 5b forms N-channel MOS FET (isolated-gate field effect transistor (IGFET)) with grid 4a, is used for pixel selection.The grid 4a that is arranged in a plurality of pixels on the line extends at scan-line direction (pixel line direction), forms grid line 4.
The P type capacitance electrode district 8 consistent with the line direction forms in another opening on P type well region 2; The capacitance electrode 9a that is made of polysilicon or metal silicide forms the maintenance capacitor C with P type capacitance electrode district 8, be used to keep selected signal by the MOSFET that is used for pixel selection, this capacitance electrode 9a forms in P type capacitance electrode district 8, and dielectric film (deielectric-coating) 9b is arranged between them.
First interlayer insulating film 6 forms on gate electrode 4a and capacitance electrode 9a, and the first metal layer that mainly is made of aluminium forms on dielectric film 6.
The first metal layer comprises the data line 7 (referring to Figure 20) that extends along column direction; Stretch out from data line 7 with comb teeth shape, and conduct electricity the source electrode lead 7a that contacts by contact hole 6a and source region 4b; With contact by contact hole 6b and drain region 5b conduction, and conduct electricity the relaying lead 10 that contacts by contact hole 6c and capacitance electrode 9a.
Second interlayer insulating film 11 forms on the first metal layer that forms data line 7, source electrode line 7a and relaying lead 10, and second metal level that is made of aluminium forms on second interlayer insulating film 11 substantially.Second metal level comprises the barrier film 12 that covers whole pixel region 20.Form lead 12b (with reference to Figure 22) as second metal level of barrier film 12, be used for being connected each device of the peripheral circuit (grid line drive circuit 22R and 22L, precharge/test circuit 23, picture intelligence sample circuit 24 and data line driver circuit 21) that the periphery of pixel region 20 forms.
Jack 12a is arranged on the corresponding position of isolated film 12 and relaying lead 10.The 3rd interlayer insulating film 13 forms on barrier film 12, and forms on interlayer insulating film 13 with the corresponding rectangular pixel electrodes 14 of pixel substantially, as reflecting electrode.Contact hole 16 passes the 3rd and second interlayer insulating film 13 and 11 and forms, thereby is positioned in the opening 12a.Handling with refractory metal for example after the tungsten filling contact hole 16 by CVD, the high melting point metal layer that forms on the 3rd interlayer insulating film 13 and the front of interlayer insulating film 13 (CMP) are handled and are flattened the formation minute surface by chemical-mechanical polishing (chemomechanical polishing).Then, form aluminium lamination, and have the rectangular pixel electrodes 14 of 15 μ m to the limit of 20 μ m by graphical treatment formation by the low temperature sputter process.Relaying lead 10 and pixel electrode 14 are electrically connected by column attachment plug (conductive interlayer part) 15.Passivating film 17 forms on whole pixel electrode 14.
On the other hand, can handle by CMP and make 13 complanations of the 3rd interlayer insulation film, contact hole and embedding refractory metal such as tungsten are set form attachment plug 15.
Handling the complanation that the 3rd interlayer insulating film 13 is carried out by CMP is necessary for the pixel electrode 14 that deposition has minute surface, and this pixel electrode 14 is as the reflecting electrode on each pixel.This processing also is necessary to the formation of the dielectric mirror film on pixel electrode 14, between this pixel electrode 14 and the dielectric mirror film diaphragm is arranged.CMP handle to use a kind of slurry that is made of such composition (polishing liquid), and it can promote in scribing (scribing) simultaneously before to the chemical corrosion and the mechanical buffing of wafer.
Yet in pixel region 20, be used for the MOSFET of pixel selection, the electrode cable 7a and 10 of maintenance capacitor C, and barrier film 12 is formed bottom.Simultaneously, as shown in figure 22, in peripheral circuit region (gate line drive circuit 22R and 22L, precharge/test circuit 23, picture intelligence sample circuit 24 and data line driver circuit 21), electrode cable 7a and lead 12b between device form bottom.In addition, in the zone of terminal pads 26, be formed with lower membrane 26a that constitutes by the first metal layer and the upper layer film 26b that constitutes by second metal level.As a result, after deposition the 3rd interlayer insulating film 13, the surface elevation 13a that represents with dotted line among Figure 22 is in pixel region rising at once, peripheral circuit region and terminal pads district.When handling by CMP, in the time of will having the surface finish of the 3rd interlayer insulating film 13 of this big unevenness, the height 13b that finishes after the polishing of representing with solid line among Figure 22 reflects the original surface elevation 13a that dots.According to the inventor's further investigation, very clear in standing the liquid crystal board substrate 31 of this polishing on pixel region the surface planarization particular importance of the 3rd interlayer insulating film 13.
The patent disclosure No.9-68718 of Japanese unexamined has disclosed the technology that the 3rd interlayer insulating film 13 on the pixel region 20 is carried out complanation of being used for, wherein between the first metal layer such as relaying lead 10 and second metal level (separation layer), be provided for the discrete model figure of the metal level of each pixel, thereby so that make the unevenness on the whole surface of the inhibition barrier film 12 that highly raises.When the formation intermediate metal layer just raises for the height that makes each pixel, add the step of extra deposit interlayer insulating film.During the surperficial unevenness of interlayer insulating film, initial polishing velocity reduces naturally in CMP handles before having reduced polishing, thereby for forming polishing time that the complanation interlayer insulating film 13 carried out the mirror surface need grow and polishing liquids in a large number.Therefore carry out being deposited on of illustraton of model shape on each pixel in pixel region 2O and the shortcoming that causes production cost to increase is arranged aspect the production technology.
Figure 23 is the explanation liquid crystal board substrate 31 polishings film contour curve figure of the thickness distribution of the 3rd interlayer insulating film 13 afterwards, wherein forms to have about 24,000
Figure C20061010022100071
The 3rd interlayer insulating film 13 of thickness, this film 13 stands CMP and handles then, reaches 12,000 up to the residual thickness at the center of pixel region 20 the 3rd interlayer insulating film 13
Figure C20061010022100072
Till.In Figure 24, with the curve of mark * draw the left strip of paper used for sealing of being done along the a-a ' line of Figure 23 is shown and distributes at the residual thickness of vertical direction.In Figure 25, with the curve of mark * draw the center pixel of being done along the b-b ' line of Figure 23 is shown and distributes at the residual thickness of vertical direction.In Figure 26, with the curve of mark * draw the last strip of paper used for sealing of being done along the c-c ' line of Figure 23 is shown and distributes at horizontal residual thickness.In Figure 27, with the curve of mark * draw the center pixel of being done along the d-d ' line of Figure 23 is shown and distributes at horizontal residual thickness.In Figure 28, illustrate along the following strip of paper used for sealing zone that the e-e ' line of Figure 23 is done with the curve of mark * draw and to distribute at horizontal residual thickness.
Shown in Figure 23 to 28, the maximum ga(u)ge difference is about 6,120 in pixel region 2O and the seal area 27
Figure C20061010022100073
Therefore the substrate that comprises pixel region 20 and seal area 27 is done as a wholely fully not flatten.The center, upper and lower of the periphery of terminal pads 26 and seal area 27 is by excessive polishing, and the right part of seal area 27 and the polishing of left part center are not enough.
As shown in figure 22, because the terminal pads 26 of the projection of some shape is arranged in array discretely in the terminal pads district, will be with the lug boss 13c that the 3rd interlayer insulating film 13 covers by very fast polishing.Therefore the initial burnishing speed in the zone of terminal pads 26 is than the height of pixel region 20.Therefore, before pixel region 20 fully flattened, the zone of terminal pads 26 may exceedingly be polished, so that exposed bottom (upper layer film 26b).
The method that is used to compensate the excessive polishing of terminal pads 26 comprises the thick deposit of the 3rd interlayer insulating film 13.According to this method,, therefore compare polishing velocity and significantly reduce with initial burnishing speed even by very fast polishing, also finished in the complanation of this zone the 3rd interlayer insulating film 13 before bottom exposes substantially in the zone of terminal pads 26.As a result, can be by spending more polishing time that pixel region 20 is flattened and not exposing bottom.
The formation of the 3rd thick interlayer insulating film 13 causes that the contact hole degree of depth that is used for attachment plug 15 increases, because high like this aspect ratio makes to be difficult to use the refractory metal landfill contact hole 16 that constitutes attachment plug 15.Because attachment plug 15 is current-carrying parts of crossing interlayer, it passes second interlayer insulating film 11, separation layer 12 and the 3rd interlayer insulating film 13 and forms, and arrives pixel electrode 14, so contact hole 16 has the big degree of depth at first.In addition, for preventing to enter into by opening 12a the leakage of the light of device such as MOSFET and similar device, must reduce opening 12a, thereby the diameter of contact hole 16 to reduce also from the gap between the pixel electrode 14.Contact hole 16 has high aspect ratio inevitably.Therefore need make interlayer insulating film 13 attenuation that to polish.Yet as mentioned above, the 3rd interlayer insulating film 13 in CMP overtreating ground butt joint line end pad 26 zones polishes.
Shown in Figure 26 and 28 and since the thickness at the center, upper and lower of seal area 27 because of the excessive polishing in the zone of terminal pads 26 less than pixel region, the edge, upper and lower of pixel region 20, and the center, upper and lower of seal area 27 is by excessive polishing.Excessive polishing because of the zone of terminal pads 26, four angles in the right side of seal area 27 and left side also will have little thickness, and because the low initial burnishing speed that the flatness of seal area 27 causes before polishing, the right part of seal area 27 and left part center are polished hardly.As a result, the heart is partially polished not enough therein for the right hand edge of the right side of seal area 27 and left side and pixel region 20 and left hand edge.When the surrounding edge of pixel region 20 and seal area 27 have such dip plane, the reflection of the pixel electrode 14 that forms on the 3rd interlayer insulating film 13 after polishing reduces, the gap that in Liquid crystal module, is difficult to regulon, and the tackiness of seal is unsatisfactory.When after CMP handles, being provided for the contact hole 16 of attachment plug 15,, be difficult to optimize the etching time of contact hole because of in uneven thickness.
In view of inharmonic problem about the interlayer insulating film that between barrier film and pixel electrode, forms, and the problem that need in the reflective liquid crystal board substrate, carry out polishing, first purpose of the present invention provides a kind of electro-optical device substrate, as the liquid crystal board substrate, it is included in and is formed in the on-chip pixel region a plurality of interlayer insulating films that alternately form and the tunic structure of a plurality of conductive layers, it is characterized in that the electric light substrate has such structure, it does not need extra depositing step, and interlayer insulating film there is uniform polishing velocity, and does not make the interlayer insulating film thickening.
Second purpose of the present invention provides a kind of electro-optical device substrate, as the liquid crystal board substrate, it has the polished surface of the interlayer insulating film that flattens in seal area and pixel region, and the reflection of the pixel electrode that improves, and it makes it possible to the gap of regulon easily, the tackiness of seal of raising and the etching time of the contact hole optimized are arranged.
For reaching in first purpose the present invention, first method, for the surface elevation that makes unpolished interlayer insulating film as far as possible equably flattens, by using the conductor layer that forms previously, in the whole outside of pixel region, rather than the model figure of the interlayer insulating film height that will polish of on the space of pixel region, being formed for raising.Promptly, the present invention is characterised in that a kind of electro-optical device substrate, be included in the pixel region a plurality of interlayer insulating films that alternately form and the tunic structure of a plurality of conductive layers, on-off element is corresponding with each pixel in this pixel region is arranged on the substrate, and at least one interlayer insulating film flattens by polishing below the top conductive layer in a plurality of conductive layers; Substrate is characterised in that the model figure of single or multiple layers is arranged at least near the terminal pads that on-chip non-pixel region forms, and this layer comprises the conductive layer below the described interlayer insulating film that stands to polish.Terminal pads comprises the trunk connection end pad that is arranged near the input terminal pad of substrate edge and is provided with in the position of substrate inside.
Because near this model graphic structure that terminal pads, is provided with, near the surface elevation of the interlayer insulating film that will polish that forms terminal pads raises, surface elevation is identical with the surface elevation of the interlayer insulating film that will polish in the pixel region basically, makes the surface elevation unanimity like this on whole surface.The surface has uniform polishing velocity in chemically mechanical polishing (CMP) or similar technology uniformly, and does not have near terminal pads and outside polishing rapidly, and the polished surface of interlayer insulating film is more smooth than conventional surface.As a result, pixel region flattens more satisfactorily, and the control of cell gap improves in using the unit block of substrate (counter substrate), and the etching time to the contact hole of conductive interlayer part in the pixel region etc. is determined easily after the polishing.
The surface of this uniform polish has prevented because of the terminal pads layer below terminal pads excessive polishing partly exposes, and can realize the attenuation of unpolished interlayer insulating film.The aspect ratio of partly locating contact hole owing to conductive interlayer in pixel electrode is improved because of attenuation, thereby has realized the opening portion of minor diameter by the contact hole that minor diameter is arranged.As a result, isolation performance improves.
First conductive layer that the conductive interlayer part will link to each other with on-off element and the top conductive layer that forms on the interlayer insulating film that will polish are electrically connected, the model figure can be following any one: the first model figure that constitutes by first conductive layer, the second model figure that constitutes by second conductive layer that forms between first conductive layer and top conductive layer such as the barrier film, and their combination.
In the time of near the electrical conduction model figure is positioned at pixel region external terminal pad, the model figure plays barrier film, so it prevents to enter into on-chip pixel region from the parasitic light of pixel region outside, and the result has suppressed photocurrent and improved on-off element.
Because by using anisotropic conducting film to carry out hot press, the input terminal pad is connected on the outer lead, therefore after the polishing on the model graph area interlayer insulating film of conductive particle infringement attenuation, and will occur and the short circuit of input terminal pad.When forming the model figure when extract the district almost gamut out near the lead the input terminal pad on, two adjacent input terminal pads will cause short circuit by the model figure.
In the present invention, the model figure that is arranged on input terminal pad periphery is made of the model figure of a plurality of separations, thereby makes the height unanimity on the interlayer insulating film surface that will polish of formation, and does not have short circuit between adjacent terminal pads.Along with the increase of the illustraton of model figurate number of separating, the possibility of short circuit descends.
Be preferably between two adjacent input terminal pads non-model graph area is set.Non-model graph area is near the lead of the soft band lead of suppressing in the hot press process.If form the model figure continuously, then the conductive particle in the anisotropic conductive film will increase the possibility of short circuit between terminal pads and the model figure, cause two short circuits (short-cutting) between the terminal pads by the model figure.The formation of non-model figure can prevent this undesirable short circuit reliably.
Thereby between the model figure that prevents input terminal pad and separation as far as possible by the conductive particle bridge joint short circuit in the anisotropic conductive film, the spacing between the model figure of the separation on input terminal pad and its periphery is set to larger than the spacing between near lead and the lead the model figure.
Spacing between the model figure on trunk connection end pad and its periphery is set to larger than the spacing between near lead and the lead the model figure.Usually silver paste (silver paste) causes the conduction on the trunk connection end pad.Even the silver paste on the trunk connection end pad expands to outside the trunk connection end pad slightly, this silver paste can not cause yet with trunk connection end pad near the short circuit of model figure.
For realizing second purpose, the present invention's second method is characterised in that, the model figure that is made of single or multiple conductive layers is set near seal area that surrounds pixel region and terminal pads, and this conductive layer is positioned at below the interlayer insulating film that will polish.When seal area is not provided with the model figure, interlayer insulating film certainly will have the surface of inclination at the periphery of pixel region before polishing.The low reflection of the barrier film of top conductive layer is caused on the surface of this inclination, and forms the difficulty of the etching time in hole because of the optimization that causes of the uneven thickness of interlayer insulating film after the polishing.The figure that supplies a model can address this is that.The surface elevation that does not polish interlayer insulating film is in whole zone, is consistent basically on comprising near seal area, the pixel region, thereby the interlayer insulating film of polishing almost not have uneven thickness in the surface of inclination and the pixel region.
If the outside at the seal area that the model figure is arranged is not provided with the model figure, then after the polishing on seal area interlayer insulating film the surface of inclination is arranged.In the manufacturing of photoelectric device, in the time of on being fixed to substrate, the control of (being called cell gap) of gap between two substrates will be disturbed in the surface of inclination, and cause the shortcoming of seal tackiness.
For addressing these problems, the neighboring area that is preferably in seal area is provided with the model figure.
The second model figure that the model figure can be the first model figure that is made of first conductive layer that is electrically connected on the on-off element, be made of second conductive layer between first conductive layer and top conductive layer such as barrier film, perhaps the built-up pattern figure of the first and second model figures.
Best, the model figure that is provided with in the neighboring area of seal area and seal area is formed on the isolated figure, and the figure that this is isolated and the pilot layer of on-off element are same one decks.Simultaneously, if desired, be preferably formed on the isolated figure near the model figure the terminal pads district, the figure that this is isolated and the pilot layer of on-off element are same one decks.By figure is used as the substrate that is used to raise the bottom, can control the complanation of surface elevation of the interlayer insulating film of polishing more accurately.
In addition, the invention is characterized in that one or more model figures that the conductive layer below the interlayer insulating film that will polish constitutes are arranged on the adjacent area of drive circuit, this drive circuit is arranged on the periphery of pixel region, and provides signal to on-off element.Zone line between seal area and pixel region, being provided with of model figure helps utilize the complanation of polishing the interlayer insulating film that carries out.The second model figure that the model figure can be the first model figure that is made of first conductive layer, be made of second conductive layer, or the built-up pattern figure of the first and second model figures.
In addition, the invention is characterized in, single or multiple model figures are arranged on the angular zone of seal area, the sealing district is arranged on the periphery of pixel region, and the conductive layer of model figure below the interlayer insulating film that will polish constitutes, and has the periphery of the side zones that is lower than seal area and the density of the periphery of the angular zone of the seal area that forms on the periphery of pixel region.At the angular zone of seal area, the model figure of a plurality of separations is by component cloth, and this model figure is different from wide continuous model figure on sealing side and angular zone periphery.Therefore, use the unevenness that causes because of the model figure of separating to reflect in the surfaceness of not polishing interlayer insulating film of four jiaos of hermetic units, and four angle parts are compared and are had higher initial burnishing speed with four angle parts with continuous wide model figure.As a result, equate with polishing velocity in the seal area in the polishing velocity of four angle parts, and the variation of residual thickness can reduce in pixel region and seal area.
When even the single or multiple model figures that constitute when the conductive layer below the interlayer insulating film that will polish are formed on seal area except that angular zone, promptly, even when not forming the model figure in four angle parts, also will there be flute mark the angle part and at the peripheral seal area boundary member that forms of pixel region corner angle be arranged also.Therefore boundary member polished easily in the starting stage, and formed inclined surface.Inclined surface extends to interior pixels district and seal area gradually.Thereby pixel region and seal area can be done as a wholely to make it to flatten or complanation.
This model figure can be the first model figure that is made of first conductive layer, the second model figure that is made of second conductive layer, or the model figure of the first and second model graphics combine.
Feature of the present invention also is, forms at on-chip non-pixel region to comprise a plurality of uneven analog pixel figure that is positioned at the conductive layer below the interlayer insulating film that will polish, rather than form continuous wide model figure in non-pixel region.In substrate with uneven analogy model figure, owing to have very similarly uneven surfaces figure at non-pixel region with at the not polishing interlayer insulating film of pixel region, therefore initial polishing velocity is almost equal on whole substrate, and can realize high-precision surface at least in pixel region and seal area.
The direction that is preferably in two sizes in substrate upper edge repeats to form a plurality of uneven analog pixel figures, so that this layout has the space systematicness.This systematicness is corresponding with the space systematicness of inhomogeneous pixel graphics, as the matrix in pixel region.Surface on pixel region and the seal area is further significantly flattened or complanation.
Uneven analog pixel figure can be the first model figure that is made of first conductive layer, the second model figure that is made of second conductive layer, or the built-up pattern figure of the first and second model figures.The analog pixel figure that comprises the figure of interlayer insulating film will closer imitate pixel graphics.
Best, inhomogeneous analog pixel figure is formed by simulation grid line and analog data line at least.These form typical unevenness in pixel, and relevant with the systematicness of unevenness in the pixel region.
Use electro-optical device substrate to produce electro-optical device, and this electro-optical device is applicable in the display part of various electron devices, for example the light valve of projection display device.
Fig. 1 is the layout planimetric map according to the liquid crystal board substrate that is used for the reflection of reflective liquid crystal plate of the embodiment of the invention 1.
Fig. 2 is the cut-open view of being done along the B-B ' line of Fig. 1.
Fig. 3 be with Fig. 1 in the cut-open view of another structure of the corresponding input terminal pad of cross-section structure.
Fig. 4 is near the partial plan layout pixel region and the seal area in the reflective liquid crystal board substrate of embodiment 1.
Fig. 5 is near the partial plan layout the data line driver circuit in the reflective liquid crystal board substrate of embodiment 1.
Fig. 6 is near the partial plan layout the terminal pads in the reflective liquid crystal board substrate of embodiment 1.
Fig. 7 is the partial plan layout of the connection between terminal pads and the soft band lead in the reflective liquid crystal board substrate of explanation embodiment 1.
Fig. 8 is the cut-open view of being done along the A-A ' line of Fig. 7.
Fig. 9 is the partial plan layout according to the periphery of trunk connection end pad in the reflective liquid crystal board substrate of embodiment 1.
Figure 10 is the film contour curve figure of explanation according to embodiment 1 thickness distribution of the 3rd interlayer insulating film after the polishing of liquid crystal board substrate, wherein has thickness and is about 24,000
Figure C20061010022100131
The 3rd interlayer insulating film 13 be formed, and after stand CMP and handle, reach 12,000 up to residual thickness at the center of pixel region the 3rd interlayer insulating film
Figure C20061010022100132
Till.
Figure 11 is the partial plan layout according to second embodiment of the invention four angle parts of seal area in the reflective liquid crystal board substrate.
Figure 12 is the cut-open view of being done along the C-C ' line of Figure 11.
Figure 13 is the film contour curve figure of explanation according to the thickness distribution of the 3rd interlayer insulating film after the polishing of embodiment 2 liquid crystal board substrates, wherein forms to have about 24,000
Figure C20061010022100133
The 3rd interlayer insulating film of thickness, this film stands CMP and handles then, reaches 12,000 up to the residual thickness at the center of pixel region the 3rd interlayer insulating film
Figure C20061010022100134
Till.
Figure 14 is the partial plan layout according to four angle parts of seal area in the embodiment of the invention 3 reflective liquid crystal board substrates.
Figure 15 is the cut-open view of being done along the C-C ' line of Figure 14.
Figure 16 figure is the film contour curve figure of explanation according to the thickness distribution of the 3rd interlayer insulating film after the polishing of embodiment 3 liquid crystal board substrates, wherein forms to have about 24,000
Figure C20061010022100135
The 3rd interlayer insulating film of thickness, this film stands CMP and handles then, reaches 12,000 up to the residual thickness at the center of pixel region the 3rd interlayer insulating film Till.
Figure 17 is with the synoptic diagram as the image projection machine of the example of projection display apparatus of reflective liquid crystal plate as light valve.
Figure 18 is the cut-open view of reflective liquid crystal plate.
Figure 19 is the planimetric map of the reflective liquid crystal board substrate that uses in the conventional reflective liquid crystal plate.
Figure 20 is the partial plan layout of the pixel region of reflective liquid crystal board substrate among Figure 19.
Figure 21 is the cut-open view of being done along the A-A ' line of Figure 13.
Figure 22 is the cut-open view of being done along the B-B ' line of Figure 12.
Figure 23 is the film contour curve figure of the thickness distribution of the 3rd interlayer insulating film afterwards of the conventional reflective liquid crystal board substrate polishing shown in explanation Figure 19, wherein forms to have about 24,000
Figure C20061010022100141
The 3rd interlayer insulating film of thickness, this film is subjected to handle through CMP then, reaches 12,000 up to the residual thickness at the center of pixel region the 3rd interlayer insulating film
Figure C20061010022100142
Till.
Figure 24 is at the residual film thickness degree distribution curve of vertical direction along strip of paper used for sealing left side that the a-a ' line of the Figure 10 among the Figure 23 in the conventional embodiment, the embodiment 1, Figure 13 among the embodiment 2 and the Figure 16 among the embodiment 3 is done.
Figure 25 is the pixel center done along the b-b ' line of the Figure 10 among the Figure 23 in the conventional embodiment, the embodiment 1, Figure 13 among the embodiment 2 and the Figure 16 among the embodiment 3 residual film thickness degree distribution curve in vertical direction.
Figure 26 is that the strip of paper used for sealing upside done along the c-c ' line of the Figure 10 among the Figure 23 in the conventional embodiment, the embodiment 1, Figure 13 among the embodiment 2 and the Figure 16 among the embodiment 3 is at horizontal residual film thickness degree distribution curve.
Figure 27 is that the pixel center done along the d-d ' line of the Figure 10 among the Figure 23 in the conventional embodiment, the embodiment 1, Figure 13 among the embodiment 2 and the Figure 16 among the embodiment 3 is at horizontal residual film thickness degree distribution curve.
Figure 28 is that the pixel center done along the e--e ' line of the Figure 10 among the Figure 23 in the conventional embodiment, the embodiment 1, Figure 13 among the embodiment 2 and the Figure 16 among the embodiment 3 is at horizontal residual film thickness degree distribution curve.
Now describe according to embodiments of the invention with reference to the accompanying drawings.
[embodiment 1]
Fig. 1 is the layout planimetric map according to the reflective liquid crystal board substrate of the embodiment of the invention 1, and Fig. 2 is the cut-open view of being done along the B-B ' line of Fig. 1.
Reflective liquid crystal board substrate 131 according to as shown in Figure 1 present embodiment comprises: with the same at the conventional liquid crystal board substrate 31 shown in Figure 18 and 19, and the rectangular pixels district (viewing area) 20 that is furnished with the matrix of pixel electrode 14 as shown in figure 18; Be positioned at the right side of pixel region 20 and the grid line drive circuit of left hand external (Y driver) 22R and 22L, be used to scan grid line (scan electrode or line electrode); Precharge/test circuit 23 is used for data line (signal electrode or row electrode); Be positioned at the picture intelligence sample circuit 24 of outside, pixel electrode 14 bottom side, be used for providing picture intelligence to data line according to pictorial data; Be positioned at the seal area 27 of grid line drive circuit 22R and 22L, precharge/test circuit 23 and picture intelligence sample circuit 24 outsides, be used to place seal 36 (referring to Figure 18); Arrange along the bottom, and the anisotropic conductive film by therebetween and a plurality of terminal pads 26 of soft band lead adhesion; Data line driver circuit (X driver) 21 between terminal pads array 26 and seal area 127 bottom sides is used for providing sampled signal to picture intelligence sample circuit 24; Be positioned at trunk connection end pad (so-called silver point) 29R and the 29L on next door, datawire driver 21 two ends, be used for to electrode 33 is powered on glass substrate 35.Each grid line drive circuit 22R and 22L and data line driver circuit 21 have shift register, so that according to the transmission of shifted data in the shift register, sweep signal is provided and provides sampled signal to visual sample circuit 24 to grid line respectively.Signal sample circuit 24 provides picture intelligence according to sampled signal to data line.
In the present embodiment, the isolated wide continuous model graph area of seal area 127 formation that has frame shape and surround pixel region 20 as representing with hacures.Input terminal pad 26, trunk connection end pad 29R and 29L and data line driver circuit 21 are surrounded by the wide continuous model graph area shown in hacures.
The plane of the pixel region 20 of liquid crystal board substrate 131 and sectional structure be identical with shown in Figure 20 and 21 respectively.As shown in Figure 2, P well region 2 is formed on P --Semiconductor chip 1 (N --Semiconductor chip also can) upper surface on, this semiconductor chip 1 is made of monocrystalline silicon, has big size (limit of about 20mm), and is formed with field oxide film (so-called LOCOS film) thereon.P type well region 2 forms the public well region of pixel region 20, and be used to make peripheral circuit (grid line drive circuit 22R and 22L, precharge/test circuit 23, picture intelligence sample circuit 24 and datawire driver 21) the P type well region 2 ' of device keep apart, wherein pixel region 20 for example is provided with the picture element matrix of 768 * 1024 size.
Field oxide film 3 has two openings in the separated region of each pixel.The grid 4a process that is made of polysilicon or metal silicide forms at the gate insulating film 4b of opening central authorities; The N that the both sides of grid 4a form on P type well region 2 + Source region 5a and N +Drain region 5b forms on-off element with grid 4a, and promptly N-channel MOS FET (isolated-gate field effect transistor (IGFET)) is used for pixel selection.As shown in figure 20, the grid 4a that is arranged in a plurality of pixels on the line extends along scan-line direction (pixel line direction), forms grid line 4.
Although not shown among Fig. 2, the P type capacitance electrode district 8 consistent with line forms in another opening on P type well region 2.The capacitance electrode 9a that is made of polysilicon or metal silicide forms maintenance electric capacity (accumulation capacitance) C with P type capacitance electrode district 8, be used to keep selected signal by the MOSFET that is used for pixel selection, this capacitance electrode 9a forms in P type capacitance electrode district 8, and dielectric film (deielectric-coating) 9b is arranged between the two.
Keep the polysilicon that electric capacity 9a can be by playing the grid 4a among the MOSFET or the film depositing operation of metal silicide layer to form, this MOSFET is used for pixel selection.Dielectric film (deielectric-coating) 9b below the maintenance electric capacity 9a also can form by the insulator film deposition technology of gate insulating film 4b.Dielectric film 9b and 4b form by thermal oxidation and have about 400
Figure C20061010022100161
To 800
Figure C20061010022100162
Thickness.It is 1000 that capacitance electrode 9a and grid 4a have thickness
Figure C20061010022100163
To 2000
Figure C20061010022100164
Polysilicon layer and thickness be 1000
Figure C20061010022100165
To 3000
Figure C20061010022100166
Refractory metal such as the unitized construction of the silicide layer of Mo or W.By the self-regulation ion implantation technology of the N type impurity that on grid 4a side base piece surface, carries out, form source electrode and drain electrode 5a and 5b as mask.
By comprising that ion injects and the doping process of thermal treatment (diffusion again) forms P type capacitance electrode district 8.Ion injects and can carry out before grid forms.After dielectric film 9b forms, mix with P type trap 2 in identical impurity so that there is the impurity content higher than its inside on the surface of P type trap 2, and form low resistivity zone.Impurity content better is 1 * 10 in P type trap 2 17Cm -3Perhaps still less and be more preferably from 1 * 10 16Cm -3To 5 * 10 16Cm -3Source electrode and drain region 5a and 5b preferably impurity level be from 1 * 10 20Cm -3To 3 * 10 30Cm -3Impurity level is from 1 * 10 preferably in P type capacitance electrode district 8 18Cm -3To 5 * 10 19Cm -3, consider as reliability and the crushing resistance (pressure resistance) of the dielectric film 9b of the ingredient that keeps capacitor C, be more preferably from 1 * 10 18Cm -3To 1 * 10 19Cm -3
First interlayer insulating film 6 forms on grid 4a and capacitance electrode 9a, and first conductive layer (being called the first metal layer later on) that is made of aluminium substantially forms on dielectric film 6.The first metal layer comprises the data line 7 (with reference to Figure 20) that extends along column direction, begin to extend from data line 7 as broach, and the source electrode lead 7a that contact by contact hole 6a and source region 4a conduction, conduct electricity to contact and pass through contact hole 6c and capacitance electrode 9a by contact hole 6b and drain region 5b and conduct electricity the relaying lead 10 that contacts.
First interlayer insulating film 6 is about 1000 by for example deposit thickness
Figure C20061010022100167
HTO film (silicon oxide layer that forms by high temperature CVD technology) and deposit thickness be about 8000
Figure C20061010022100168
To 10000
Figure C20061010022100169
BSPG film (silicate glass film that boron and phosphorus are arranged) form.The first metal layer that forms source electrode lead 7a and relaying lead 10 has the four-layer structure that for example is made of Ti/TiN/AL/TiN by the order such end of since.
End Ti layer has about 100
Figure C200610100221001610
To 600
Figure C200610100221001611
Thickness, the TiN layer has about 1000 Thickness, the 3rd Al layer has about 4000
Figure C200610100221001613
To 10,000
Figure C200610100221001614
Thickness, top TiN layer has about 300
Figure C200610100221001615
To 600
Figure C200610100221001616
Thickness.
Second interlayer insulating film 11 is formed on the first metal layer, and is formed on second interlayer insulating film 11 by second conductive layer (hereinafter referred to as second metal level) that aluminium constitutes.Second metal level has covered the major part of pixel region 20, and comprises the barrier film 12 that is used to shield two compartments between the adjacent pixel electrodes 14.Second metal level that forms barrier film 12 is used as in peripheral circuit (grid line drive circuit 22R and 22L, precharge/test circuit 23, picture intelligence sample circuit 24 and data line driver circuit 21) and is connected lead 12b (with reference to figure 2).
Second interlayer insulating film 11 by for example utilize plasma CVD technology by tetraethyl orthosilicate (tetraethyl ortho-silicate) (TEOS) deposit thickness be about 3000
Figure C20061010022100171
To 6000
Figure C20061010022100172
Silicon oxide layer (hereinafter being called the TEOS film), deposit spin-coating glass film (SOG) thereon, utilize deep etch technology that it is corroded, and deposit thickness is about 2000 thereon
Figure C20061010022100173
To 5000
Figure C20061010022100174
The 2nd TEOS film form.
Second metal level and the first metal layer that form barrier film 12 and similar portions have same structure, the Ti/IiN/Al/TiN four-layer structure that for example forms the end of since.
End Ti layer has about 100
Figure C20061010022100175
To 600
Figure C20061010022100176
Thickness, the 2nd TiN layer has about 1000
Figure C20061010022100177
Thickness, the 3rd Al layer has about 4000
Figure C20061010022100178
To 10,000
Figure C20061010022100179
Thickness, top TiN layer has about 300 To 600
Figure C200610100221001711
Thickness.
Jack 12a is arranged on the corresponding position of barrier film 12 and relaying lead 10.The 3rd interlayer insulating film 13 is formed on the barrier film 12, and substantially corresponding with pixel rectangular pixel electrodes 14 is formed on the interlayer insulating film 13 as reflecting electrode.The 3rd interlayer insulating film forms can resembling in second interlayer insulating film 11, promptly is about 3000 by deposit thickness
Figure C200610100221001712
To 6000
Figure C200610100221001713
The TEOS film, deposit sog film thereon, utilize deep etch technology that it is corroded, and deposit thickness is about 16,000 To 24,000
Figure C200610100221001715
The 2nd TEOS film.On the other hand, the 3rd interlayer insulating film can only be formed by the TEOS film, rather than is formed by the sog film that inserts between two TEOS films.Thickness range is preferably from 16,000 in this case To 24,000
Figure C200610100221001717
Be to improve moisture resistance, can be below the TEOS film or above the formation silicon nitride film.When silicon nitride film is upper membrane, before silicon nitride film, the TEOS film is flattened by CMP technology, perhaps silicon nitride film is flattened by CMP technology.
Contact hole 16 passes the 3rd and second interlayer insulating film 13 and 11 and forms, thereby is positioned at the opening 12a of barrier film 12.After using refractory metal such as tungsten filling contact hole 16 by CVD technology, utilize chemically mechanical polishing (CMP) technology that the high melting point metal layer of formation on the 3rd interlayer insulating film 13 and the front of interlayer insulating film 13 are flattened, form minute surface.After the polishing, in the thinnest part, the residual thickness of interlayer insulating film 13 is adjusted at about 4,000
Figure C200610100221001718
To 10,000
Then, forming thickness by the low temperature sputtering technology is about 300
Figure C20061010022100182
To 5,000
Figure C20061010022100183
Aluminium lamination, and to form the limit by graphical technology be the rectangular pixel electrodes 14 of 15 μ m to 20 μ m.A metal level of separation layer 12 is crossed in the attachment plug (conductive interlayer part) 15 that is made of refractory metal, and relaying lead 10 and pixel electrode 14 are electrically connected.Can make 13 complanations of the 3rd interlayer insulating film by CMP technology, contact hole and embedding therein refractory metal such as tungsten are set form attachment plug 15.On the other hand, can enlarge the opening 12a in second metal level 12, in this opening 12a, can form by second metal level 12 and constitute and have for example second a relaying lead of rectangular shape, the first relaying lead 10 and the second relaying lead can interconnect, and can the second relaying lead be connected on the pixel electrode 14 by attachment plug 15.The thickness that is made of monox or similar substance is about 500
Figure C20061010022100184
To 2,000
Figure C20061010022100185
Passivating film 17 be formed on the whole pixel electrode 14.Calibration membrane (alignment film) is formed on the whole passivating film 17, and stands friction (rubbing) and handle in the liquid crystal board manufacturing.In the present embodiment, although pixel electrode 14 is formed by the 3rd conductive layer (hereinafter referred to as the 3rd metal level), when substrate is when forming by the technology that is used to deposit a plurality of metal levels, pixel electrode 14 also can form in upper layer.In all cases, pixel electrode 15 is all formed by metal level topmost.
As mentioned above, silicon oxide film is used as the passivating film 17 that covers pixel region 20, and thickness is about 2,000
Figure C20061010022100186
To 10,000
Figure C20061010022100187
Silicon nitride film be used in peripheral circuit region, seal area and the scribing part.On passivating film 17, can form dielectric mirror film.
As shown in Figure 1, the seal area 127 of the most pixel region 20 that occupies rectangular shaped semiconductor device 1 with frame shape surrounds.Seal area 127 is formed on pixel region 20 and does not comprise borderline region between the non-pixel region of liquid crystal (peripheral circuit region, terminal pads district and scribe area).In the present embodiment, seal area 127 comprises part peripheral circuit (grid line drive circuit 22R and 22L, precharge/test circuit 23 and picture intelligence sample circuit 24), has only data line driver circuit 21 to be positioned at the outside of seal area 127 like this.Certainly, data line driver circuit 21 also can be positioned at seal area 127 inside.
In the present embodiment, as shown in Figure 2, the cross-section structure of seal area 127 comprise by being formed on the field oxide film 3 of constituting of polysilicon or metal silicide and with the separated wide row graph 127a of grid 4a; The wide continuous lower model figure A that constitutes by the first metal layer; With the isolated wide continuous cope figure B that constitutes by second metal level.Figure 127a can form by the technology that is used for gate electrode 4a.Model figure A and B can form by the technology that is used for first and second metal levels respectively.The thickness corresponding thickness of the surface elevation of the 3rd interlayer insulating film 13 and figure 127a and model figure A and B is raise equably, and equates with the surface elevation of pixel region and peripheral circuit region substantially.
Shown in the hacures among Fig. 4 to 6 and Fig. 9, form a model graph area at the periphery of the data line driver circuit 21 that is positioned at seal area 127 outsides and the periphery of trunk connection end pad 29R and 29L and input terminal pad 26 except that conductor section, this model graph area electricity is floated or is fixed on the supply voltage.In the present embodiment, the structure that input terminal pad 26 has the lower layer 26a that is used as the first metal layer and piles up as the upper layer 26b of second metal level, and the cross-section structure of model graph area comprises the wide continuous lower model figure A as the first metal layer on first interlayer insulating film 6 that is formed on the field oxide film 3; With the wide continuous cope figure B that is formed on conduct second metal level on second interlayer insulating film 11.Model figure A and B can form by the technology that is used for metal level.The surface elevation of the 3rd interlayer insulating film 13 is raise by the thickness corresponding thickness with model figure A and B after film forms at once equably, and by the rising effect of adjacent area, the height directly over the input terminal pad 26 equates with the surface elevation of pixel region and peripheral circuit region substantially.
Shown in Figure 4 and 5, model figure M is located at a plurality of lead L that begin to extend from data line driver circuit 21 among the X of frontier district between isolated rectangular conductor OUTBetween, this frontier district X is between the lower edge and data line driver circuit 21 of seal area 127.Model figure M also can form by the technology that is used for metal level between lead.
In the formation of input terminal pad 26, upper layer 26b is embedded in the big opening that is provided with in second interlayer insulating film 11 on lower layer 26a thereby forms big flute mark on upper layer 26, and the 3rd interlayer insulating film 13 directly over upper layer 26 also has flute mark inevitably.When the depositing operation of the 3rd interlayer insulating film 13 comprises the formation of sog film, can alleviate the flute mark on the upper layer 26 to a certain extent.
Because significantly greater than the zone of the contact hole of lead electrode, therefore the flute mark on the 3rd interlayer insulating film 13 directly over the input terminal pad 26 can not only compensate by extra formation sog film in the zone of input terminal pad 26.
Fig. 3 is the cut-open view of another structure of input terminal pad.Among Fig. 3, on lower layer 26a, form after a plurality of little contact holes, form terminal pads 26 ' by embedding upper layer 26b '.In this structure, the phenomenon that the material that is used for upper layer 26b ' is fallen into contact hole is suppressed, and has formed tiny flute mark independently; Thereby the surface of upper layer 26b ' is flattened.As a result, the surface of the 3rd interlayer insulating film 13 of formation flattens easily, and can not reflect the flute mark that those are tiny.
In aforesaid present embodiment, be vertically formed wide continuous model figure (model figure A and B), thereby make the density of figure in the whole zone of the outside of pixel region and peripheral circuit region, almost reach 100%, therefore surface elevation basically identical on whole substrate of the 3rd interlayer insulating film 13 after deposition.Solid line among Fig. 2 and 3 is illustrated in the CMP polishing height of polished surface of the 3rd interlayer insulating film 13 afterwards.Because the surface of interlayer insulating film 13 does not obviously exceed in the zone of input terminal pad 26 and 26 ' before polishing, therefore realized all even medium polishing velocity, and do not exposed input terminal pad 26 and 26 '.The CMP polishing time can increase, and therefore with conventional depth (about 4,000
Figure C20061010022100201
) compare the polishing degree of depth also can increase.The thickness of the 3rd interlayer insulating film 13 reduced after the advantage of this uniform polish speed caused and polishes.The aspect ratio of the contact hole 16 that is provided with on the opening 12a of barrier film 12 in pixel region 20 and the diameter of attachment plug 15 reduce, and the open area of opening 12a is reduced, and the result has improved shielding properties.In not forming the CMP glossing of sog film, the polishing degree of depth of increase can be slowed down the dark step at the opening 12a place that forms when the 3rd interlayer insulating film only is made of the TEOS film.Therefore, can simplify the depositing operation of the 3rd interlayer insulating film 13, the result has improved throughput rate.
As in the plane figure of Fig. 1 shown in the hacures, in the present embodiment, model figure district is positioned on the outside of the almost whole seal area 127 except that data line driver circuit 21, signal conductor, power lead, input terminal pad 26 and trunk connection end pad 29R and 29L.Shown in Figure 4 and 5, be formed on lead L OUTModel figure N with substrate right side and left side RAnd N LBetween rectangular conductor between model figure M be arranged among the zone line X between data line driver circuit 21 (comprise shift register and form the logical circuit of sampled signal according to the output of shift register) and the seal area 127.Lead L OUTAnd the spacing between the model figure M is about 5 μ m between lead.The output lead L that is used for sampled signal output OUTBegin to extend to picture intelligence sample circuit 24 from data line driver circuit 21 (shift register and logical circuit), so the model figure has rectangular shape between lead.As shown in Figure 6, there are two kinds of zones to extend to the lead of substrate inside, promptly are used for to data line driver circuit 21 input signals (DXIN (data-signal), power supply V from input terminal pad 26 DdxAnd V Ssx, clock signal and reverse clock signal) lead L INAnd be used for to grid line drive circuit 22R and 22L and precharge/test circuit 23 input signals (DYIN (data-signal), power supply V DdyAnd V Ssy, clock signal and reverse clock signal) lead.Therefore the lead L to column direction (being vertical direction in the drawings) that extracts out from input terminal pad 26 is divided into the lead L that guides data line driver circuit 21 into INWith other lead on the online direction in conductor section (being horizontal in the drawings).Like this, input terminal pad 26, a plurality of isolated rectangle that forms between input lead are separated model figure S 1To S 3, with at lead L to data line driver circuit 21 input INBetween between the isolated rectangular conductor that forms model figure T in the zone and the zone line Y between the data line driver circuit 21 of input terminal pad 26.In Fig. 6, the quantity of the input terminal pad 26 that illustrates reduces.
The flat shape of each input terminal pad 26 comprise as the rectangular conductive contact portion 261 of major part and from the right side of conduction contact part 261 or left side the lead that extends to substrate inside (on column direction) with little width extract part 262 out.The lead that is positioned at each input terminal pad 26 on substrate center line right side is extracted part 262 out and is positioned at the left side of conduction contact part 261, and the lead extraction part 262 that is positioned at each the input terminal pad 26 the substrate center line on the left of is positioned at the right side of conduction contact part 261.Isolated in a lateral direction rectangle is separated model figure S 2Being arranged in lead extracts out between the part 262.And then isolated rectangle is separated model figure S 3Be formed on and have the lead of extracting the lead L that part 262 extracts out out from lead and extract out between the end of part 262.Isolated rectangle is separated model figure S 1Be formed on the next door, edge of substrate side input terminal pad 26.
Right side and left side model figure N at substrate RAnd N LExtend to the position of input terminal pad 26, and isolated separation model figure S 2' be formed on the space that the rightmost of input terminal pad 26 and leftmost lead are extracted part 262 next doors out.Model figure N RAnd N LEnd and the end of input terminal pad 26 be in same level, and isolated separation model figure S 0Be arranged on model figure N on the substrate angle RAnd N LTerminal next door.The flat shape of the model figure of these separations is not limited to rectangle (comprising square), can select different shape (triangle, polygon and shaped form).For example, hexagon can be set and separate the model figure to form honeycomb shape.
As shown in figure 18, by hot press, these input terminal pads 26 can be connected on the soft band lead 39 by the anisotropic conductive film between them (ACF) 38.Dotted line among Fig. 6 is represented the edge in the zone that occupied by anisotropic conducting film 38.Shown in Fig. 7 and 8, soft band lead 39 comprises insulation soft band 39a and a plurality of bar shaped lead-in wire 39b that are connected thereto.Anisotropic conductive film 38 folder is inserted between the array of the edge of soft band 39a and input terminal pad 26.
Anisotropic conductive film 38 is about 5 μ m by grain size and constitutes to conductive particle 38a and the insulating gel viscosity resin 38b of 10 μ m.Suppressing soft band 39a makes thickness be reduced to about 2 μ m to 10 μ m.Be connected because the lead-in wire 39b of each terminal pads 26 and corresponding soft band lead 39 is the conductive particle 38a conductions by the Discrete Distribution of compacting, so 38 of anisotropic conductive film have electric conductivity in vertical direction.In Fig. 7 and 8, the quantity of the input terminal pad 26 that illustrates reduces equally.
By sedimentation model graph area on the periphery of input terminal pad 26 (model figure A and B), the surface elevation of the 3rd interlayer insulating film 13 that forms on input terminal pad 26 is not raise separately, but equates with the surface elevation of pixel region 20 substantially; Therefore in glossing, the regional initial polishing velocity reduction at input terminal pad 26 has prevented that input terminal pad 26 is polished, can realize the attenuation of the 3rd interlayer insulating film 13.If the model graph area forms continuously, then after anisotropic conductive film 38 hot press, will between input terminal pad 26, produce short circuit by conductive particle 38a and model figure around input terminal pad 26.
Under the contrast, in the present embodiment, the model figure is not set between input terminal pad 26, the figure E that therefore do not supply a model, and the model figure S that is separated of input terminal pad 26 1To S 2Surround, prevented the short circuit between the input terminal pad 26.For preventing short circuit, input terminal pad 26 and the model figure S that separates by anisotropic conductive film 38 0To S 2Between and the model figure S of each separation 0To S 2Between gap ratio lead L and model figure S 3Between spacing (about 5 μ m) wide.
For further suppressing to be right after the fluctuating of the 3rd interlayer insulating film 13 in the zone of input terminal pad 26 after the film deposition, can between input terminal pad 26, form the model figure, and the model figure between input terminal pad 26 also is divided into the model figure of separation, so that prevent the short circuit between the input terminal pad 26.When the illustraton of model figurate number amount of separating increased, the possibility of short circuit reduced; But when this quantity increases, be right after after the film deposition in the model graph area surface undulation of the 3rd interlayer insulating film 13 clearly.Therefore, preferably select moderate quatity.The flat shape of the model figure of these separations is not limited to rectangle (comprising square), can select different shape (triangle, polygon and shaped form).For example, the model figure of hexagon separation can be set to form honeycomb shape.
Fig. 9 is the partial plan layout of the periphery of trunk connection end pad 29R.Trunk connection end pad 29R (29L) is connected to lead L (to be used to the polarity of conversion input voltage that normal voltage is provided, the alternating current that this input voltage is used for liquid crystal drives) on rectangular pads, and with silver paste be connected to glass substrate 35 on the electrode 33, this lead L is from the terminal pads 26 of the ragged edge on data line driver circuit 21 next doors.Trunk connection end pad 29R (29L) is by model figure N RAnd N LSurround.As a result, as in the terminal pads 26, be right after after the film deposition, the surface elevation of the 3rd interlayer insulating film 13 is consistent.
In the present embodiment, trunk connection end pad 29R and model figure N RBetween spacing for example be set to 70 μ, even so that also can prevent short circuit when stretching out slightly at the silver paste of coating.That is, trunk connection end pad 29R and model figure N RBetween gap ratio lead and the spacing between the nearest model figure wide.The model figure that surrounds trunk connection end pad 29R can be the model figure of separating.
Figure 10 is the film contour curve figure of explanation according to embodiment 1 thickness distribution of the 3rd interlayer insulating film 13 after 131 polishings of liquid crystal board substrate, wherein has thickness and is about 24,000
Figure C20061010022100231
The 3rd interlayer insulating film 13 be formed, and after stand CMP and handle, reach 12,000 up to residual thickness at the center of pixel region 20 the 3rd interlayer insulating film 13
Figure C20061010022100232
Till.In Figure 24, the curve that draws with mark △ illustrates the left strip of paper used for sealing of being done along the a-a ' line of Figure 10 and distributes at the residual thickness of vertical direction.In Figure 25, the curve that draws with mark △ illustrates the center pixel of being done along the b-b ' line of Figure 10 and distributes at the residual thickness of vertical direction.In Figure 26, the curve that draws with mark △ illustrates the last strip of paper used for sealing of being done along the c-c ' line of Figure 10 and distributes at horizontal residual thickness.In Figure 27, the curve that draws with mark △ illustrates the center pixel of being done along the d-d ' line of Figure 10 and distributes at horizontal residual thickness.In Figure 28, the curve that draws with mark △ illustrates along the following strip of paper used for sealing zone that the e-e ' line of Figure 10 is done and distributes at horizontal residual thickness.
These curve proofs maximum ga(u)ge difference between pixel region 20 and seal area 127 is 2,720 , and the spacing between the outline line is (with 1,000 The thickness difference correspondence) obviously greater than the situation among Figure 23.The flatness of pixel region 20 improves 2 times or more.
The maximum difference of going up thickness at whole substrate (chip) drops to about 2,910
Figure C20061010022100235
The top side of seal area 127 has the gradient of the core of flute mark to drop to approximately half or still less, the gradient of the core of the bottom side flute mark of seal area 127 drops to about 1/4th or still less.Minimum thickness is located at drift angle (top corner) in the right side of seal area 127 and left side, has therefore prevented the projection at center, and gradient drops to 1/4th or still less.Wide continuous model graph area (model figure A and B) causes this tangible improvement in the almost whole outside of pixel region and peripheral circuit region.
The maximum difference of thickness is reduced to 1,000 in pixel region 20
Figure C20061010022100236
Or it is littler better.In the thickness distribution of pixel region 20, the perpendicular line of pixel center is corresponding with the concave point of thickness (trough) line, and the center of input terminal pad 26 and maximum ga(u)ge (about 14,500 ) correspondence.Compare with the regular situation among Figure 23, this points out out in the zone of input terminal pad 26 polishing not enough.
[embodiment 2]
Figure 11 is the partial plan layout according to second embodiment of the invention four angle parts of seal area in the reflective liquid crystal board substrate.Figure 12 is the cut-open view of being done along the C-C ' line of Figure 11.In Figure 11, have the region representation the first metal layer of point-like figure, have hatched region representation second metal level, and the 3rd metal level is not shown.Structure except that describing below is identical with structure according to the reflective liquid crystal board substrate of embodiment 1.
Reflective liquid crystal board substrate 231 have with according to the essentially identical structure of reflective liquid crystal board substrate of embodiment 1.Pixel region 20 is surrounded by the seal area 127 of isolated wide continuous model graph area (the model figure B of the model figure A of the first metal layer and second metal level).Input terminal pad 26, trunk connection end pad 29R and 29L and data line driver circuit 21 are also surrounded by wide continuous model graph area (the model figure B of the model figure A of the first metal layer and second metal level).With wide continuous model figure, as in embodiment 1, being positioned at the lead L of sealed sides OUTBetween model figure A difference, in the rectangular area at four jiaos of hermetic unit 127C places of seal area 127, the model figure of the first metal layer forms the group that comprises a plurality of independently separated graphicses.Specifically, a plurality of rectangle separated graphicses that respectively have different area aIn vertical direction with laterally arrange, and have 50% or littler pattern density dividually.Separated graphics aHas mutually different area less than input terminal pad 26.Model figure B ' at four jiaos of hermetic unit 127C place second metal levels has the wide continuous surface of rectangle.The result reflects the model figure of separation at the not polished surface of four jiaos of hermetic unit 127C the 3rd interlayer insulating film 13 shown in the dotted line among Figure 12 aThe roughness of unevenness.
Be provided with in the CMP that four jiaos of hermetic unit 127C have a surface of the 3rd interlayer insulating film 13 on the substrate of separation model figure of low Density Distribution handles, four jiaos of hermetic unit 127C have the initial burnishing speed higher than the mild bump pad side of seal area 127.Therefore the polishing velocity of the seal area 127 that is surrounded by four unit at four jiaos of hermetic unit 127C places during polishing equals the polishing velocity of interior zone, and the difference of residual thickness is suppressed between pixel region 20 and the seal area 127.Particularly, it is important making the right corner of bottom side of the seal area 127 among the angle part 127a of four unit and left comer that roughening is arranged in advance.
When the model figure of separating aHave substantially the area that equates, and at four jiaos of hermetic unit 127C places during even or stochastic distribution, the pattern density that reduces (ratios of the whole model graphics areas that reduce on the per unit area) can cause bigger model figure aBetween spacing, and therefore model figure aHas little distribution density.As a result, the initial burnishing speed of the 3rd interlayer insulating film 13 is higher than the initial burnishing speed of four jiaos of hermetic unit 127C peripheries, and the surface of inclination at first forms at the periphery of four jiaos of hermetic unit 127C, and the surface that tilts during polishing is gradually to internal extended.If pattern density is identical, separate the model figure when reducing aQuantity the time and when increase separating the model figure aArea the time, then these be rise and fall and have bigger initial burnishing speed.Identical with above-mentioned situation, the border of four jiaos of hermetic unit 127C forms the surface of inclination fast, and the surface that tilts during polishing is gradually to internal extended.Owing to be provided with the model graphical distribution that is used to accelerate the initial burnishing speed that four jiaos of hermetic unit 127C compare with its periphery in the present embodiment, therefore residual thickness is subjected to the influence as the residual thickness of four jiaos of hermetic unit 127C of standard thickness, thereby and residual thickness is being equated with seal area 127 peripheries and the pixel region 20 that are surrounded by four jiaos of hermetic unit 127C of four unit.Therefore, seal area 127 and pixel region 20 flatten or are flattened.
As shown in figure 11, at four jiaos of hermetic unit 127C, a plurality of rectangles are separated the model figure aVertically be arranged in the right side and the left side of seal area, and a plurality of rectangle is separated the model figure aAlong the top side and the bottom side that are horizontally arranged in seal area.Each vertical rectangle that has the highest initial burnishing speed on vertical (vertically) limit is separated model figure aBe believed to be helpful in the complanation of the vertical direction of seal area, and have each horizontal rectangle separation model figure of the highest initial burnishing speed on vertical (laterally) limit aBe believed to be helpful in the complanation of the horizontal direction of seal area.In the present embodiment, vertical rectangle is separated the model figure aBe not arranged near the top side and bottom side of hermetic unit, and laterally rectangle is separated the model figure aBe not arranged near the right side and left side of hermetic unit.But vertical rectangle is separated the model figure aBe arranged near the right side and left side of hermetic unit, and laterally rectangle is separated the model figure aBe arranged near the top side and bottom side of hermetic unit.As a result, realized high initial burnishing speed by high initial burnishing speed at four jiaos of hermetic unit 127C at these model figures of vertical and horizontal direction.
To separating the model figure aThe change of shape, array and pattern density will further improve the complanation of seal area 127 and interior zone.
When four jiaos of hermetic unit 127C do not have model figure (pattern density is zero), therefore polished easily because the angle begins to have flute mark and boundary member projection from its periphery on the starting stage border of polishing, thus form the surface of inclination.The surface that tilts is progressively to inner area extension.As a result, pixel region 20 and seal area flatten fully or are flattened.
Figure 13 is the film contour curve figure of explanation according to the thickness distribution of the 3rd interlayer insulating film 13 after 231 polishings of embodiment 2 liquid crystal board substrates, wherein forms to have about 24,000
Figure C20061010022100251
The 3rd interlayer insulating film 13 of thickness, this film 13 stands CMP and handles then, reaches 12,000 up to the residual thickness at the center of pixel region 20 the 3rd interlayer insulating film 13
Figure C20061010022100261
Till.In Figure 24, the curve that draws with mark illustrates the left strip of paper used for sealing of being done along the a-a ' line of Figure 13 and distributes at the residual thickness of vertical direction.In Figure 25, the curve that draws with mark illustrates the center pixel of being done along the b-b ' line of Figure 13 and distributes at the residual thickness of vertical direction.In Figure 26, the curve that draws with mark illustrates the last strip of paper used for sealing of being done along the c-c ' line of Figure 13 and distributes at horizontal residual thickness.In Figure 27, the curve that draws with mark illustrates the center pixel of being done along the d-d ' line of Figure 13 and distributes at horizontal residual thickness.In Figure 28, the curve that draws with mark illustrates along the following strip of paper used for sealing zone that the e-e ' line of Figure 13 is done and distributes at horizontal residual thickness.
These curve proofs maximum ga(u)ge difference between pixel region 20 and seal area 127 is 1,380
Figure C20061010022100262
, and the spacing between the outline line is (with 1,000 The thickness difference correspondence) greater than the situation among Figure 10.Compare with embodiment 1, the flatness of pixel region 20 improves 2 times or more.Also still have big thickness inadequately owing to comprise the zone polishing of the input terminal pad 26 of wide continuous model figure, the maximum difference of going up thickness at whole substrate (chip) is about 2,500
Figure C20061010022100264
Compare with embodiment 1, the top side of seal area 127 have the gradient of the core of flute mark drop to approximately half or still less.The right side of seal area 127 and left side are smooth basically, because the model figure that low pattern density is arranged in the lower right corner and the lower left corner of seal area 127 promotes polishing.
Yet as shown in figure 13, seal area still has big thickness at the periphery in the lower right corner and the lower left corner, and therefore the maximum difference of thickness is not less than 100 in pixel region 20 and seal area 127
Figure C20061010022100265
When four jiaos of hermetic unit 127C do not have the model figure aWhen (pattern density is zero), interior pixels district 20 further flattens or is flattened, but the periphery of four jiaos of hermetic unit 127C has steep gradient.Can form the model figure like this a, promptly begin pattern density to be reduced to the upper position in right side and left side or to the core of bottom side from right base angle and left base angle (bottomright and left corner) 127C.In this case, pixel region 20 and seal area 127 can further flatten or be flattened.
[embodiment 3]
Figure 14 is the partial plan layout according to four angle parts of seal area in the embodiment of the invention 3 reflective liquid crystal board substrates.Figure 15 is the cut-open view of being done along the C-C ' line of Figure 14, in Figure 14, has the region representation the first metal layer of point-like figure, have hatched region representation second metal level, and the 3rd metal level is not shown.Structure except that describing below is identical with structure according to the reflective liquid crystal board substrate of embodiment 1.
Reflective liquid crystal board substrate 331 in the present embodiment has and is positioned at the seal area 227 that surrounds pixel region 20 and the inhomogeneous analog pixel figure P as model pattern matrix (figure that two dimension repeats) on the perimeter thereof.Inhomogeneous analog pixel figure P vertically and flatly extends on the periphery of data line driver circuit 21, trunk connection end pad 29R and 29L and input terminal pad 2.On the 3rd interlayer insulating film 13, each inhomogeneous analog pixel figure P produces the inhomogeneous figure that is similar to the pixel graphics in the pixel region 20 and has the volume similar to each pixel.
In the present embodiment, each inhomogeneous analog pixel figure comprises: have and the simulation grid line 4 that is positioned at the first metal layer of the grid line 4 basic equal widths on the pixel bottom PThe data line 7 of the first metal layer of pixel; Has analog data line 7 with the first metal layer of source electrode lead 7a and relaying lead 10 basic equal widths PAnalog source electrode lead 7a P Analog junction lead 10 PWide simulation barrier film 12 with second metal level of the barrier film 12 of second metal level in the imitation pixel portion PTherefore the pattern density of bottom lead and the first metal layer is about 25% in each pixel, the pattern density of the inhomogeneous analog pixel figure P that is made of the first metal layer and second metal level is set to substantially the same value.
At the periphery and the borderline region X ' of upper and lower seal area (side) 227, the signal conductor L of the first metal layer from data line driver circuit 21 to picture element signal sample circuit 24 OUTBe used as analog data line 7 by x PThe simulation grid line 4 of the first metal layer P' and analog source electrode lead 7a P' be not connected to analog data line 7 POn.
Inhomogeneous analog pixel figure P vertically and flatly repeats on substrate, but the matrix of the matrix of inhomogeneous analog pixel figure P and the pixel region in the present embodiment 20 is slightly different.Can be by changing the layout and the signal conductor L of device among peripheral circuit region such as data line driver circuit 21, picture element signal sample circuit 24 and grid line drive circuit 22R and the 22L OUTLayout make the matrix of inhomogeneous analog pixel figure P and pixel region 20 unified.
On the substrate 331 that is provided with inhomogeneous analog pixel figure P, before CMP handles, on surface, periodically arranged and resembled the such uneven surface figure of inhomogeneous pixel graphics except the zone of the 3rd interlayer insulating film 13 of pixel region 20.Therefore, begin to make polishing velocity consistent on whole substrate 331 from the initial burnishing stage, and pixel region 20 and seal area 227 can high precision flatten or flattened at least.
Figure 16 figure is the film contour curve figure of explanation according to the thickness distribution of the 3rd interlayer insulating film 13 after 331 polishings of embodiment 3 liquid crystal board substrates, wherein forms to have about 24,000 The 3rd interlayer insulating film 13 of thickness, this film 13 stands CMP and handles then, reaches 12,000 up to the residual thickness at the center of pixel region 20 the 3rd interlayer insulating film 13
Figure C20061010022100272
Till.In Figure 24, the curve that draws with mark zero illustrates the left strip of paper used for sealing of being done along the a-a ' line of Figure 16 and distributes at the residual thickness of vertical direction.In Figure 25, the curve that draws with mark zero illustrates the center pixel of being done along the b-b ' line of Figure 16 and distributes at the residual thickness of vertical direction.In Figure 26, the curve that draws with mark zero illustrates the last strip of paper used for sealing of being done along the c-c ' line of Figure 16 and distributes at horizontal residual thickness.In Figure 27, the curve that draws with mark zero illustrates the center pixel of being done along the d-d ' line of Figure 16 and distributes at horizontal residual thickness.In Figure 28, the curve that draws with mark zero illustrates along the following strip of paper used for sealing zone that the e-e ' line of Figure 16 is done and distributes at horizontal residual thickness.
These curve proofs maximum ga(u)ge difference between pixel region 20 and seal area 127 (comprising four jiaos of hermetic unit 127C) is about 850 , and the maximum difference of thickness is about 950 on whole substrate
Figure C20061010022100282
Pixel region 20 and seal area 227 flatten satisfactorily.Although it is not enough that the neighboring area of input terminal pad 26 demonstrates polishing slightly, will further flatten by this zone of pattern density that reduces inhomogeneous analog pixel figure P.
Be included in two openings that in field oxide film, are provided with, the grid line 4 of bottom, the data line 7 of the first metal layer, source electrode lead 7a, the barrier film 12 of relaying lead 10, the second metal levels and jack 12a in the part that forms the uneven surface figure on the pixel region.In the present embodiment, although the simulation grid line 4 of the first metal layer PThe grid line 4 of imitation bottom, but simulation grid line 4 PAlso can form end conductor layer.In addition, each section of inhomogeneous analog pixel figure P can comprise the simulation opening of two openings that are provided with in the imitation field oxide film 3 and the simulation jack of imitation jack 12a.The inhomogeneous analog pixel figure that obviously is similar to pixel graphics can be formed on the periphery of pixel region 20 by same technology, and does not have extra step, and pixel region 20 and seal area 227 can further flatten.
Starting stage in CMP handles, the intensive bossing on surface is difficult to polishing, and since isolated projection by fast polishing, therefore sparse bossing is easy to polishing.As two zones, the i.e. rarefaction of the compact district of intensive therein protruding stochastic distribution and sparse therein protruding stochastic distribution, when there was basic identical size in two zones, the rarefaction had higher initial burnishing speed, and therefore the surface that tilts after the polishing will be formed on these zones.The rarefaction has low pattern density as a result.On the other hand, as long as want polished surface to have uniform pattern density, the projection (island) that then has little surface area just has higher initial burnishing speed, because the girth on island is longer with respect to the area on island.In the initial burnishing stage, the zone polishing difficulty maximum of the large tracts of land projection of dense distribution is at random arranged therein.A representational example is the wide row graph that covers gamut.On the contrary, in the initial burnishing stage, there is the zone of the small size projection of sparse distribution at random polished easily therein.A representational example is the zone (not having the model figure) that does not have projection.Suppose in the initial burnishing stage, have therein sparse distribution at random the large tracts of land projection the zone and have the zone of the small size projection of dense distribution at random to have medium polishing velocity between maximal rate and the minimum speed therein; But, do not know which has higher initial burnishing speed, because polishing velocity depends on polishing solution and other parameter, comprise the systematicness of the distribution of projection, shape is arranged and the position.Because the protuberance of the rule during CMP handles in the pixel region 20 distributes, polishing solution may have the flow distribution of rule; Therefore need realize the method for similar flow distribution for non-pixel region.
In the chip size scope of reflective liquid crystal board substrate, because input terminal pad 26 is considered to maximum projection, and see sparsely from the angle that its one-dimensional array extends to distribute, comprise that therefore there is maximum polishing velocity in the zone of input terminal pad 26.Yet pixel region 20 has space periodicity in the matrix structure of uneven pixel graphics.As a result, pixel region 20 has classification (hierarchic) systematicness of the systematicness that comprises two varying levels, promptly in inhomogeneous pixel graphics the systematicness of the periodic higher level in space and in inhomogeneous pixel graphics more low-level systematicness.Inhomogeneous pixel graphics has hierarchical organization, comprises with width 1,000
Figure C20061010022100291
To 10,000 Distribution (two openings in field oxide film 3 of the various basic inhomogeneous parts (mainly), trickle represented of fine rule, the grid line 4 of end conductor layer, the data line 7 of the first metal layer, source electrode lead 7a, the barrier film 12 of the repeater electrode lead 10 and second metal level and jack 12a), and the inhomogeneous part (the second inhomogeneous part) that concentrates that causes by the scrambling of inhomogeneous substantially part in the pixel.Inhomogeneous analog pixel figure P imitation in the present embodiment includes only simulation grid line 4 P, analog data line 7 P, dummy source electrode 7a PWith analog junction lead 10 PThe inhomogeneous part that concentrates on a large scale, rather than basic inhomogeneous part.In the present embodiment, the inhomogeneous part of Nong Suoing is considered to the overlapping part of grid line 4 and data line 7 and the overlapping part of capacitance electrode 9a and relaying lead 10.Therefore, inhomogeneous analog pixel figure P preferably includes simulation grid line 4 P, analog data line 7 PAnd analog junction lead 10 PTypical inhomogeneous part can be used as the ingredient of inhomogeneous analog pixel electrode P.In inhomogeneous analog pixel figure P the position of typical inhomogeneous part do not need with actual pixel in the position of typical inhomogeneous part accurately corresponding.
Suppose that inhomogeneous pixel graphics has the 3rd or more hierarchy, then be necessary accurately to duplicate inhomogeneous substantially part, thus to second or the imitation of other inhomogeneous part of the third level enough useful.When the hierarchical organization in the inhomogeneous pixel graphics was not known, the inhomogeneous analog pixel figure P that accurately duplicates inhomogeneous substantially part had an advantage, promptly simplifies mask design.For the maximum ga(u)ge difference less than 1,000 Highly accurate planarization, best inhomogeneous analog pixel figure P is accurately duplicating of inhomogeneous substantially part.
The liquid crystal board substrate is applicable to the reflective liquid crystal board substrate in the present embodiment, and also can be used for the light valve of liquid crystal projector; Comprise wrist-watch shape electron device, the portable information processor of word processor and personal computer; And the display and other electron device that are used for mobile phone.
In the liquid crystal board substrate of present embodiment, on-off element is made on the first type surface of semiconductor chip.Also can use insulated substrate such as glass substrate and quartz base plate, replace semiconductor substrate.The present invention also can be used for the formation of thin film transistor (TFT) on insulating substrate as switching device.
In addition, the present invention can be used for the flat display board substrate except that the liquid crystal board substrate.
Advantage
As mentioned above, in the untapped space of pixel region, there is not formation model in the present invention Figure, and the model figure of the height of the top interlayer insulating film that will be polished for raising is By using the conductive layer that in whole non-pixel region, forms to form. If in pixel region The formation model figure then is the height that raises, and needs to be used for deposition intermediate conductive layer and interlayer insulation The extra deposition step of film. The surface elevation place of interlayer insulating film is suppressed before polishing The time, initial burnishing speed undesirably reduces, and the mirror planeization of interlayer insulating film needs long throwing Between the light time and a large amount of polishing solutions. The present invention can address this is that and have following advantage.
(1) when single or multiple lift model figure is set near terminal pads, at terminals Near the pad, the surface that the apparent height of top interlayer insulating film is substantially equal in the pixel region is high Degree. Because apparent height is level and smooth as a whole, therefore obtain all on whole surface Even polishing velocity. Therefore the present invention has improved the excessive polishing in the terminal pads part, this One problem not yet solves in the surface that the routine that inconsistent apparent height is arranged forms, and therefore exists Terminal pads is partly located bottom and can not exposed because of polishing. This advantage is in pixel region The mirror plane on surface is useful, and will be implemented in the before change of interlayer insulating film of polishing Thin. Attenuation has improved the aspect ratio of the contact hole of conduction interlayer in pixel region, and thereby follows Contact hole with small diameter can form the opening with small diameter. Therefore blanketing effect changes Kind, the result has improved switch element. Certainly, do not need extra film deposition step.
When the electrical conduction model figure was positioned near the terminal pads outside the pixel region, the model figure rose Therefore the effect of barrier film has prevented that veiling glare is from the pixel region outside invasion to on-chip pixel In the district, the result has suppressed photoelectric current and has flowed and improved switch element.
(2) near the model figure of arranging the input terminal pad is divided into the mould of a plurality of separations During the type figure, be right after after deposition, obtain the consistent apparent height of interlayer insulating film, and And can prevent two short circuits between the adjacent input terminal pad.
(3) when between two adjacent input terminal pads, non-model figure being set, two Short circuit between the individual adjacent input terminal pad can be prevented reliably.
(4) when input terminal pad and near the input terminal pad, arrange separation model Spacing between the figure is during greater than the spacing between near the model figure lead and the lead, input Hardly can be by in the anisotropic conductive film between the model figure of terminal pads and separation Conductive particle bridge joint appears, thereby can more effectively prevent short circuit.
(5) when relaying terminal pads and near trunk connection end pad, arrange separation model Spacing between the figure is during greater than the spacing between near the model figure lead and the lead, even Silver paste on the trunk connection end pad is expanded slightly, and this silver paste can not cause and the trunk connection end yet Although near the short circuit of the model figure the pad is normally with the silver paste on the trunk connection end pad Conduction is occurred.
(6) when near surrounding the seal area of pixel region, comprising terminal pads, illustraton of model being set During shape, the apparent height of interlayer insulating film is substantially equal to pixel region before the polishing of this zone Apparent height. Pixel region and its neighboring area are with uniform polishing velocity quilt in planarization Polishing. Like this, compare with conventional structure, pixel region flattens more satisfactorily or is flattened, The result has improved reflectivity, and determines easily the afterwards etching time of contact hole of polishing.
(7) have and be positioned on the seal area at the model figure of the peripheral part setting of seal area The apparent height that interlayer insulating film is same. Therefore is throwing on the surface of the interlayer insulating film in the seal area Do not have gradient after the light, and improved the adhesivity of encapsulant.
(8) the pilot layer that is formed on switch element of the model figure in seal area is positioned at In the time of on the isolated figure of same layer, can make the surface of interlayer insulating film can be more accurate by polishing Flatten or flattened.
(9) be formed on the periphery that is arranged at pixel region and provide to switch element when the model figure In the time of near the drive circuit of signal the zone, the model figure helps to be undertaken by polishing The complanation of interlayer insulating film.
(10) in the present invention, the model figure is formed on the bight of the seal area that surrounds pixel region Divide, and have than the limit part of seal area and the low density in neighboring area of angle part. Knot Really, there is roughness on unpolished interlayer insulating film surface, and this roughness reflects four jiaos of sealings The a plurality of inhomogeneous discrete model figure of part. Because with putting down of seal area in the glossing Slow protuberance side is compared, and four jiaos of hermetic units have bigger initial burnishing speed, by four jiaos Polishing velocity is substantially equal in the inner sealing district that hermetic unit surrounds. Therefore, pixel region and close The variation of residual thickness is suppressed in the envelope district.
(11) even when four jiaos of hermetic units do not have model figure (pattern density is zero), Than angular zone the more surface of the boundary member formation inclination of high altitude is arranged in the initial burnishing stage, and And the surface that tilts is expanded to interior location.
Therefore, generally speaking pixel region and seal area can flatten or be flattened.
(12) in the present invention, in non-pixel region, can form the many of the inhomogeneous pixel of imitation Individual inhomogeneous analog pixel figure, rather than form wide continuous smooth model figure. Because Zone except pixel region has basically identical with pixel region inhomogeneous figure, so from Starting stage begins substrate and just has uniform polishing velocity, and can high accuracy make pixel region Flatten or complanation with the surface of seal area.
(13) when along two-dimensional direction a plurality of inhomogeneous analog pixel figures being set at non-pixel region The time, non-pixel region has the Spatial Rules corresponding with matrix in the pixel region, thereby and advances one Step is improved the flatness on pixel region and seal area.
(14) when each analog pixel figure comprises simulation grid line and analog data line at least, Analog pixel figure and typical inhomogeneous pixel portion and pixel region are very similar, and can High accuracy flattens or complanation the interlayer insulating film in pixel region and the seal area.

Claims (4)

1. electro-optical device substrate, it is being arranged on the on-off element of corresponding each pixel in the on-chip pixel region, has the tunic structure that a plurality of interlayer insulating films and a plurality of conductive layer alternately form, at least one described interlayer insulating film flattens by polishing below the top conductive layer in these a plurality of conductive layers, it is characterized in that:
In described on-chip non-pixel region, have a plurality of inhomogeneous analog pixel figure that is included in through the described conductive layer below the described interlayer insulating film of described polishing,
Described inhomogeneous analog pixel figure is by 2 dimension directions repeat to form in described substrate upper edge.
2. an electro-optical device is characterized in that, a kind of electrooptical material be clipped in the described electro-optical device substrate of claim 1 and and its opposing transparent substrates between.
3. an electron device that comprises display device is characterized in that, uses the electro-optical device described in the claim 2.
4. a projection display apparatus that comprises light valve is characterized in that, uses the electro-optical device described in the claim 2.
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