CN100432967C - Method, equipment and computer system for communication between PCI equipments - Google Patents
Method, equipment and computer system for communication between PCI equipments Download PDFInfo
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- CN100432967C CN100432967C CNB2005100770835A CN200510077083A CN100432967C CN 100432967 C CN100432967 C CN 100432967C CN B2005100770835 A CNB2005100770835 A CN B2005100770835A CN 200510077083 A CN200510077083 A CN 200510077083A CN 100432967 C CN100432967 C CN 100432967C
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Abstract
The present invention relates to a method for the communication among PCI equipment, which is used for PCI main equipment without the I/O read-write capability to access to an I/O space of PCI target equipment. The method comprises the steps: (1) a PCI bus used for connecting the PCI main equipment and the PCI target equipment is hung with third PCI equipment having a memory space and I/O access capability, and the third PCI equipment at least stores the initial physical address of the I/O space of the PCI target equipment; (2) when the PCI main equipment accesses to the I/O space of the PCI target equipment, the third PCI equipment completes the mapping of the I/O space of the PCI target equipment and the memory space of the equipment; data corresponding to the physical address of the I/O space to be accessed in the PCI target equipment is read, the data is sent to the PCI main equipment, or data to be written is obtained from the PCI main equipment, and then, the data is written in the physical address of the I/O space to be accessed in the PCI target equipment. The present invention can be used for the PCI main equipment without the I/O read-write capability to access to the memory space of the PCI target equipment.
Description
Technical field
The present invention relates to computer system, relate in particular to communication and computer system thereof between PCI (the Peripheral Component Interconnect) equipment.
Background technology
The pci bus technology has extensive and ripe application in fields such as computing machine, data communication products.Have a large amount of chips all to support the pci bus agreement at present, they are being worked as the PCI equipment on the pci bus.In a PCI operation, the PCI equipment of initiating the PCI operation requests is the PCI main equipment, and accessed PCI equipment is the PCI target device.According to existing P CI bus specification, the configuration space of 6 sections is arranged at most in each PCI equipment.Those configuration spaces are storage space or input/output space according to chip self decision of PCI equipment.That is, existing P CI equipment can be provided with the storage space of 6 sections, also can be made of the configuration space of 6 sections storage space and input/output space.The physical address of realizing is to be distributed when powering on configuration by system, and be provided with by the configuration read-write.
The storage space of PCI equipment need be passed through the memory read/write command access, and the input/output space of PCI equipment need be by the visit of I/O read write command.Some PCI equipment can not be initiated the visit to input/output space because design reasons does not possess the ability that I/O reads and writes.In fact, whether PCI equipment possesses the I/O literacy is chip manufacturer's decision, has the PCI equipment that does not have the I/O literacy.And in a product, there is input/output space in other PCI equipment, and the PCI equipment that does not possess the I/O literacy need be visited the input/output space that there is the PCI equipment of input/output space in another one, and can't realize at present.Such as the PCI bridge device that links to each other with CPU,, just can't visit input/output space on the pci bus that is articulated in this PCI bridge at the software that moves on the CPU if it does not possess the I/O literacy.
That is to say, the input/output space that can not have the PCI equipment of input/output space in the prior art owing to the PCI that does not possess the I/O literacy as the main equipment visit, therefore bring a lot of inconveniences, even in order to visit the input/output space of PCI equipment with input/output space, the PCI main equipment that need more renew, cause the waste of former PCI main equipment thus, need to spend technician's extra work simultaneously.
Summary of the invention
The object of the present invention is to provide the method and apparatus that communicates between a kind of PCI equipment, to solve in the prior art owing to do not possess the input/output space that the PCI of I/O literacy can not have the PCI equipment of input/output space as the main equipment visit, therefore bring inconvenience, even in order to visit the input/output space of PCI equipment with input/output space, the PCI main equipment that need more renew, cause the waste of former PCI main equipment thus, need to spend the technical matters of technician's extra work simultaneously.
The object of the present invention is to provide a kind of computer system, with the main equipment that solves computer system in the prior art and target device can not direct communication technical matters.
For addressing the above problem, the invention discloses the method that communicates between a kind of PCI equipment, be used for not having of the visit of the PCI main equipment of I/O literacy to the input/output space of PCI target device, comprise: (1) articulates the 3rd a PCI equipment that has storage space and possess the I/O access ability on the pci bus that connects PCI main equipment and PCI target device, described the 3rd PCI equipment is stored the initial physical address of PCI target device input/output space at least; When (2) the PCI main equipment is visited the input/output space of PCI target device, the 3rd PCI equipment is finished the mapping of the storage space of the input/output space of PCI target device and this equipment: read data corresponding in the input/output space physical address to be visited from the PCI target device, and with described data back to the PCI main equipment, and/or from the PCI main equipment, obtain data to be written, more described data are write PCI target device input/output space physical address to be visited.
The 3rd PCI equipment comprises two block storage spaces, first storage space is used to preserve the initial physical address of input/output space of PCI target device and the input/output space size of preserving the PCI target device, and second storage space is used to realize the mapping of the storage space of the I/O address space of PCI target device and this PCI equipment.
Step (2) reads data corresponding in the input/output space physical address to be visited from the PCI target device, and described data back to PCI main equipment is specially: (11) are when the input/output space of PCI main equipment visit PCI target device, calculate the address start address of physical address=side-play amount+second storage space of visit, the input/output space address start address of the input/output space physical address-PCI target device of described side-play amount=to be visited; (12) the 3rd PCI equipment are initiated retry to the PCI main equipment and are stopped order, stop the transmission of data, and send the bus application to bus arbiter; (13) when receiving bus arbiter when allowing the 3rd PCI hold facility bus, the 3rd PCI equipment adds the I/O address of the reference address visit PCI target device that the initial physical address of the input/output space of PCI target device obtains, reading of data according to step (11) offset calculated; (14) the 3rd PCI equipment deposit the data that read in second block storage space; (15) the PCI main equipment sends the bus application to bus arbiter, and when bus arbiter allowed the PCI main equipment to take bus, the 3rd PCI equipment echo back data was to the PCI main equipment.
Step (2) obtains the data that write in advance from the PCI target device, described data being write PCI target device input/output space physical address to be visited is specially again: when (21) visit the input/output space of PCI target device when the PCI main equipment, directly the visit physical address to the 3rd PCI equipment writes data, the address start address of physical address=side-play amount+second storage space of visit, the input/output space address start address of the input/output space physical address-PCI target device of described side-play amount=to be visited; The data that (22) the 3rd PCI equipment are preserved physical address and write are sent the bus application to bus arbiter; (23) when receiving bus arbiter when allowing the 3rd PCI hold facility bus, the 3rd PCI equipment adds according to step (21) offset calculated and the I/O address of the reference address visit PCI target device that the initial physical address of the input/output space of PCI target device obtains writes data.
The invention discloses the method that communicates between second kind of PCI equipment, be used for not having of the visit of the PCI main equipment of memory read write capability to the storage space of PCI target device, (1) articulate the 3rd a PCI equipment that has input/output space and possess the memory access ability on the pci bus that connects PCI main equipment and PCI target device, described the 3rd PCI equipment is stored the initial physical address of PCI target device storage space at least; When (2) the PCI main equipment is visited the storage space of PCI target device, the 3rd PCI equipment is finished the storage space of PCI target device and the mapping of native system input/output space: read data corresponding in the storage space physical address to be visited from the PCI target device, and with described data back to the PCI main equipment, and/or from the PCI main equipment, obtain data to be written, more described data are write PCI target device storage space physical address to be visited.
The 3rd PCI equipment comprises two block I/O spaces at least, the first block I/O space is used to preserve the initial physical address of storage space of PCI target device and the storage space size of preserving the PCI target device at least, and the second block I/O space is used to realize the mapping of the input/output space of the memory address space of PCI target device and this PCI equipment.
Step (2) reads data corresponding in the storage space physical address to be visited from the PCI target device, and described data back to PCI main equipment is specially: (11) are when the storage space of PCI main equipment visit PCI target device, calculate the address start address in the physical address=side-play amount+second block I/O space of visit, the start address of the storage space address of the storage space physical address-PCI target device of described side-play amount=to be visited; (12) the 3rd PCI equipment are initiated retry to the PCI main equipment and are stopped order, stop the transmission of data, and send the bus application to bus arbiter; (13) when receiving bus arbiter when allowing the 3rd PCI hold facility bus, the 3rd PCI equipment adds the storage address of the reference address visit PCI target device that the initial physical address of the storage space of PCI target device obtains, reading of data according to step (11) offset calculated; (14) the 3rd PCI equipment deposit the data that read in second block I/O space; (15) the PCI main equipment sends the bus application to bus arbiter, and when bus arbiter allowed the PCI main equipment to take bus, the 3rd PCI equipment echo back data was to the PCI main equipment.
Step (2) obtains the data that write in advance from the PCI target device, described data being write PCI target device storage space physical address to be visited is specially again: when (21) visit the storage space of PCI target device when the PCI main equipment, directly the visit physical address to the 3rd PCI equipment writes data, the address start address of physical address=side-play amount+second storage space of visit, the storage space address start address of the storage space physical address-PCI target device of described side-play amount=to be visited; The data that (22) the 3rd PCI equipment are preserved physical address and write are sent the bus application to bus arbiter; (23) when receiving bus arbiter when allowing the 3rd PCI hold facility bus, the 3rd PCI equipment adds according to step (21) offset calculated and the storage address of the reference address visit PCI target device that the initial physical address of the storage space of PCI target device obtains writes data.
The invention discloses the method that communicates between the third PCI equipment, the PCI main equipment is connected by bus bridge with the PCI target device, certain section or the visit of a few segment memory address spaces with main bridge one side are transformed into from the visit in the I/O address space of bridge.
A kind of computer system comprises: main equipment, can initiate read-write operation at least one target device by bus;
Target device, it has main equipment can't be by the address space of the direct visit of bus; It is characterized in that, also comprise:
The 3rd equipment, it has main equipment can pass through the directly address space of visit of bus, and has the literacy by the address space of bus access target device;
The 3rd equipment is mapped to the address space of described target device on self the address space for described main equipment visit.
The PCI main equipment of described main equipment for not having the I/O literacy, described target device is the PCI target device with input/output space, described the 3rd equipment is the PCI equipment that has storage space and possess the I/O access ability, perhaps described main equipment is not for having the PCI main equipment of memory read write capability, described target device is the PCI target device with storage space, and described the 3rd equipment is the PCI equipment that has input/output space and possess the memory access ability.
Described the 3rd hanging equipment is connected on the bus of main equipment and target device.
Described the 3rd equipment is for connecting the bus bridge of main equipment and target device.
Compared with prior art, the present invention has the following advantages: the present invention is by articulating one the 3rd PCI equipment or a bus bridge being set on the pci bus of PCI main equipment and PCI target device, the PCI main equipment is finished and is anyly all needed to set up transfer by the 3rd PCI equipment/bus bridge during once to the visit of PCI target device: the Memory space that the input/output space of PCI equipment is mapped to system, or the Memory spatial mappings of PCI equipment is to the method for the input/output space of system, solve the PCI main equipment that do not possess the I/O literacy to the problem of other PCI target device input/output spaces visits with do not possess the technical matters of the PCI main equipment of Memory literacy to the Memory space access of PCI target device.
The present invention also discloses and a kind ofly can make the computer system that communicates between main equipment and the target device.
Description of drawings
Fig. 1 is a schematic diagram of the equipment that communicates between the PCI equipment;
Fig. 2 is the exemplifying embodiment process flow diagram that communicates between the PCI equipment of Fig. 1;
Fig. 3 is another schematic diagram of the method that communicates between the PCI equipment;
Fig. 4 is second schematic diagram that communicates between the PCI equipment;
Fig. 5 is the second enforcement schematic diagram that communicates between the PCI equipment;
Fig. 6 is a computer system synoptic diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, specify the present invention.
See also Fig. 1, it is a schematic diagram of the equipment that communicates between the PCI equipment.The equipment that communicates between a kind of PCI equipment, be used for not having of the visit of the PCI main equipment of I/O literacy to the input/output space of PCI target device, on the pci bus that connects PCI main equipment and PCI target device, articulate the 3rd a PCI equipment that has storage space and possess the I/O access ability, when the PCI main equipment is visited the input/output space of PCI target device, finish the mapping of the storage space of the input/output space of PCI target device and this equipment: from the PCI target device, read data corresponding in the input/output space physical address to be visited, and with described data back to the PCI main equipment, and/or from the PCI main equipment, obtain data to be written, more described data are write PCI target device input/output space physical address to be visited.
Articulate the 3rd PCI equipment at main equipment and target device.The 3rd PCI equipment is used for finishing the mapping of the input/output space of PCI target device to system Memory space.The 3rd PCI equipment is for having Memory space PCI target device, and promptly the PCI main equipment on the pci bus can be initiated the read-write operation to its Memory space; The 3rd PCI equipment should possess the main equipment of initiating the I/O access ability simultaneously, can visit the PCI target device, and described PCI target device is the PCI equipment that has input/output space in the accompanying drawing 1.In brief, the PCI main equipment visit that possesses Memory (storer) access ability has the PCI equipment of input/output space, finishes its visit by " transfer " of the 3rd PCI equipment.
Setting up the PCI main equipment do not have the I/O literacy need may further comprise the steps the visit of the input/output space of PCI target device:
(1) articulate the 3rd a PCI equipment that has storage space and possess the I/O access ability on the pci bus that connects PCI main equipment and PCI target device, described the 3rd PCI equipment is stored the initial physical address of PCI target device input/output space at least;
When (2) the PCI main equipment is visited the input/output space of PCI target device, the 3rd PCI equipment is finished the mapping of the storage space of the input/output space of PCI target device and this equipment: read data corresponding in the input/output space physical address to be visited from the PCI target device, and with described data back to the PCI main equipment, and/or from the PCI main equipment, obtain data to be written, more described data are write PCI target device input/output space physical address to be visited.
Following mask body is introduced each step.
The 3rd PCI equipment is stored the initial physical address of PCI target device input/output space at least.When PCI main equipment (the PCI equipment that possesses the Memory access ability) visit PCI target device (the PCI equipment that has input/output space), PCI equipment can write data in the input/output space to be visited according to the initial physical address of the PCI target device input/output space of storing, and data are read from input/output space to be visited.
Such as: the 3rd PCI equipment comprises two block storage spaces, and the first block storage space is used to preserve the initial physical address of input/output space of PCI target device and the input/output space size of preserving the PCI target device,
Second storage space is used to realize the mapping of the storage space of the I/O address space of PCI target device and this PCI equipment.The 3rd PCI equipment also can comprise two block storage spaces, this part storage space is used to preserve the initial physical address of input/output space of PCI target device and the input/output space size of preserving the PCI target device, and the mapping that realizes the storage space of the I/O address space of PCI target device and this PCI equipment.The piece number of storage space does not influence follow-up communication process, below comprises that with the 3rd PCI equipment two block storage spaces are example, and concrete communication process is described.
Step (2) reads data corresponding in the input/output space physical address to be visited from the PCI target device, and described data back to PCI main equipment is specially:
(11) when the PCI main equipment is visited the input/output space of PCI target device, calculate the address start address of physical address=side-play amount+second storage space of visit, described side-play amount is the input/output space address start address of input/output space physical address one PCI target device to be visited;
(12) the 3rd PCI equipment are initiated retry to the PCI main equipment and are stopped order, stop the transmission of data, and send the bus application to bus arbiter;
(13) when receiving bus arbiter when allowing the 3rd PCI hold facility bus, the 3rd PCI equipment adds the I/O address of the reference address visit PCI target device that the initial physical address of the input/output space of PCI target device obtains, reading of data according to step (11) offset calculated;
(14) the 3rd PCI equipment deposit the data that read in second block storage space;
(15) the PCI main equipment sends the bus application to bus arbiter, and when bus arbiter allowed the PCI main equipment to take bus, the 3rd PCI equipment echo back data was to the PCI main equipment.
Step (2) obtains the data that write in advance from the PCI main equipment, more described data are write PCI target device input/output space physical address to be visited and be specially:
(21) when the PCI main equipment is visited the input/output space of PCI target device, directly the visit physical address to the 3rd PCI equipment writes data, the address start address of physical address=side-play amount+second storage space of visit, the input/output space address start address of the input/output space physical address-PCI target device of described side-play amount=to be visited;
The data that (22) the 3rd PCI equipment are preserved physical address and write are sent the bus application to bus arbiter;
(23) when receiving bus arbiter when allowing the 3rd PCI hold facility bus, the 3rd PCI equipment adds according to step (21) offset calculated and the I/O address of the reference address visit PCI target device that the initial physical address of the input/output space of PCI target device obtains writes data.
Below in conjunction with the power on action of back system software of pci system, specify a specific embodiment of such scheme.The following system software of mentioning is initiated the program of accord with PCI Specification operation for ordering a PCI equipment (a PCI equipment is the PCI main equipment that possesses the Memory access ability, and the 2nd PCI equipment is the PCI target device that has input/output space).For example, a PCI equipment is a microprocessor that possesses pci bus, and system software is the program that runs on this CPU.
The 3rd PCI equipment should be realized two Memory spaces, for example Bar0 and Bar1 at least.Be provided with two 32/64 register in Bar0, an initial physical address that is used to preserve the input/output space of PCI the 2nd PCI equipment is designated as IOBaseAddres_Reg herein; Another is used for the size that saved system is distributed to the input/output space of the 2nd PCI equipment, is designated as Long_Reg herein.For 32 pci system, IOBaseAddres_Reg, Long_Reg should be 32, should be 64 for 64 pci system IOBaseAddres_Reg, Long_Reg.Bar1 is used to the mapping of the I/O address space of the 2nd PCI equipment of realizing to the Memory space of system, so the size of Bar1 should be not less than the input/output space size sum of the 2nd PCI equipment.
At the beginning of communicating between the one PCI equipment and the 2nd PCI equipment, at first need to carry out initial work and data are write in the corresponding space.Such as:
After system software recognizes the 2nd PCI equipment and the 3rd PCI equipment by supplier ID and device id, utilize " configurable write operation " to give the 2nd PCI equipment, the 3rd PCI devices allocation input/output space physical address and Memory space physics address respectively respectively, and initialization is carried out in those addresses.For example, should finish the initialization of Bar0 base address pointer register, Bar1 base address pointer register for the 3rd PCI equipment.
System software writes the input/output space start address of the 2nd PCI equipment respectively and distributes to the 2nd PCI equipment by " Memory writes " order among IOBaseAddres_Reg, the Long_Reg in the Bar0 of the 3rd PCI equipment input/output space is size always.
When a PCI equipment need send the data of the corresponding input/output space that read command reads the 2nd PCI equipment, then concrete communication steps (seeing also Fig. 2) as follows:
S11: a PCI equipment sends to the pci bus arbiter device and takies bus line command;
S12: when obtaining the permission of pci bus arbiter device, read the Bar1 offset address, carry out the calculating of physical address: input/output space physical address to be visited is with respect to the offset address of the base address, input/output space address (being the value of IOBaseAddres_Reg) of the 2nd PCI equipment, add the base address, address of the Bar1 of the 3rd PCI equipment, be the actual physical address.
Such as: for example the base address, Memory address of the Bar1 of the 3rd PCI equipment is 0X80010000, the I/O address base address of the 2nd PCI equipment is 0X00001000, will visit then that I/O address is the unit of 0X0000100C on the 2nd PCI equipment, its Memory address that will visit is 0x8001000C.
S13: when the 3rd PCI equipment is initiated this read access at a PCI equipment, send " retry termination " to a PCI equipment, stop the transmission of data, preserve address (as 0x8001000C) in the address phase of operation simultaneously, and send bus application (S14) to bus arbiter immediately.
S15: the 3rd PCI equipment calculates corresponding offset according to the address 0x8001000C that preserves and is " 0x000C ", and add that " IOBASEADDRESS_Reg " obtains I/O address space address 0x0000100C to be read, when bus arbiter allows the 3rd PCI hold facility bus, the 3rd PCI equipment sends " I/O read operation " immediately, operation address is 0x00001000C, reading of data from the 2nd PCI equipment.
S16: owing to what the 3rd PCI equipment sent when step a2 is " retry termination ", and a PCI equipment can be initiated the bus application to moderator once more after the REQ that experiences at least 2 cycles is invalid;
S17: if moderator allows a PCI hold facility bus, then a PCI equipment can be initiated the read operation to the 0x8001000C address of the 3rd PCI equipment once more.For this read operation, it is effective that the 3rd PCI equipment determines the data of reading from the 0x00001000C address, so can be to these data of PCI equipment loopback, PCI equipment fair termination after the read operation of finishing one-period.So far, finished the read operation of a PCI equipment to the I/O address space of the 2nd PCI equipment.
When a PCI equipment need send write order and writes the corresponding input/output space of data to the two PCI equipment, then concrete communication steps (seeing also Fig. 3) as follows, then:
S21: a PCI equipment sends to the pci bus arbiter device and takies bus line command;
S22: when obtaining the permission of pci bus arbiter device, write data to the Bar1 offset address, carry out the calculating of physical address: input/output space physical address to be visited is with respect to the offset address of the base address, input/output space address (being the value of IOBaseAddres Reg) of the 2nd PCI equipment, add the base address, address of the Bar1 of the 3rd PCI equipment, be the actual physical address.
S23: when the 3rd PCI equipment is initiated this write access at a PCI equipment, preserve the address that writes, preserve the data that write in the data phase, and send the bus application to bus arbiter immediately in the address phase
S24: when bus arbiter allowed the 3rd PCI hold facility bus, the 3rd PCI equipment sent " I/O write operation " immediately, the address that operation address is preserved for the b1 step, the data that data to be written are preserved for step b1.Finish the action that the input/output space to the 2nd PCI equipment writes.
Can visit the PCI equipment that has input/output space except the PCI main equipment of the above-mentioned disclosed Memory of possessing access ability, the invention also discloses a kind of method of the PCI main equipment of memory read write capability that realize not having the visit of the storage space of PCI target device.
See also Fig. 4, its equipment schematic for communicating between the another kind of PCI equipment of the present invention.The equipment that communicates between a kind of PCI equipment, be used for not having of the visit of the PCI main equipment of I/O literacy to the input/output space of PCI target device, on the pci bus that connects PCI main equipment and PCI target device, articulate the 3rd a PCI equipment that has storage space and possess the I/O access ability, when the PCI main equipment is visited the input/output space of PCI target device, finish the mapping of the storage space of the input/output space of PCI target device and this equipment: from the PCI target device, read data corresponding in the input/output space physical address to be visited, and with described data back to the PCI main equipment, and/or from the PCI main equipment, obtain data to be written, more described data are write PCI target device input/output space physical address to be visited.
The present invention also provides the method that communicates between a kind of PCI equipment, is used for not having the visit of the PCI main equipment of memory read write capability to the storage space of PCI target device, comprising:
(1) articulate the 3rd a PCI equipment that has input/output space and possess the memory access ability on the pci bus that connects PCI main equipment and PCI target device, described the 3rd PCI equipment is stored the initial physical address of PCI target device storage space at least;
When (2) the PCI main equipment is visited the storage space of PCI target device, the 3rd PCI equipment is finished the storage space of PCI target device and the mapping of native system input/output space: read data corresponding in the storage space physical address to be visited from the PCI target device, and with described data back to the PCI main equipment, and/or from the PCI main equipment, obtain data to be written, more described data are write PCI target device storage space physical address to be visited.
The 3rd PCI equipment comprises two block I/O spaces, the first block I/O space is used to preserve the initial physical address of storage space of PCI target device and the storage space size of preserving the PCI target device at least, and the second block I/O space is used to realize the mapping of the input/output space of the memory address space of PCI target device and this PCI equipment.
Step (2) reads data corresponding in the storage space physical address to be visited from the PCI target device, and described data back to PCI main equipment is specially:
(11) when the PCI main equipment is visited the storage space of PCI target device, calculate the address start address in the physical address=side-play amount+second block I/O space of visit, the start address of the storage space address of the storage space physical address-PCI target device of described side-play amount=to be visited;
(12) the 3rd PCI equipment are initiated retry to the PCI main equipment and are stopped order, stop the transmission of data, and send the bus application to bus arbiter;
(13) when receiving bus arbiter when allowing the 3rd PCI hold facility bus, the 3rd PCI equipment adds the storage address of the reference address visit PCI target device that the initial physical address of the storage space of PCI target device obtains, reading of data according to step (11) offset calculated;
(14) the 3rd PCI equipment deposit the data that read in second block I/O space;
(15) the PCI main equipment sends the bus application to bus arbiter, and when bus arbiter allowed the PCI main equipment to take bus, the 3rd PCI equipment echo back data was to the PCI main equipment.
Step (2) obtains the data that write in advance from the PCI target device, more described data are write PCI target device storage space physical address to be visited and be specially:
(21) when the PCI main equipment is visited the storage space of PCI target device, directly the visit physical address to the 3rd PCI equipment writes data, the address start address of physical address=side-play amount+second storage space of visit, the storage space address start address of the storage space physical address-PCI target device of described side-play amount=to be visited;
The data that (22) the 3rd PCI equipment are preserved physical address and write are sent the bus application to bus arbiter;
(23) when receiving bus arbiter when allowing the 3rd PCI hold facility bus, the 3rd PCI equipment adds according to step (21) offset calculated and the storage address of the reference address visit PCI target device that the initial physical address of the storage space of PCI target device obtains writes data.
The invention also discloses the bus bridge that utilizes PCI-To-PCI and replace the 3rd above-mentioned PCI equipment, finish mutual method for communicating (seeing also Fig. 5) between the PCI equipment.The PCI main equipment is connected by bus bridge with the PCI target device, certain section or the visit of a few segment memory address spaces with main bridge one side, be transformed into from the visit in the I/O address space of bridge, make the PCI main equipment that does not have the I/O literacy have access ability to the input/output space of PCI target device, perhaps, make PCI main equipment have access ability to the storage space of PCI target device with memory read write capability.
On broad sense, bus bridge also is a kind of PCI equipment, so the method that communicates between the PCI equipment that provides of this programme is identical with aforementioned two disclosed principles of scheme, repeats no more.
In computer system, industry has many kinds of bus specifications, more than above-mentioned two kinds of operating position of the present invention, and for example the PCI-X standard also is applicable to the present invention.Based on design of the present invention, adopt the mode of other buses the industry those of ordinary skill to be expected easily to realize more embodiment.Thereby, see also Fig. 6 with a kind of embodiment that the present invention sums up, it is the structural representation of a kind of computer system of the present invention, comprising:
Main equipment 21 can be initiated read-write operation at least one target device 23 by bus;
Target device 23, it has main equipment 21 can't be by the address space of the direct visit of bus;
The 3rd equipment 22, it has main equipment 21 can pass through the directly address space of visit of bus, and has the literacy by the address space of bus access target device 23;
The 3rd equipment 22 is mapped to the address space of described target device 23 on self the address space for described main equipment 21 visits.
The PCI main equipment of described main equipment 21 for not having the I/O literacy, described target device 23 is for having the PCI target device of input/output space, and described the 3rd equipment 22 is the PCI equipment that has storage space and possess the I/O access ability, perhaps
Described main equipment 21 is not for having the PCI main equipment of memory read write capability, and described target device 23 is the PCI target device with storage space, and described the 3rd equipment 22 is the PCI equipment that has input/output space and possess the memory access ability.
Described the 3rd equipment 22 is articulated on the bus of main equipment and target device.Described the 3rd equipment 22 can be for connecting the bus bridge of main equipment and target device.
Only more than discloses and to be several specific embodiments of the present invention, but the present invention is not limited thereto, any those skilled in the art can think variation all should drop in protection scope of the present invention.
Claims (12)
1, the method that communicates between a kind of PCI equipment is used for not having the visit of the PCI main equipment of I/O literacy to the input/output space of PCI target device, it is characterized in that, comprising:
(1) articulate the 3rd a PCI equipment that has storage space and possess the I/O access ability on the pci bus that connects PCI main equipment and PCI target device, described the 3rd PCI equipment is stored the initial physical address of PCI target device input/output space at least;
When (2) the PCI main equipment is visited the input/output space of PCI target device, the 3rd PCI equipment is finished the mapping of the storage space of the input/output space of PCI target device and this equipment: read data corresponding in the input/output space physical address to be visited from the PCI target device, and with described data back to the PCI main equipment, and/or from the PCI main equipment, obtain data to be written, more described data are write PCI target device input/output space physical address to be visited.
2, the method that communicates between the PCI equipment as claimed in claim 1, it is characterized in that, the 3rd PCI equipment comprises two block storage spaces, first storage space is used to preserve the initial physical address of input/output space of PCI target device and the input/output space size of preserving the PCI target device, and second storage space is used to realize the mapping of the storage space of the I/O address space of PCI target device and this PCI equipment.
3, the method that communicates between the PCI equipment as claimed in claim 2 is characterized in that, step (2) reads data corresponding in the input/output space physical address to be visited from the PCI target device, and described data back to PCI main equipment is specially:
(11) when the PCI main equipment is visited the input/output space of PCI target device, calculate the address start address of physical address=side-play amount+second storage space of visit, described side-play amount is the input/output space address start address of input/output space physical address-PCI target device to be visited;
(12) the 3rd PCI equipment are initiated retry to the PCI main equipment and are stopped order, stop the transmission of data, and send the bus application to bus arbiter;
(13) when receiving bus arbiter when allowing the 3rd PCI hold facility bus, the 3rd PCI equipment adds the I/O address of the reference address visit PCI target device that the initial physical address of the input/output space of PCI target device obtains, reading of data according to step (11) offset calculated;
(14) the 3rd PCI equipment deposit the data that read in second block storage space;
(15) the PCI main equipment sends the bus application to bus arbiter, and when bus arbiter allowed the PCI main equipment to take bus, the 3rd PCI equipment echo back data was to the PCI main equipment.
4, the method that communicates between the PCI equipment as claimed in claim 2 is characterized in that, step (2) obtains the data that write in advance from the PCI main equipment, more described data are write PCI target device input/output space physical address to be visited and be specially:
(21) when the PCI main equipment is visited the input/output space of PCI target device, directly the visit physical address to the 3rd PCI equipment writes data, the address start address of physical address=side-play amount+second storage space of visit, the input/output space address start address of the input/output space physical address-PCI target device of described side-play amount=to be visited;
The data that (22) the 3rd PCI equipment are preserved physical address and write are sent the bus application to bus arbiter;
(23) when receiving bus arbiter when allowing the 3rd PCI hold facility bus, the 3rd PCI equipment adds according to step (21) offset calculated and the I/O address of the reference address visit PCI target device that the initial physical address of the input/output space of PCI target device obtains writes data.
5, the equipment that communicates between a kind of PCI equipment is used for not having the visit of the PCI main equipment of I/O literacy to the input/output space of PCI target device, it is characterized in that,
Described hanging equipment is connected on the pci bus that is connected with PCI main equipment and PCI target device, described equipment is the PCI equipment that has storage space and possess the I/O access ability, described equipment is stored the initial physical address of PCI target device input/output space at least, when the PCI main equipment is visited the input/output space of PCI target device, finish the mapping of the storage space of the input/output space of PCI target device and this equipment: from the PCI target device, read data corresponding in the input/output space physical address to be visited, and with described data back to the PCI main equipment, and/or from the PCI main equipment, obtain data to be written, more described data are write PCI target device input/output space physical address to be visited.
6, the method that communicates between a kind of PCI equipment is used for not having the visit of the PCI main equipment of memory read write capability to the storage space of PCI target device, it is characterized in that,
(1) articulate the 3rd a PCI equipment that has input/output space and possess the memory access ability on the pci bus that connects PCI main equipment and PCI target device, described the 3rd PCI equipment is stored the initial physical address of PCI target device storage space at least;
When (2) the PCI main equipment is visited the storage space of PCI target device, the 3rd PCI equipment is finished the storage space of PCI target device and the mapping of native system input/output space: read data corresponding in the storage space physical address to be visited from the PCI target device, and with described data back to the PCI main equipment, and/or from the PCI main equipment, obtain data to be written, more described data are write PCI target device storage space physical address to be visited.
7, the method that communicates between the PCI equipment as claimed in claim 6, it is characterized in that, the 3rd PCI equipment comprises two block I/O spaces at least, the first block I/O space is used to preserve the initial physical address of storage space of PCI target device and the storage space size of preserving the PCI target device at least, and the second block I/O space is used to realize the mapping of the input/output space of the memory address space of PCI target device and this PCI equipment.
8, the equipment that communicates between a kind of PCI equipment, be used for not having of the visit of the PCI main equipment of memory read write capability to the storage space of PCI target device, it is characterized in that, described hanging equipment is connected on the pci bus that is connected with PCI main equipment and PCI target device, described equipment is the PCI equipment that has input/output space and possess the memory access ability, described equipment is stored the initial physical address of PCI target device storage space at least, when the PCI main equipment is visited the storage space of PCI target device, described equipment is in order to the storage space of finishing the PCI target device and the mapping of native system input/output space: read data corresponding in the storage space physical address to be visited from the PCI target device, and with described data back to the PCI main equipment, and/or from the PCI main equipment, obtain data to be written, more described data are write PCI target device storage space physical address to be visited.
9. computer system comprises: the PCI main equipment, can initiate read-write operation at least one PCI target device by bus;
The PCI target device, it has the PCI main equipment can't be by the address space of the direct visit of bus; It is characterized in that, also comprise:
PCI the 3rd equipment, it has the PCI main equipment can pass through the directly address space of visit of bus, and has the literacy by the address space of bus access PCI target device;
PCI the 3rd equipment is mapped to the address space of described PCI target device on self the address space for described PCI main equipment visit.
10, computer system as claimed in claim 9, it is characterized in that, the PCI main equipment of described PCI main equipment for not having the I/O literacy, described PCI target device is the PCI target device with input/output space, described PCI the 3rd equipment is the PCI equipment that has storage space and possess the I/O access ability, perhaps
Described PCI main equipment is not for having the PCI main equipment of memory read write capability, and described PCI target device is the PCI target device with storage space, and described PCI the 3rd equipment is the PCI equipment that has input/output space and possess the memory access ability.
11, computer system as claimed in claim 9 is characterized in that, described PCI the 3rd hanging equipment is connected on the bus of PCI main equipment and PCI target device.
12, computer system as claimed in claim 9 is characterized in that, described PCI the 3rd equipment is for connecting the bus bridge of PCI main equipment and PCI target device.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100770835A CN100432967C (en) | 2005-06-15 | 2005-06-15 | Method, equipment and computer system for communication between PCI equipments |
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| CNB2005100770835A CN100432967C (en) | 2005-06-15 | 2005-06-15 | Method, equipment and computer system for communication between PCI equipments |
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| EP2182444A4 (en) * | 2007-08-24 | 2011-04-27 | Fujitsu Ltd | Method for restraining requirements for i/o space of pci device |
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| CN1206879A (en) * | 1997-07-25 | 1999-02-03 | 三星电子株式会社 | Interconnection bridge for external parts |
| CN1529256A (en) * | 2003-10-17 | 2004-09-15 | 中兴通讯股份有限公司 | Dual-ring quene-based, non-interrupt PCI communication method |
| CN1556642A (en) * | 2003-12-31 | 2004-12-22 | 中兴通讯股份有限公司 | Device and method of data pocket retransmission between POS-PHY bus and PCI bus |
| CN1564147A (en) * | 2004-03-31 | 2005-01-12 | 港湾网络有限公司 | Double CPU communication systems based on PCI shared memory |
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|---|---|---|---|---|
| CN1206879A (en) * | 1997-07-25 | 1999-02-03 | 三星电子株式会社 | Interconnection bridge for external parts |
| CN1529256A (en) * | 2003-10-17 | 2004-09-15 | 中兴通讯股份有限公司 | Dual-ring quene-based, non-interrupt PCI communication method |
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| CN1564147A (en) * | 2004-03-31 | 2005-01-12 | 港湾网络有限公司 | Double CPU communication systems based on PCI shared memory |
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