CN100432695C - Integrated measuring systme for radar receiver - Google Patents

Abstract

The present invention discloses a radar receiver parameter test device which comprises a computer, an instrument set, a data collection and storage device and a receiver state controller, wherein test instruments in the instrument set are respectively connected with an interface card of the computer. The data collection and storage device comprises a plurality of long wire receiver sets, and each long wire receiver set is connected with a receiver of measured radars through a test passageway, wherein a part of the long wire receiver sets are connected with a datum communication card of the computer through a register and a memory, and a part of the long wire receiver sets are connected with the data communication card of the computer through a register, a logic circuit and a single chip computer. In the receiver state controller, the measured radars are orderly connected with a PC serial port, an electric level translator and the single chip computer, and are grouped to be connected with a control panel, signal source and a long wire transmitter. Because various instruments, the computer data collection and storage device and the receiver state controller are combined, the automatic test of various parameters of a radar receiver is achieved, and the present invention has the advantages of equipment capacity reduction, time saving and efficiency increasing.

Description

Integrated measuring systme for radar receiver

One, technical field

The present invention relates to a kind of radar receiver parameter test device, particularly a kind of integrated measuring systme for radar receiver.

Two, background technology

Radar receiver is an important component part in the radar system, and target echo signal mixing, filtering, amplification, signal Processing that it receives radar antenna are extracted useful signal.The radar receiver parameter testing is radar receiver requisite step in production, use, maintenance process, US Patent specification US5952834 discloses a kind of ATE (automatic test equipment) that is used to test electric signal and analyzes electric signal, communication system, radar system and other signal generating apparatus noise component, and it is mainly used in the noise component of test receiver; A kind of radar receiver noise figure testing apparatus is disclosed in " research of Radar Receiver Noise Coefficient Measuring Instrument and design " literary composition of delivering on 57 pages of the magazines of publishing September calendar year 2001 " computer automatic analysis and control ", it is a platform with PC virtual instrument card+military industrial computer, can finish test to multiple radar receiver noise figure, and provided the software expression that realizes test automatically, be mainly used in the noise figure of test receiver; It is mutually inconsistent that technology that " computer-aided test of Modern Radar Receiver channel characteristic " literary composition is introduced in the magazine of publishing in May, 1997 " modern radar " is mainly used between the amplitude phase error of I, Q component in the passage of test receiver and each receiving cable width of cloth; In the master thesis that the old Kong Ming of Northwestern Polytechnical University writes " virtual instrument technique and the application in the airborne radar test thereof ", though the technology of introducing is a test macro with a plurality of test functions, but this technology is mainly based on vxi bus, the radar of test mainly is an airborne radar, and technology that " pulsed radar receiver intelligence test equipment " literary composition is introduced in " the academic meeting of Chinese cosmonautics meeting collection of thesis " is mainly used in the carrier signal parameter of test receiver.Hence one can see that, the testing apparatus of present every radar receiver parameter is generally all independent to be used, by a certain or several parameters of instruments such as vector voltmeter, noise measuring set, frequency spectrograph, power oscillograph difference test receiver, test event is single, and mostly is manual operations.

Three, summary of the invention

1, goal of the invention: the purpose of this invention is to provide a kind of integrated measuring systme for radar receiver, can carry out the automatic Synthesis test to the multiple parameter of radar receiver.

2, technical scheme: the present invention is a kind of integrated measuring systme for radar receiver, comprise instrument group, data acquisition memory storage, receiver state control device and computing machine, wherein, in the instrument group each testing tool respectively with computing machine on GPIB (general purpose interface bus) card connection; The data acquisition memory storage comprises a plurality of line receiver group exclusive data acquisition and storage devices, and the data acquisition memory storage comprises line receiver group 1-6, and each line receiver group is connected with tested radar receiver by test channel; Among the first line receiver group 1-3, each line receiver group is successively through a registers group, each registers group comprises one 64 first register 1 or 2,3 and one 32 second register 5 or 6,7, three second registers select 1 device and the 3rd register 9 through 3 successively, the 3rd register 9 is connected to first memory 1 respectively, the data communication card connection of the 2 and the 4th register 13, the four registers 13 and computing machine; The second line receiver group 4 is connected with the 6th register 8 of 32 of two-stages through one 64 the 5th register 4; The 6th register 8 is connected with the 7th register 14 with second memory 3,4 respectively, the data communication card connection of the 7th register 14 and computing machine; One group of the output signal of the 3rd line receiver group 5 is changeed through first string and shift register, the 8th register 11 connect with first memory 1,2, and another group signal changes through second string and shift register, the 9th register 12 connect with second memory 3,4; The 4th line receiver group 6 is connected with single-chip microcomputer through the tenth register 10, logical circuit, the data communication card connection of single-chip microcomputer and computing machine; Long line transmitter is connected with logical circuit; In the receiver state control device, the control routine that computing machine produces transfers to single-chip microcomputer through PC serial ports, level translator successively, after single-chip microcomputer is handled, one group of signal is given first registers group 1, control signal selects 1 allocate memory group to deposit the space through 16, the content of first registers group 1 shows on the radar duty demonstration charactron of controller, the state of a control that another group signal removes the control radar receiver through 2 outputs of second registers group.

3, beneficial effect: the present invention combines multiple instrument, computing machine and data acquisition memory storage, receiver state control device, in test process, carry out program control to radar receiver duty, testing tool, realized automatic test to the multiple performance of radar receiver, index parameter, thereby reduced the volume of testing apparatus, save the running time, improved work efficiency.

Four, description of drawings

Fig. 1 is a radar receiver Integrated Measurement System block diagram.

Fig. 2 is a radar receiver behavior control device The general frame.

Fig. 3 is the data acquisition system (DAS) The general frame.

Fig. 4 is the circuit block diagram of string commentaries on classics and 1, register 11.

Fig. 5 is the sequential chart of circuit shown in Figure 4.

Fig. 6 is a logic circuit diagram.

Fig. 7 is the dynamic range synoptic diagram.

Fig. 8 is that log characteristic is analyzed synoptic diagram.

Five, embodiment

Integrated measuring systme for radar receiver as shown in Figure 1, it comprises computing machine, instrument group, data acquisition memory storage and receiver state control device, wherein, the instrument group comprises vector voltmeter, noise measuring set, frequency spectrograph, power oscillograph, and each testing tool and signal source are by the gpib interface card connection of bus and computing machine.

The receiver state control device as shown in Figure 2.Computing machine produces control routine and transfers to single-chip microcomputer through PC serial ports, level translator successively, and after single-chip microcomputer was handled, one group of signal showed the radar receiver duty through first registers group 1.Another group signal is through second registers group, 2 control radar operation of receiver states.

The exclusive data acquisition and storage device as shown in Figure 3, the data acquisition memory storage comprises line receiver group 1-6, each line receiver group is connected with tested radar receiver by test channel.Among the first line receiver group 1-3, each line receiver group is successively through a registers group, each registers group comprises one 64 first registers 1 or 2 or 3 and one 32 second registers 5 or 6 or 7, three second registers 5,6,7 select the 1 and the 3rd register 9 through 3 successively, the 3rd register 9 is connected to first memory 1 respectively, the data communication card connection of the 2 and the 4th register 13, the four registers 13 and computing machine; The second line receiver group 4 is connected with the 6th register 8 of 32 of two-stages through one 64 the 5th register 4; The 6th register 8 is connected with the 7th register 14 with second memory 3,4 respectively, the data communication card connection of the 7th register 14 and computing machine; One group of the output signal of the 3rd line receiver group 5 is changeed through first string and shift register 1, the 8th register 11 connect with first memory 1,2, and another group signal changes through second string and the 2, the 9th register 12 connects with second memory 3,4; The 4th line receiver group 6 is connected with single-chip microcomputer through the tenth register 10, logical circuit, the data communication card connection of single-chip microcomputer and computing machine; In the receiver state control device, the control routine that computing machine produces transfers to single-chip microcomputer through PC serial ports, level translator successively, after single-chip microcomputer is handled, one group of signal is given first registers group 1, control signal is selected 1 allocate memory group 1 through 16, the content of first registers group 1 shows on the radar duty demonstration charactron of controller, the state of a control that another group signal removes the control radar receiver through 2 outputs of second registers group.

1, circuit description:

(1) line receiver group 1-4:

Every group 64, import 128 lines, export 64 lines.Parametric device model: 26LS32.The DIP16 encapsulation.

(2) the line receiver group 5,6:

Line receiver 5 inputs 12 lines are exported 6, wherein, and 2 of data, 2 of data-frame sync pulses, 2 of sampling clocks; Line receiver 6 inputs 10 lines are exported 5, wherein 4 on clock and PRF1 position.

(3) register 1-8,2 select 1:

Among the register 1-4,64 in each register is 2 to select 1, and 64 of its inputs are exported 32; Register 5-7,32 in each register; Register 8 is two-stage 32 bit registers.

Register 1,2 selects 1,5,96 signal wires of register.

(4) register 9,3 selects 1:

96 inputs, 32 outputs.With two EPLD, divide I, Q.Register 9 ternary outputs are controlled by S4.

(5) register 11,12, string commentaries on classics and 1, and string commentaries on classics and 2:

3 of wherein string commentaries on classics and 1, register 11 inputs are exported 32,8 of control signals.Totally 44 lines adopt 1 EPLD.Circuit block diagram as shown in Figure 4.

String change and 1 and string changes and 2, register 11 and register 12, shared two identical EPLD.Foregoing circuit is input 16 * 2 * 2.Sequential as shown in Figure 5.If 32 * 2 * 2, H1 interval 64 adds a pulse by steering logic in middle 32 pulses place, is H2.

(6) storer 1,2:

Be 32 * 64k.Requirement speed is fast.With reference to model: CY7C1021 (64K * 16bit)

(7) single machine unit:

Single-chip microcomputer is selected AT89C51 for use, communicates by letter with data collector with data communication card, transmits order and state.

(8) long line transmitter:

The output internal clocking, device model: 26LS31, DIP16 encapsulation.

(9) steering logic:

With single chip communication:

Data bus: 8.

Address bus: 4.

Control signal: 3, reading and writing, start, stop.

Condition line: 1 of acquisition state, 1 of output state.

Amount to: 17.

Input signal:

The input external clock: 5, CK1-CK5, H1.

The input internal clocking: 1,20MHz.

Incoming sync pulse: 1, the PRF pulse.

Amount to: 8.

Output signal:

OPADD code: 16.

Output clock: 3: CP1, CP1, CP0

Control is selected: 15.S1 ~ S12:14 position; Totally 4 of C1, C2, R, W.

The physical circuit block diagram as shown in Figure 5.

2, testing algorithm:

(1) hyperchannel amplitude-phase consistency:

If obtain the output signal data of a certain frequency from the measurement passage be:

S _i＝I _i+Q _i i＝1，2......N， (1)

The output signal data of a certain frequency of reference channel is:

Sr _i＝Ir _i+Qr _i i＝1，2......N， (2)

Can be regarded as to such an extent that the phase differential of every bit is thus

φ _ei＝arg(S _i/Sr _i)， (3)

The amplitude ratio is:

A _ei＝|S _i/Sr _i| (4)

: phase differential:

${\mathrm{\φ}}_e=\underset{i}{\mathrm{\Σ}}{\mathrm{\φ}}_{\mathrm{ei}}/N---\left(5\right)$

The average amplitude ratio:

$A_e=\underset{i}{\mathrm{\Σ}}{A}_{\mathrm{ei}}/N---\left(6\right)$

(2) amplitude versus frequency characte:

If obtain the output signal data of a certain frequency from the measurement passage be:

S _i＝I _i+Q _i i＝1，2......N， (7)

Then the amplitude of every bit is A _i=| S _i|, so the output amplitude of this frequency is:

$A=\underset{i}{\mathrm{\Σ}}{A}_i/N---\left(8\right)$

(3) dynamic range:

The radar duty correctly is set.The signalization source frequency.Signal amplitude is from A1 to A2, and step-length is the Δ decibel.Measure corresponding system-gain.The dynamic range gain trace is seen Fig. 6.The output power that is increased to when making gain compression 1dB when signal amplitude is output power 1dB compression point level P _-1(dBm), and record this moment signal to noise ratio (S/N ratio) be Snr, think that then system dynamics scope DR (dB) is: DR=Snr

(4) log characteristic:

Receiver is input as Ain, is output as Vout.Fitting a straight line is y=ax+b.Artificial definite two working point A1, A2.Calculate the logarithm error in this scope, Fig. 7 is seen in log characteristic analysis signal.With least square method estimated parameter a, b.

$\underset{a,b}{\min }\{\mathrm{\δ}=\mathrm{\Σ}[A_{\mathrm{in}}-\frac{V_{\mathrm{out}}\left(A_{\mathrm{in}}\right)-b}{a}\left]\right\}---\left(9\right)$

In the computation process, determine a earlier, the scope of b is selected big step-length again.Determine an a for the second time, b estimates more accurate a, b numerical value again with the less step-length of a, b more among a small circle.Finally draw the logarithm scope (Ain1, Ain2) and this scope in maximum error δ.

(5) orthogonal channel signal to noise ratio (S/N ratio) and number of significant digit calculate:

1) signalization frequency and amplitude record signal power S;

2) shutdown signal source radio frequency output records noise power N ₀

3) filtering N ₀In clutter, obtain noise power N;

4) then signal to noise ratio (S/N ratio) is SNR=S/N, and number of significant digit is:

ENOB＝(20log(2 ^n-1-1)-20log(N)-1.763)/6.02 (10)

N is an A/D transducer figure place in the formula.

(6) orthogonal channel amplitude phase error:

Intermediate-freuqncy signal is:

s(t)＝Amsin[2π(f0+fd)t+θ] (11)

In the formula, Am is the intermediate-freuqncy signal amplitude.F0 is an IF-FRE.Fd is Doppler frequency or signal frequency.θ is the intermediate-freuqncy signal first phase.The zero intermediate frequency digital signal is:

I _n＝A _Imcos(2πfdn/fpo+θ)+a (12)

Q _n＝A _Qmsin(2πfdn/fpo+θ+δ)+b (13)

In the formula, A _Im, A _QmBe respectively the amplitude of I road and Q road signal.A, b are respectively the direct current offset on I road and Q road.Fpo is the digital signal samples rate.δ is the phase error of orthogonal signal.

Get according to (12) formula:

$a=\frac{1}{N}[\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{I}_n-\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{A}_{\mathrm{Im}}\cos (2\mathrm{\πn}\frac{f_d}{f_{\mathrm{po}}}+\mathrm{\θ})]---\left(14\right)$

When fd satisfies:

fd＝fpoM/N (15)

M, N are positive integer in the formula, then in (14) formula square bracket back one be zero:

$a=\frac{1}{N}\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{I}_n---\left(16\right)$

Can get equally:

$b=\frac{1}{N}\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{Q}_n---\left(17\right)$

Zero intermediate frequency signals behind the compensating DC offset is:

I’n＝In-a (18)

Q’n＝Qn-b (19)

Get according to (12), (18) formula:

$\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{I}_n^{\′2}=\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{A}_{\mathrm{Im}}^2{\cos }^2(2\mathrm{\π}{f}_{b}n/f_{\mathrm{po}}+\mathrm{\θ})=\frac{N}{2}{A}_{\mathrm{Im}}^2-\frac{1}{2}{A}_{\mathrm{Im}}^2\underset{n=1}{\overset{N}{\mathrm{\Σ}}}\cos (4\mathrm{\π}{f}_{d}n/f_{\mathrm{po}}+2\mathrm{\θ})---\left(20\right)$

Fd satisfies (15) formula, then following formula last be zero:

$A_{\mathrm{Im}}=\sqrt{\frac{2}{N}\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{I}_n^2}---\left(21\right)$

Equally, get according to (13), (19) formula:

$A_{\mathrm{Qm}}=\sqrt{\frac{2}{N}\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{Q}_n^2}---\left(22\right)$

I, Q channel amplitude mismatch ratio η are:

$\mathrm{\η}=20\log \left(\frac{A_{\mathrm{Im}}}{A_{\mathrm{Qm}}}\right)---\left(23\right)$

Get according to (12), (13), (18), (19) formula:

${I^{\′}}_n\·{Q^{\′}}_n=\frac{1}{2}{A}_{\mathrm{Im}}{A}_{\mathrm{Qm}}[\sin (4\mathrm{\π}{f}_{d}n/f_{\mathrm{po}}+2\mathrm{\θ}+\mathrm{\δ})+\sin \mathrm{\δ}]---\left(24\right)$

To the following formula summation, when fd satisfies (15) formula:

$\sin \mathrm{\δ}=\frac{2}{N{A}_{\mathrm{Im}}{A}_{\mathrm{Qm}}}\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{I}_n{Q}_n-\frac{1}{N}\underset{n=1}{\overset{N}{\mathrm{\Σ}}}\sin (4\mathrm{\πMn}/N+2\mathrm{\θ}+\mathrm{\δ})---\left(25\right)$

Second of following formula is 0.Because of δ is very little, then:

δ=sin δ (radian)=(180sin δ)/π (degree) (26)

That is:

$\mathrm{\δ}=\frac{360}{\mathrm{N\π}{A}_{\mathrm{Im}}{A}_{\mathrm{Qm}}}\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{I}_n{Q}_n$ (degree) (27)

The mirror image level can pass through the DFT discrete transform, calculates component of signal and image frequency component position, and read output signal component and image frequency component calculate image frequency component residue.

If signal frequency can not satisfy (15) formula, can remove input signal, directly calculate direct current offset with (15), (16) formula.

3, software design:

Testing software is made up of following module:

(1) PCI communication card module:

Input: parameter (sampled data length, clock delay, clock edge parameter, clock source parameter, time size) image data process is as follows:

1) initialization PCI-7200 card.

2) the read data mode is set, sends the read data order.

3) the write data mode is set, by the PCI-7200 card to the single-chip microcomputer write data, the data that the data that single-chip microcomputer is sent according to the PCI-7200 card provide the PCI-7200 card to read to the PCI-7200 card.

(2) serial communication modular:

Input: the data that need send to control desk (STC is set, noise bits is set, local oscillator selection, waveform codes, other)

(3) write data library module:

Write the ACCESS database by the mode of DAO, major key constrains in the program and realizes, that is to say under the identical condition of twice test parameter, covers last test result.

(4) read data library module:

Read the ACCESS database by the mode of DAO.

(5) signal source administration module:

Output power and frequency by IEEE-488 bus control signal source.

(6) vector voltmeter is surveyed amplitude module:

Output power and frequency by IEEE-488 bus control signal source.

(7) vector voltmeter is surveyed amplitude and phase test module:

From vector voltmeter, read the phase differential and the amplitude difference of single channel amplitude and phase place and two passages by IEEE-488 bus.

(8) noise-measuring instrument administration module:

By IEEE-488 bus calibration noise-measuring instrument, the required parameter of noise-measuring instrument test is set, select the test pattern of noise-measuring instrument, read the noise figure that noise-measuring instrument records.

(9) frequency spectrograph administration module:

By IEEE-488 bus calibration frequency spectrograph, the frequency spectrograph centre frequency is set, Span frequency, parameters such as datum.Test out power, frequency, the each harmonic, spuious of simple signal by frequency spectrograph, test out the three dB bandwidth of FM signal..

(10) power meter initialization module:

By IEEE-488 bus calibration power meter, the required parameter of power meter test is set, from the power of power meter read output signal.

(11) wide test module during oscillograph:

By IEEE-488 bus the required parameter of oscillograph test is set, from the oscillograph read output signal the time wide.

Native system can be measured single channel radar or the noise figure of hyperchannel radar under various duties, gain, amplitude versus frequency characte, dynamic range, image frequency supression degree, the main performance of A/D transducer, the main performance of i/q demodulator, the log characteristic of log channel, the frequency of local vibration source, power, frequency spectrum is spuious, each harmonic, the frequency of driving source, power, frequency spectrum is spuious, each harmonic, the peak power of emission pumping signal, wide and bandwidth during the 3dB of waveform, pulse pressure consistance between the amplitude-phase consistency between each receiving cable of radar receiver and each receiving cable of radar receiver.Wherein, the radar receiver dynamic range, the number of significant digit of A/D transducer, log characteristic, the orthogonal channel characteristic, the measurement of the influence of intermediate frequency amplifier paired pulses compression etc. is by digital signal processing, measures with the virtual instrument mode.

Claims (1)

1, a kind of integrated measuring systme for radar receiver comprises computing machine, it is characterized in that: this system also comprises instrument group, data acquisition memory storage and receiver state control device, and wherein, each testing tool is connected with the interface card of computing machine respectively in the instrument group; The data acquisition memory storage comprises a plurality of line receiver group exclusive data acquisition and storage devices, the data acquisition memory storage comprises line receiver group (1-6), each line receiver group is connected with tested radar receiver by test channel, in the first line receiver group (1-3), each line receiver group is successively through a registers group, each registers group comprises one 64 first register (1,2,3) and one 32 second register (5,6,7), three second registers select 1 device and the 3rd register (9) through 3 successively, the 3rd register (9) is connected to first memory (1 respectively, 2) and the 4th register (13), the data communication card connection of the 4th register (13) and computing machine; The second line receiver group (4) is connected with the 6th register (8) of 32 of two-stages through one 64 the 5th register (4); The 6th register (8) is connected with the 7th register (14) with second memory (3,4) respectively, the data communication card connection of the 7th register (14) and computing machine; One group of the output signal of the 3rd line receiver group (5) is changeed through first string and shift register, the 8th register (11) and first memory (1,2) connect, another group signal changes through second string and shift register, the 9th register (12) and second memory (3,4) connect; The 4th line receiver group (6) is connected with single-chip microcomputer through the tenth register (10), logical circuit, the data communication card connection of single-chip microcomputer and computing machine; Long line transmitter is connected with logical circuit; In the receiver state control device, the control routine that computing machine produces transfers to single-chip microcomputer through PC serial ports, level translator successively, after single-chip microcomputer is handled, one group of signal is given first registers group (1), control signal selects 1 allocate memory group to deposit the space through 16, the content of first registers group (1) shows on the radar duty demonstration charactron of controller, the state of a control that another group signal removes the control radar receiver through second registers group (2) output.

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