CN100429566C - Pixel array, display panel thereof and display - Google Patents
Pixel array, display panel thereof and display Download PDFInfo
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- CN100429566C CN100429566C CNB2006101693101A CN200610169310A CN100429566C CN 100429566 C CN100429566 C CN 100429566C CN B2006101693101 A CNB2006101693101 A CN B2006101693101A CN 200610169310 A CN200610169310 A CN 200610169310A CN 100429566 C CN100429566 C CN 100429566C
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Abstract
This invention relates to pixel array and its display panel and device, wherein, the scan array comprises one first scan line connected to first array pixel and second array pixel; one second scan line connected to third and fourth pixel; several data lines divided into first and second sets; the first set is connected to third set pixel an the second set connected to fourth pixel. This invention reduces pixel array inner scanning usage number through each row of pixel with added data line to ensure the resistance accordance of data line and pixel array.
Description
Technical field
The present invention relates to a kind of pel array and display panel thereof and display, and be particularly related to a kind of pel array and display panels and LCD of triangular form pel array.
Background technology
Fig. 1 is known LCD 100, the pel array (pixel array) of its display panel (display panel) 101 adopt triangular form pel array (delta type pixel array or triangular type pixelarray) and and data line (data line) DL in the display panel 101 and the backguy (wire) between sweep trace (scan line) arrange synoptic diagram.Please refer to Fig. 1, triangular form pel array by the disclosed display panel 101 of Fig. 1 can be found out, sub-pixel (sub pixel) position in its first row and last column sub-pixel can be on not coaxial, so and backguy (wire) arrangement mode between the data line DL in the display panel 101 can form ladder form arrangement (step-type arrangement).Wherein, each the bar data line DL in the display panel 101 is a corresponding source electrode distribution that is coupled to source electrode driver 103.
In known technology, be positioned at coaxial sub-pixel (for example sub-pixel SP1 and the SP2 of Fig. 1) in the triangular form pel array of display panel 101, its data line DL in the display panel that is electrically connected to 101 be inequality.Therefore, must growth as the backguy distance of the data line DL in the sub-pixel SP3 of the second row sub-pixel among the edge regions A of Fig. 1 left side and the pairing display panel 101 of the sub-pixel SP4 of last column sub-pixel, could electrically connect with the source electrode distribution of source electrode driver 103, to such an extent as to so the backguy length between the interior data line DL of the triangular form pel array of display panel 101 and display panel 101 is different, and cause its each bar data line DL backguy impedance and be not quite similar, so the picture that can cause display panel 101 to be presented is inhomogeneous.
And it will be further appreciated that, because the backguy distance of the data line DL in the pairing display panel 101 of sub-pixel SP4 of the sub-pixel SP3 of the second row sub-pixel among the edge regions A of Fig. 1 left side and last column sub-pixel must increase, could electrically connect with the source electrode distribution of source electrode driver 103, so can cause the backguy space of the triangular form pel array periphery of display panel 101 to increase, and the triangular form pel array of display panel 101 and the backguy complexity between the data line DL in the display panel 101 have also been promoted simultaneously, and then the complexity that can produce on the product manufacture increases, and the problem that descends of its manufacturing process qualification rate.
In addition, because be positioned at coaxial sub-pixel in the triangular form pel array of display panel 101, its the data line DL in the display panel that is electrically connected to 101 be inequality, so it is the source electrode distribution number of source electrode driver 103 certainly will will increase, identical with the backguy number of the interior data line DL of the source electrode distribution number that reaches source electrode driver 103 and display panel 101.Yet, because used with display panel 101 in the same number of source electrode driver 103 of data line DL backguy, so the production cost will promote.
And what deserves to be mentioned is again, the triangular form pel array of known display panel 101, its each row sub-pixel all need be electrically connected to a sweep trace (scan line) GL, scanning voltage (the scan voltage that is exported with the gate wirings of receiving grid driver 105, Vscan), and enable its inner thin film transistor (TFT) (thin film transistor, TFT), and the charge efficiency of opening for the TFT that will promote each sub-pixel of each row in sub-pixel, known way is the size that has increased TFT, promote its charge efficiency to reach, but so can make the aperture opening ratio (aperture ratio) of each sub-pixel that each row sub-pixel is interior reduce, and then cause the penetrance (transmittance) of display panel 101 also to descend thereupon.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of pel array, it is by the corresponding sweep trace (scan line) of per two row sub-pixels, to reduce the configured number of one times of pel array interscan line, the number of scanning lines of employed gate drivers like this also can reduce one times, reaching the purpose that reduces the production cost, and the data line that doubles (data line), so that data line is consistent with the backguy impedance between pel array.
Another object of the present invention is to provide a kind of display panel, the image element array substrates of its utilization the invention described above is in wherein, not only can reach the advantage of the image element array substrates of the invention described above thus, and can also make that the picture that display panel presented is more even.
Based on above-mentioned and other purpose, the invention provides a kind of pel array, it comprises article one sweep trace, second sweep trace, and some data lines.Wherein, article one sweep trace and the first row sub-pixel and the second row sub-pixel electrically connect, and the second sweep trace then electrically connects with the third line sub-pixel and fourth line sub-pixel, and the sub-pixel dislocation in the wherein above-mentioned four lines sub-pixel in the adjacent lines is arranged.Some data line is divided into first group and second group, wherein first group and first and the third line sub-pixel electrically connect, second group then with second and the fourth line sub-pixel electrically connect.
Aforesaid pel array, wherein this first group turns right around to the below along the left side of each sub-pixel of this first row in sub-pixel, and turn left behind the below along the right side of the sub-pixel of this second row in sub-pixel of correspondence, turn right around to the below in the left side of the sub-pixel in this third line sub-pixel of correspondence again, and this second group turns left around to the below along the right side of each sub-pixel of this first row in sub-pixel, and turn right behind the below along the left side of the sub-pixel of this second row in sub-pixel of correspondence, turn left around to the below in the right side of the sub-pixel in this third line sub-pixel of correspondence again.
Aforesaid pel array, wherein this first group turns left around to the below along the right side of each sub-pixel of this first row in sub-pixel, and turn right behind the below along the left side of the sub-pixel of this second row in sub-pixel of correspondence, turn left around to the below in the right side of the sub-pixel in this third line sub-pixel of correspondence again, and this second group turns left around to the below along the right side of each sub-pixel of this first row in sub-pixel, and turn right behind the below along the left side of the sub-pixel of this second row in sub-pixel of correspondence, turn left around to the below in the right side of the sub-pixel in this third line sub-pixel of correspondence again.
Aforesaid pel array, wherein said data line is parallel to each other, and orthogonal with this first and second sweep trace.
From another viewpoint, the invention provides a kind of pel array, it comprises article one sweep trace, second sweep trace, and some data lines.Wherein, article one sweep trace and the first row sub-pixel and the second row sub-pixel electrically connect, and the second sweep trace then electrically connects with the third line sub-pixel and fourth line sub-pixel, and the sub-pixel dislocation in the wherein above-mentioned four lines sub-pixel in the adjacent lines is arranged.Some data line is divided into first group, second group, the 3rd group, four group group, the 5th group and the 6th group, wherein the first, the 3rd and the 5th group and first and the third line sub-pixel electrically connect, the second, the 4th and the 6th group then with second and the fourth line sub-pixel electrically connect.
Aforesaid pel array, wherein this first group turns left around to the below along the right side of the sub-pixel of this first row in sub-pixel of correspondence, and turn right behind the below along the left side of the sub-pixel of this second row in sub-pixel of correspondence, turn left around to the below in the right side of the sub-pixel in this third line sub-pixel of correspondence again.
Aforesaid pel array, wherein this second group along the right side of the sub-pixel of this first row in sub-pixel of correspondence toward left and right around the sub-pixel in pairing this second capable sub-pixel, and the right side of the sub-pixel in this third line sub-pixel of correspondence toward left and right around the sub-pixel in pairing this fourth line sub-pixel.
Aforesaid pel array, wherein the 3rd group turns right around to the below along the left side of the sub-pixel of this first row in sub-pixel of correspondence, and turn left behind the below along the right side of the sub-pixel of this second row in sub-pixel of correspondence, turn right around to the below in the left side of the sub-pixel in this third line sub-pixel of correspondence again.
Aforesaid pel array, wherein this four group group is turned left side around to the below along the top of the sub-pixel of this first row in sub-pixel of correspondence, and turn left behind the below along the right side of the sub-pixel of this second row in sub-pixel of correspondence, turn right around to the below in the left side of the sub-pixel in this third line sub-pixel of correspondence again.
Aforesaid pel array, wherein the 5th group's correspondence around behind the sub-pixel of this first row in sub-pixel, again the right side of the sub-pixel in this second row sub-pixel of correspondence toward left and right around the sub-pixel in pairing this third line sub-pixel.
Aforesaid pel array, wherein the 6th group turns right around to the below along the top of the sub-pixel of this first row in sub-pixel of correspondence, and turn right behind the below along the left side of the sub-pixel of this second row in sub-pixel of correspondence, turn left around to the below in the right side of the sub-pixel in this third line sub-pixel of correspondence again.
Aforesaid pel array, wherein said data line is parallel to each other, and orthogonal with this first and second sweep trace.
From another viewpoint, the invention provides a kind of display panel again, it is characterized in that having pel array, this pel array comprises article one sweep trace, second sweep trace, and some data lines.Wherein, article one sweep trace and the first row sub-pixel and the second row sub-pixel electrically connect, and the second sweep trace then electrically connects with the third line sub-pixel and fourth line sub-pixel, and the sub-pixel dislocation in the wherein above-mentioned four lines sub-pixel in the adjacent lines is arranged.Some data line is divided into first group and second group, wherein first group and first and the third line sub-pixel electrically connect, second group then with second and the fourth line sub-pixel electrically connect.
Aforesaid display panel, wherein this display panel comprises display panels.From another viewpoint, the invention provides a kind of display panel again, it has a pel array, and it comprises article one sweep trace, second sweep trace, and some data lines.Wherein, article one sweep trace and the first row sub-pixel and the second row sub-pixel electrically connect, and the second sweep trace then electrically connects with the third line sub-pixel and fourth line sub-pixel, and the sub-pixel dislocation in the wherein above-mentioned four lines sub-pixel in the adjacent lines is arranged.Some data line is divided into first group, second group, the 3rd group, four group group, the 5th group and the 6th group, wherein the first, the 3rd and the 5th group and first and the third line sub-pixel electrically connect, the second, the 4th and the 6th group then with second and the fourth line sub-pixel electrically connect.
Aforesaid display panel, wherein this display panel comprises display panels.
Pel array provided by the present invention, it can be applied in now the display panels and LCD thereof, because by the corresponding sweep trace (scan line) of per two row sub-pixels, so can reduce the load of gate driver drive display panel, so can reduce the consumed power of display panel integral body, and also because of the corresponding sweep trace of per two row sub-pixels, so must increase the sweep time of display panels, so can accelerate liquid crystal reaction (LC response) speed of the pixel of display panels.
In addition, because reduce the number of the sweep trace that is disposed in one times of pel array and the number of the data line that doubles, so can save the space that backguy is arranged in the pel array, but so size of the thin film transistor (TFT) of each sub-pixel in the reduced image pixel array, so each the sub-pixel aperture opening ratio in the pel array also increases thereupon, thus with the charge efficiency of the thin film transistor (TFT) of sub-pixel in the penetrance that promotes display panel and its pel array.
In addition, pel array provided by the present invention, because the data line that doubles (data line), so not only can reduce the complexity that the backguy in the pel array is arranged, and data line is consistent with the backguy impedance between pel array, so can be so that the picture that display panels presented be comparatively even, and the picture quality of its applied LCD also promotes thereupon.For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, the preferred embodiments of the present invention cited below particularly, and cooperate appended accompanying drawing, be described in detail below.
Description of drawings
Fig. 1 is known LCD, the pel array of its display panel adopt the triangular form pel array and and the synoptic diagram arranged of the data line in the display panel and the backguy between sweep trace.
Fig. 2 is the calcspar according to the display of first embodiment of the invention.
Fig. 3 is the circuit diagram of pel array of the display panel of first embodiment of the invention.
Fig. 4 is the calcspar according to the display of second embodiment of the invention.
Fig. 5 is the circuit diagram of pel array of the display panel of second embodiment of the invention.
Fig. 6 is the calcspar according to the display of third embodiment of the invention.
Fig. 7 is the circuit diagram of pel array of the display panel of third embodiment of the invention.
Wherein, description of reference numerals is as follows:
100,200,400,600 displays
101,201,401,601 display panels
103,203 source electrode drivers
105,205 gate drivers
300,500,700 pixel array circuit figure
R1～R4 first～fourth line sub-pixel
The DL data line
FGL first sweep trace
SGL second sweep trace
SP 1, SP2, SP3, SP4 sub-pixel
Embodiment
First embodiment
Fig. 2 is the calcspar according to the display 200 of first embodiment of the invention, wherein display 200 can be any plane display, for example LCD (liquid crystal display, LCD), plasma scope (plasma display panel, PDP) etc.Please refer to Fig. 2, display 200 is a LCD, and it comprises display panel 201, source electrode driver 203, and gate drivers 205.Wherein, display panel 201 comprises pel array (pixel array), and it is configured on the substrate (substrate, not shown), and has article one sweep trace FGL, second sweep trace SGL, and some data line DL.In this first embodiment, the sweep trace FGL and the first row sub-pixel R1 and the second row sub-pixel R2 electrically connect, sweep trace SGL then electrically connects with the third line sub-pixel R3 and fourth line sub-pixel R4, and the dislocation of the sub-pixel among above-mentioned four lines sub-pixel R1～R4 in the adjacent lines is arranged, so to form triangular form pel array (delta type pixel array).
Some data line DL in the pel array of display panel 201 are divided into first group and second group.Wherein, turn right around to the below and electrically connect with sub-pixel in the corresponding first row sub-pixel R1 in the left side of the data line DL of first group each sub-pixel (sub pixel) in this first row sub-pixel R1, and turn left behind the below in the right side of the sub-pixel in the second row sub-pixel R2 of the non-contraposition of vicinity of correspondence, and turn right around to the below and electrically connect with sub-pixel in corresponding this third line sub-pixel R3 in the left side of the sub-pixel in the third line sub-pixel R3 of the non-contraposition of vicinity of correspondence again.
Turn left around to the below and electrically connect with sub-pixel in the corresponding second row sub-pixel R2 in the right side of each sub-pixel of the data line DL of second group in the first row sub-pixel R1, and turn right behind the below in the left side of the sub-pixel in the second row sub-pixel R2 of the non-contraposition of vicinity of correspondence, and turn left around to the below and electrically connect with sub-pixel in the corresponding fourth line sub-pixel R4 in the right side of the sub-pixel in the third line sub-pixel R3 of the non-contraposition of vicinity of correspondence again.
So according to as can be known above-mentioned, a source electrode distribution (source line) of the electric connection source electrode driver 203 of the data line DL correspondence of first group, in order to receive its data voltage of exporting (data voltage), and provide sub-pixel to first row sub-pixel R1 and the third line sub-pixel R3, and a source electrode distribution of the also corresponding electric connection source electrode driver 203 of the data line DL of second group, in order to receiving the data voltage that it is exported, and provide sub-pixel to the second row sub-pixel R2 and the fourth line sub-pixel R4.
In this first embodiment, the first row sub-pixel R1 and the corresponding first sweep trace FGL of the second row sub-pixel R2, so when gate wirings (gate line) the output scanning voltage (scan voltage) of gate drivers 205 during to the first sweep trace FGL, thin film transistor (TFT) (the thin film transistor of the sub-pixel in the first row sub-pixel R1 and the second row sub-pixel R2, not shown) can be enabled simultaneously (enable), the data voltage of being exported with the reception sources driver 203 of correspondence.In like manner as can be known, the third line sub-pixel R3 and the also corresponding second sweep trace SGL of fourth line sub-pixel R4, so when gate wirings output scanning voltage to the second sweep trace SGL of gate drivers 205, the thin film transistor (TFT) of the sub-pixel in the third line sub-pixel R3 and the fourth line sub-pixel R4 can be enabled simultaneously, the data voltage of being exported with the reception sources driver 203 of correspondence.
Fig. 3 is the circuit diagram of pel array of the display panel 201 of first embodiment of the invention.Please in the lump with reference to Fig. 2 and Fig. 3, can find out by the disclosed circuit 300 of Fig. 3, because of the corresponding sweep trace of per two row sub-pixels in the pel array of display panel 201, so two row pixels of its corresponding scanning beam, the thin film transistor (TFT) in its sub-pixel can present and turns upside down and contraposition such as non-.And because the technology that first embodiment focuses on is the backguy arrangement mode of the pel array of display panel 201, but not the Driving technique of display panel 201, and the Driving technique of display panel 201 is well known technology, should be that the technician knows under field of the present invention, and, therefore seldom do narration in order not obscure spirit of the present invention.
In this first embodiment, it is to be used as illustrating with four lines sub-pixel R1～R4, yet should be with this field that the present invention belongs to technician, and know the pel array of the display panel that multirow sub-pixel more constituted easily by inference, so at this and no longer given unnecessary details according to after the above-mentioned explanation.
And what deserves to be mentioned is that by the electrical connection of the pel array of the disclosed display panel 201 of Fig. 2 as can be known, the data line DL of first group and the data line DL of second group are parallel to each other, and orthogonal with the first sweep trace FGL and the second sweep trace SGL.In addition, it is formed with the bouble-bow font and with left and right sides mirror (mirror) arrangement, so not only can reduce the complexity that the interior backguy of the pel array of display panel 201 is arranged, and the backguy impedance phase of its corresponding data lines DL is with (that is etc. impedance), so can be so that the picture that display panel 201 is presented is comparatively even, to such an extent as to the picture quality that its applied display 200 is presented promotes.
In addition, because the first row sub-pixel R1 and the corresponding article one sweep trace of second row sub-pixel R2 FGL, and the third line sub-pixel R3 and the corresponding second sweep trace of fourth line sub-pixel R4 SGL, so what can know by inference is, the employed number of scanning lines of pel array of the display panel 201 of present embodiment lacks one times than the employed number of scanning lines of the pel array of the display panel of prior art, so can reduce the load that gate drivers 205 drives display panel 201, so can reduce the consumed power of display panel 201 integral body, and also because of the corresponding sweep trace of per two row sub-pixels, so must increase the sweep time of display panel 201, so can accelerate liquid crystal reaction (LCresponse) speed of interior each sub-pixel of pel array of display panel 201.
Accept above-mentioned, also also because of like this, so can save the space that the interior backguy of the pel array of display panel 201 is arranged, so can dwindle the size of the thin film transistor (TFT) of each sub-pixel in the pel array of display panel 201, each sub-pixel aperture opening ratio (aperture ratio) in the pel array of display panel 201 like this also increases thereupon, thus with the penetrance (transmittance) of lifting display panel 201 and the charge efficiency (that is efficient of antithetical phrase pixel internal storage accumulate capacity charge) of the thin film transistor (TFT) of the interior sub-pixel of its pel array.
Second embodiment
Fig. 4 is the calcspar according to the display 400 of second embodiment of the invention.Please in the lump with reference to Fig. 2 and Fig. 4, display 400 does not exist together with the maximum of display 200, it is that the span wire system of the data line DL of the data line DL of first group of pel array of display panel 401 and second group is different from the span wire system of the data line DL of the data line DL of first group of pel array of display panel 201 and second group, and the problem of its effect that will reach and solution is all identical with display 200, so no longer given unnecessary details at this.
In this second embodiment, turn left around to the below and electrically connect with sub-pixel in the corresponding first row sub-pixel R1 in the right side of each sub-pixel of the data line DL of first group in the first row sub-pixel R1, and the left side of the sub-pixel in the second row sub-pixel R2 of the non-contraposition of vicinity of correspondence turns right behind the below, and turn left around to the below and electrically connect with sub-pixel in corresponding the third line sub-pixel R3 in the right side of the sub-pixel in the third line sub-pixel R3 of the non-contraposition of vicinity of correspondence again.
Turn left around to the below and electrically connect with sub-pixel in the corresponding second row sub-pixel R2 in the right side of each sub-pixel of the data line DL of second group in the first row sub-pixel R1, and the left side of the sub-pixel in the second row sub-pixel R2 of the non-contraposition of vicinity of correspondence turns right behind the below, and turn left around to the below and electrically connect with sub-pixel in the corresponding fourth line sub-pixel R4 in the right side of the sub-pixel in the third line sub-pixel R3 of the non-contraposition of vicinity of correspondence again.
Fig. 5 is the circuit diagram 500 of pel array of the display panel 401 of second embodiment of the invention, it is also because of the corresponding sweep trace of per two row sub-pixels in the pel array of display panel 401, so two row pixels of its corresponding scanning beam, thin film transistor (TFT) in its sub-pixel also can present and turns upside down and contraposition such as non-, and because the technology that second embodiment focuses on is the backguy arrangement mode of the pel array of display panel 401, but not the Driving technique of display panel 401, and the Driving technique of display panel 401 and display panel 201 are similar, so no longer given unnecessary details at this.
The 3rd embodiment
Fig. 6 is the calcspar according to the display 600 of third embodiment of the invention.Please merge with reference to Fig. 2 and Fig. 6, display 600 does not exist together with the maximum of display 200, the data line DL that is the pel array of display panel 601 is divided into six groups, and the mode of its backguy also is different from the data line DL span wire system of the pel array of display panel 201, but the effect of reaching and the problem of solution are all identical with display 200, so no longer given unnecessary details at this.
In this 3rd embodiment, turn left around to the below and electrically connect with sub-pixel in the corresponding first row sub-pixel R1 in the right side of the sub-pixel of the data line DL of first group in the first row sub-pixel R1 of correspondence, and the left side of the sub-pixel in the second row sub-pixel R2 of the non-contraposition of vicinity of correspondence turns right behind the below, and turn left around to the below and electrically connect with sub-pixel in corresponding the third line sub-pixel R3 in the right side of the sub-pixel in the third line sub-pixel R3 of the non-contraposition of vicinity of correspondence again.
The right side of the sub-pixel of the data line DL of second group in the first row sub-pixel R1 of correspondence toward left and right around the sub-pixel in the second capable sub-pixel R2 of contiguous non-contraposition, and with its electric connection, and the right side of the sub-pixel in the third line sub-pixel R3 of the non-contraposition of vicinity of correspondence toward left and right around the sub-pixel in the fourth line sub-pixel R4 of contiguous non-contraposition, and with its electric connection.
Turn right around to the below and electrically connect with sub-pixel in the corresponding first row sub-pixel R1 in the left side of the sub-pixel of the data line DL of the 3rd group in the first row sub-pixel R1 of correspondence, and the right side of the sub-pixel in the second row sub-pixel R2 of the non-contraposition of vicinity of correspondence turns left behind the below, and turn right around to the below and electrically connect with sub-pixel in corresponding the third line sub-pixel R3 in the left side of the sub-pixel in the third line sub-pixel R3 of the non-contraposition of vicinity of correspondence again.
The top of the sub-pixel of the data line DL of four group group in the first row sub-pixel R1 of the correspondence side of turning left electrically connects with sub-pixel in the corresponding second row sub-pixel R2 around to the below, and the right side of the sub-pixel in the second row sub-pixel R2 of the non-contraposition of vicinity of correspondence turns left behind the below, and turn right around to the below and electrically connect with sub-pixel in the corresponding fourth line sub-pixel R4 in the left side of the sub-pixel in the third line sub-pixel R3 of the non-contraposition of vicinity of correspondence again.
The data line DL correspondence of the 5th group around behind the sub-pixel in the first row sub-pixel R1, and with its electric connection, again the right side of the sub-pixel in the second row sub-pixel R2 of the non-contraposition of vicinity of correspondence toward left and right around the sub-pixel in the third line sub-pixel R3 that is close to non-contraposition, and with its electric connection.
Turn right around to the below and electrically connect with sub-pixel in the corresponding second row sub-pixel R2 in the top of the sub-pixel of the data line DL of the 6th group in the first row sub-pixel R1 of correspondence, and the left side of the sub-pixel in the second row sub-pixel R2 of the non-contraposition of vicinity of correspondence turns right behind the below, and turn left around to the below and electrically connect with sub-pixel in the corresponding fourth line sub-pixel R4 in the right side of the sub-pixel in the third line sub-pixel R3 of the non-contraposition of vicinity of correspondence again.
And what deserves to be mentioned is, the data line DL of the data line DL of second group and the 5th group in this 3rd embodiment, it is because of around around the pairing sub-pixel, so might cause its aperture opening ratio (aperture ratio) to descend, so in this 3rd embodiment, at this shortcoming, the data line DL of all second groups and the data line DL of the 5th group corresponding around around sub-pixel, it utilizes the color of higher gray scale to compensate on colored filter (color filter), but not the data line DL of the data line DL of second group and the 5th group corresponding around around sub-pixel, that is first, the 3rd, the pairing sub-pixel of the data line of the 4th and the 6th group, then utilize the color of low gray scale to do collocation, so after above-mentioned average its colourity, can solve the shortcoming that this 3rd embodiment is caused.
Fig. 7 is the circuit diagram 700 of pel array of the display panel 601 of third embodiment of the invention, it is also because of the corresponding sweep trace of per two row sub-pixels in the pel array of display panel 601, so two row pixels of its corresponding scanning beam, thin film transistor (TFT) in its sub-pixel also can present and turns upside down and contraposition such as non-, and because the technology that the 3rd embodiment focuses on also is the backguy arrangement mode of the pel array of display panel 601, but not the Driving technique of display panel 601, and the Driving technique of display panel 601 is also similar with display panel 201, so no longer given unnecessary details at this.
In sum, the present invention provides a kind of pel array, and it can be applied in now the display panels and LCD thereof.According to spirit of the present invention, it has descending some advantage:
1. because of the corresponding sweep trace of per two row pixels, so the load of gate driver drive display panel is descended, so can reduce the consumed power of display panel integral body, to prevent to cause under the high flow rate electric weight the influence of high heat, high resistance to display panel, and also because of like this, must increase the sweep time of display panel, so can accelerate liquid crystal reaction (LC response) speed of interior each pixel of pel array of display panel.
2. because reduce the use number of one times of pel array interscan line and the number of the data line that doubles, so can save the space that backguy is arranged in the pel array, but so size of the thin film transistor (TFT) of each sub-pixel in the reduced image pixel array, each sub-pixel aperture opening ratio (apertureratio) in the pel array like this also increases thereupon, thus with the penetrance (transmittance) of lifting display panel and the charge efficiency of the thin film transistor (TFT) of the interior sub-pixel of its pel array.
3. because the data line (data line) that doubles, so not only can reduce the complexity that the backguy in the pel array is arranged, and data line is consistent with the backguy impedance between pel array, so can be so that the picture that display panels presented be comparatively even, and the picture quality of its applied LCD also promotes thereupon.
Though the present invention with preferred embodiment openly as above; right its is not in order to restriction the present invention; any one of ordinary skill in the art; without departing from the spirit and scope of the present invention; when can doing a little change and modification, so protection scope of the present invention is as the criterion when looking the scope that accompanying Claim defines.
Claims (16)
1. pel array comprises:
One article one sweep trace, this article one sweep trace and the first row sub-pixel and the second row sub-pixel electrically connect;
One second sweep trace, this second sweep trace and the third line sub-pixel and fourth line sub-pixel electrically connect, and the sub-pixel in wherein above-mentioned those row sub-pixels in the adjacent lines is arranged for dislocation; And
Some data lines, described data line are divided into first group and second group, and wherein this first group and this first and this third line sub-pixel electrically connect, this second group then with this second and this fourth line sub-pixel electrically connect;
The backguy arrangement design of wherein said some data lines is:
The data line backguy equal in length of described first row sub-pixel and the described second row sub-pixel;
The data line backguy equal in length of described the third line sub-pixel and described fourth line sub-pixel.
2. pel array as claimed in claim 1, wherein this first group turns right around to the below along the left side of each sub-pixel of this first row in sub-pixel, and turn left behind the below along the right side of the sub-pixel of this second row in sub-pixel of correspondence, turn right around to the below in the left side of the sub-pixel in this third line sub-pixel of correspondence again, and this second group turns left around to the below along the right side of each sub-pixel of this first row in sub-pixel, and turn right behind the below along the left side of the sub-pixel of this second row in sub-pixel of correspondence, turn left around to the below in the right side of the sub-pixel in this third line sub-pixel of correspondence again.
3. pel array as claimed in claim 1, wherein this first group turns left around to the below along the right side of each sub-pixel of this first row in sub-pixel, and turn right behind the below along the left side of the sub-pixel of this second row in sub-pixel of correspondence, turn left around to the below in the right side of the sub-pixel in this third line sub-pixel of correspondence again, and this second group turns left around to the below along the right side of each sub-pixel of this first row in sub-pixel, and turn right behind the below along the left side of the sub-pixel of this second row in sub-pixel of correspondence, turn left around to the below in the right side of the sub-pixel in this third line sub-pixel of correspondence again.
4. pel array as claimed in claim 1, wherein said data line is parallel to each other, and orthogonal with this first and second sweep trace.
5. pel array comprises:
One article one sweep trace, this article one sweep trace and the first row sub-pixel and the second row sub-pixel electrically connect;
One second sweep trace, this second sweep trace and the third line sub-pixel and fourth line sub-pixel electrically connect, and the sub-pixel dislocation in wherein above-mentioned these row sub-pixels in the adjacent lines is arranged; And
Some data lines, described data line is divided into first group, second group, the 3rd group, four group group, the 5th group and the 6th group, wherein this first, the 3rd and the 5th group and this first and this third line sub-pixel electrically connect, this second, the 4th and the 6th group then with this second and this fourth line sub-pixel electrically connect;
The backguy arrangement design of wherein said some data lines is:
The data line backguy equal in length of described first row sub-pixel and the described second row sub-pixel;
The data line backguy equal in length of described the third line sub-pixel and described fourth line sub-pixel.
6. pel array as claimed in claim 5, wherein this first group turns left around to the below along the right side of the sub-pixel of this first row in sub-pixel of correspondence, and turn right behind the below along the left side of the sub-pixel of this second row in sub-pixel of correspondence, turn left around to the below in the right side of the sub-pixel in this third line sub-pixel of correspondence again.
7. pel array as claimed in claim 5, wherein this second group along the right side of the sub-pixel of this first row in sub-pixel of correspondence toward left and right around the sub-pixel in pairing this second capable sub-pixel, and the right side of the sub-pixel in this third line sub-pixel of correspondence toward left and right around the sub-pixel in pairing this fourth line sub-pixel.
8. pel array as claimed in claim 5, wherein the 3rd group turns right around to the below along the left side of the sub-pixel of this first row in sub-pixel of correspondence, and turn left behind the below along the right side of the sub-pixel of this second row in sub-pixel of correspondence, turn right around to the below in the left side of the sub-pixel in this third line sub-pixel of correspondence again.
9. pel array as claimed in claim 5, wherein this four group group is turned left side around to the below along the top of the sub-pixel of this first row in sub-pixel of correspondence, and turn left behind the below along the right side of the sub-pixel of this second row in sub-pixel of correspondence, turn right around to the below in the left side of the sub-pixel in this third line sub-pixel of correspondence again.
10. pel array as claimed in claim 5, wherein the 5th group's correspondence around behind the sub-pixel of this first row in sub-pixel, again the right side of the sub-pixel in this second row sub-pixel of correspondence toward left and right around the sub-pixel in pairing this third line sub-pixel.
11. pel array as claimed in claim 5, wherein the 6th group turns right around to the below along the top of the sub-pixel of this first row in sub-pixel of correspondence, and turn right behind the below along the left side of the sub-pixel of this second row in sub-pixel of correspondence, turn left around to the below in the right side of the sub-pixel in this third line sub-pixel of correspondence again.
12. pel array as claimed in claim 5, wherein said data line is parallel to each other, and orthogonal with this first and second sweep trace.
13. a display panel comprises pel array as claimed in claim 1.
14. display panel as claimed in claim 13, wherein this display panel comprises display panels.
15. a display panel comprises pel array as claimed in claim 5.
16. display panel as claimed in claim 15, wherein this display panel comprises display panels.
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| CNB2006101693101A CN100429566C (en) | 2006-12-12 | 2006-12-12 | Pixel array, display panel thereof and display |
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| CNB2006101693101A CN100429566C (en) | 2006-12-12 | 2006-12-12 | Pixel array, display panel thereof and display |
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| CN100429566C true CN100429566C (en) | 2008-10-29 |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101354506B (en) * | 2007-07-25 | 2010-04-21 | 北京京东方光电科技有限公司 | Pixel structure of thin-film transistor LCD device |
| TWI543130B (en) * | 2009-05-29 | 2016-07-21 | 皇家飛利浦電子股份有限公司 | Cuttable display device, method of providing a cut-to-measure display device for displaying an image using a cuttable display device, and computer-implemented method of positioning a closed two-dimensional contour relative to a two-dimensional lattice of |
| CN102854680B (en) * | 2012-09-25 | 2015-02-25 | 南京中电熊猫液晶显示科技有限公司 | High-light transmittance transparent display device |
| CN103943032B (en) * | 2014-04-01 | 2016-03-02 | 京东方科技集团股份有限公司 | A kind of array base palte and display device |
| CN103985735A (en) * | 2014-04-25 | 2014-08-13 | 友达光电股份有限公司 | Display panel |
| KR102581759B1 (en) | 2016-05-23 | 2023-09-25 | 삼성디스플레이 주식회사 | Display apparatus |
| CN107004392B (en) | 2016-11-28 | 2019-11-05 | 上海云英谷科技有限公司 | The distributed driving of display panel |
| CN107038967B (en) * | 2017-05-15 | 2019-06-28 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
| CN107104112A (en) * | 2017-06-20 | 2017-08-29 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display panel, display device |
| TWI668508B (en) | 2018-08-13 | 2019-08-11 | 友達光電股份有限公司 | Pixel unit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1731503A (en) * | 2005-09-06 | 2006-02-08 | 友达光电股份有限公司 | Display panel |
| CN1779766A (en) * | 2004-11-22 | 2006-05-31 | 三星Sdi株式会社 | Triangular pixel circuit and luminescent circuit display device |
| US20060197726A1 (en) * | 2005-03-02 | 2006-09-07 | Yuan-Liang Wu | Pixel array substrate having storage capacitances that vary along a scan line |
| JP2006276401A (en) * | 2005-03-29 | 2006-10-12 | Seiko Epson Corp | Electrooptical device and electronic equipment |
-
2006
- 2006-12-12 CN CNB2006101693101A patent/CN100429566C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1779766A (en) * | 2004-11-22 | 2006-05-31 | 三星Sdi株式会社 | Triangular pixel circuit and luminescent circuit display device |
| US20060197726A1 (en) * | 2005-03-02 | 2006-09-07 | Yuan-Liang Wu | Pixel array substrate having storage capacitances that vary along a scan line |
| JP2006276401A (en) * | 2005-03-29 | 2006-10-12 | Seiko Epson Corp | Electrooptical device and electronic equipment |
| CN1731503A (en) * | 2005-09-06 | 2006-02-08 | 友达光电股份有限公司 | Display panel |
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