CN100428747C - Generating method for linear digital frequency modulation signal - Google Patents
Generating method for linear digital frequency modulation signal Download PDFInfo
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- CN100428747C CN100428747C CNB2005100182176A CN200510018217A CN100428747C CN 100428747 C CN100428747 C CN 100428747C CN B2005100182176 A CNB2005100182176 A CN B2005100182176A CN 200510018217 A CN200510018217 A CN 200510018217A CN 100428747 C CN100428747 C CN 100428747C
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Abstract
The present invention relates to a method for generating linear digital frequency modulation signals. Firstly, a recursive feedback mode is used for generating a basal digital specimen sequence, and subsequently, the generated basal digital specimen sequence is compensated in a certain amplitude way so that the outputted linear frequency modulation signals are continuous oscillation signals. The basal digital specimen sequence is generated by using a second order IIR filter and is given by a formula y [n]=2*A[n]*y [n-1]-y [n-2], wherein the y [n] is the basal digital specimen sequence, and A[n] determines the frequency of the sequence The amplitude compensation has the proposal that the basal digital specimen sequence is multiplied by a variable which can form complementation with the amplitude variation of the basal digital specimen; the variable is given by a formula G[n]=Kx*G[n-1], when n is equal to 0, the G[n]=Kx*G[n-1] has the result G[0]=1G[1]=Kx, wherein the G[n] represents the compensation value, and the Kx represents the varying frequency of the compensation value; finally, a total output formula is yout [n]=G[n]*y [n]. The procedure realizing the linear frequency modulation signals is simplified, and the computational amount is greatly reduced. Moreover, the recursive result in each time is stored in an original storage device so that the storage space is reduced.
Description
Technical field
The present invention relates to a kind of production method of linear digital frequency modulation signal, (Infinite Impulse Response, IIR) filter produces the method in linear frequency modulated radar signal source particularly to utilize the second order infinite impulse response.(Field Programmable GateAway FPGA) waits resource-constrained but realizes in the fast device of parallel processing to be specially adapted at the scene programmable logic device.
Background technology
Linear frequency modulation (Linear Frequency Modulation, LFM) be also referred to as Chirp, be the earliest with the most ripe pulse compression technique of development, this technology can allow radar system launch the relative broad of width and the lower pulse of peak power, to obtain burst pulse, the resolution of high-peak power radar system and detection performance.The method of traditional generation linear FM signal is divided into simulation and digital method.Mainly (Voltage ControlledOscillator VCO) produces linear FM signal to simulation, and major defect is that signal coherency is poor, frequency instability etc. with linear saw-tooth voltage control voltage controlled oscillator; Add phase-locked loop and can guarantee that the starting point phase place and the reference signal of linear FM signal are synchronous, but the carrier frequency phase place during producing linear FM signal guarantees by the stability of time delay and the stability of chirp rate fully.Development along with large scale integrated circuit and digital technology, present linear FM signal extensively adopts the Direct Digital synthetic method, and (Direct Digital Synthesis DDS) produces, can be to the DDS output waveform by digital-control circuit or software programming, frequency, amplitude and phase place are carried out accurately control.The circuit that DDS produces linear FM signal generally comprises reference clock, frequency accumulator, and phase accumulator, wave memorizer, digital to analog converter (D/A) and low pass filter (Low Pass Filter, LPF); Frequency accumulator is carried out accumulating operation to input signal, produces frequency control data or phase step input; Phase accumulator is formed by full adder and accumulator register cascade, frequency data added up, and be feedback circuit, produce accumulation result; Wave memorizer is for the use of tabling look-up, and the accumulation result of generation carries out addressing to it, and the data of reading are sent into D/A converter and low pass filter.Utilize digital technology to produce the generation that linear FM signal is based on the numeral sample sequence, the numeral sample sequence can produce in real time or calculate in advance and be kept in the memory, preceding a kind of method can be avoided the restriction of memory capacity, but the equal more complicated of the present implementation method that proposes.A kind of method in back is the employed method of DDS just, in current system, is widely adopted, and all are the modes that adopt the waveform storage as the serial DDS chip of the AD985X of AD company.This method simply is easy to realize, can obtains the output signal of very high resolution and relative bandwidth broad.But along with the raising of frequency resolution, corresponding memory capacity also will increase, and because DDS generally adopts the phase truncation technology, thereby in output signal, introduced spuious.On the other hand, present digital signal processor (Digital Signal Processors, DSP) can be operated in very on the high-frequency, therefore the available digital method produces high-frequency signal, but the calculating addressing of SIN function has still taken a large amount of clock cycle, and this makes that the DSP operating efficiency is low.
Summary of the invention
The objective of the invention is to adopt the second order iir filter to produce basic numeral sample sequence in real time, at last the result is compensated.
Technical scheme of the present invention: the generation of the numeral sample sequence of the production method of linear digital frequency modulation signal of the present invention, be to utilize auto-excitation type second order iir filter to produce basic numeral sample sequence, then the basic numeral sample sequence that is produced is carried out the amplitude compensation, make output linear FM signal be the self-sustained oscillation signal, basic numeral sample sequence as shown in the formula:
y[n]＝2*A[n]*y[n-1]-y[n-2] (8)
Y[n wherein] the basic numeral sample sequence of representative, two initial condition of second order filter are:
y[0]＝C*sin(Φ) y[1]＝C*sin(Φ+Ω
start+ΔΩ)(9)
Wherein Φ is an initial phase, and C is an amplitude, Ω
StartBe the initial number frequency, Δ Ω is a frequency interval;
A[n] be frequency sequence, A[n]=cos (Ω
n), Ω wherein
n=Ω
Start+ n* Δ Ω represents numerical frequency;
The amplitude compensation is that basic numeral sample sequences y [n] be multiply by a compensation sequence G[n]; G[n] provide with recursive sub:
G[n]＝Kx*G[n-1] (11)
G[0]＝1G[1]＝Kx (12)
G[n wherein] representative compensation sequence, Kx represent the speed of offset variation, and it is provided by following formula:
Kx＝(envelop(t
max)/C
initial)^(-1/N
d) (10)
Wherein ' envelop (t
MaxLast envelope value of waveform between) ' expression compensating basin, C
InitialThe initial envelope value of waveform between the expression compensating basin.Compensation increases progressively with waveform two intervals of successively decreasing by waveform and carries out respectively, and last envelope value of previous interval waveform is as the initial value of a back interval waveform envelope.N
dCorrespond respectively to the number of samples between the compensating basin; G[n] promptly be the offset that calculates, total the output of last linear digital frequency modulation signal is exactly y
Out[n]=G[n] * y[n].
The production method of described linear digital frequency modulation signal produces frequency sequence A[n with an auto-excitation type second order iir filter]:
A[n]＝2cos(ΔΩ)*A[n-1]-A[n-2] (6)
A[0]＝cos(Ω
start) A[1]＝cos(Ω
start+ΔΩ)?(7)
The production method of described linear digital frequency modulation signal, used linear digital frequency modulation signal source comprises numeral sample sequence generator, system clock and D/A converter.The numeral sample sequence generator comprises: produce basic numeral sample sequence Y[n] auto-excitation type second order iir filter, produce sequence frequency A[n] auto-excitation type second order iir filter, produce offset G[n] multiplier, produce the numeral sample sequences y
OutThe multiplier of [n] and D/A converter.The numeral sample sequence send D/A converter that digital signal is converted to analog signal output.
The production method of described linear digital frequency modulation signal, the numeral sample sequence generator in linear digital frequency modulation signal source use field programmable logic array to realize.Specifically comprise: calculated rate sequence A [n] is realized by the second order iir filter that first multiplier (MUL1), first adder (SUB1), first d type flip flop (FD1) and second d type flip flop (FD2) are formed; Two of first multiplier (MUL1) are input as 2cos (Δ Ω) and A[n-1], first d type flip flop (FD1) and second d type flip flop (FD2) are used for time delay, are used for producing A[n-1 respectively] and A[n-2].Calculate the second order iir filter realization that basic numeral sample sequences y [n] is made up of second multiplier (MUL2), second adder (SUB2), 3d flip-flop (FD3) and four d flip-flop (FD4); Frequency sequence A[n] as an input of second multiplier (MUL2), 3d flip-flop (FD3) and four d flip-flop (FD4) are used for time delay, produce y[n-1 respectively] and y[n-2]; The 4th multiplier (MUL4) is used for calculating compensation sequence G[n], Kx and G[n-1] as two inputs of the 4th multiplier (MUL4), the 5th d type flip flop (FD5) is used for time delay, produces G[n-1]; G[n] and y[n] as the input of the 3rd multiplier (MUL3), be used to calculate last numeral sample sequences y
Out[n], the 6th d type flip flop (FD6) make chronomere of numeral sample sequence time-delay export.
Advantage of the present invention: the present invention uses the FPGA device, the expense that the linear frequency modulation signal source of realizing by iir filter design can be saved hardware resource.Simplified the realization of linear FM signal, significantly reduced amount of calculation, the result of each recursion deposits in again in the former memory, has reduced memory space.The output digital signal directly obtains by calculating three stepping types, can reduce the spurious signal in amount of calculation and the output signal.Avoided improving and the defective of respective stored capacity increase with frequency resolution in the Direct Digital synthetic method, improved computational efficiency.
Description of drawings
Fig. 1 is theory diagram figure of the present invention;
Fig. 2 is a hardware elementary diagram of the present invention;
Fig. 3 is application principle figure of the present invention;
Fig. 4 is the not preceding linear FM signal time domain waveform of compensation of output
Fig. 5 is the time domain waveform of output compensation back linear FM signal;
Fig. 6 is the linear FM signal frequency spectrum (dashed line view) that produces of the present invention and the comparison diagram of desirable linear FM signal frequency spectrum (real diagram);
Fig. 7 is the program flow diagram of a realization of the present invention.
Embodiment
Fig. 1 is a theory diagram of the present invention, Fig. 2 is a hardware elementary diagram of the present invention: the production method of linear digital frequency modulation signal of the present invention adopts the recursion feedback system to produce basic numeral sample sequence, then the basic numeral sample sequence that is produced is carried out the amplitude compensation, making the output linear FM signal is the self-sustained oscillation signal.The generation of concrete numeral sample sequence, be to utilize auto-excitation type second order iir filter to produce basic numeral sample sequence, then the basic numeral sample sequence that is produced is carried out the amplitude compensation, making the output linear FM signal is the self-sustained oscillation signal, and hardware uses field programmable logic array to realize.
1, the principle of the inventive method:
The frequency of linear FM signal is linear change in time, is usually used in the continuous wave radar, adopts linear frequency modulation to interrupt continuous wave exactly as Wuhan University's high-frequency ground wave radar, and linear FM signal may be defined as:
F wherein
iBe the primary simulation frequency, B is the linear FM signal bandwidth, and T is the FM signal cycle.
In order to obtain the sinusoidal signal of formula (1) medium frequency linear change, we have a look unifrequent sinusoidal signal earlier and how to produce.Present most widely used sine-wave oscillator is the back-coupled generator that utilizes the positive feedback principle to constitute, and the limit of the system function of reponse system is a pair of conjugate root that is positioned at the imaginary axis, thereby impulse response is a constant amplitude sinusoid.In view of the above, the digital sine signal can be produced by second order numeral infinite impulse response filter, and this filter has a pair of conjugate pole on the imaginary axis, need not input signal, can self-oscillation.Its difference equation can be expressed as:
y[n]＝2cos(Ω)*y[n-1]-y[n-2] (2)
Wherein Ω is the limit of reponse system, for second order filter, and our given two initial values, to determine the initial phase and the amplitude of output signal:
y[0]＝C*sin(Φ) y[1]＝C*sin(Ω+Φ) (3)
Wherein Φ is an initial phase, and C is an amplitude.
The difference equation that (2) (3) two formulas of separating are determined gets output signal:
y[n]＝C*sin(nΩ+Φ) n＝2，3... (4)
From (4) formula as can be seen, Ω has represented the frequency of the Serial No. of (2) formula output, and the pass of it and analog frequency is: Ω=2 π f
c/ f
s, f wherein
cBe analog sine frequency, f
sBe sample rate.
Only need an addition when using FPGA or DSP to realize (2) formula, a reality is taken advantage of with three registers that are used to store and is got final product, and has significantly reduced amount of calculation and memory capacity.
Can find out that from (1) formula linear FM signal is the sinusoidal signal that frequency linearity changes, it is not the sinusoidal signal of single-frequency (being that frequency is constant), therefore, we can consider promptly to produce linear FM signal with the second order iir filter with the method that obtains the single frequency sinusoidal signal on the one hand; The frequency of each sample value correspondence of signal is different again on the other hand, is Ω if establish the initial number frequency
Start, the numerical frequency of n sample correspondence is Ω
n, then:
Ω
n＝Ω
start+n*ΔΩ n＝0，1，2，...，N-1 (5)
Wherein N is the sample of signal number in the linear frequency modulation cycle, and Δ Ω is a frequency interval, and then linear FM signal is Ω by numerical frequency
Final=Ω
Start+ (N-1) * Δ Ω, the frequency interval between adjacent sample is Δ Ω=(Ω in other words
Final-Ω
Start)/(N-1), (Ω
FinalBe numerical frequency) whenever obtain a sample of signal value by (2) formula like this, its frequency value corresponding all will be calculated by (5) formula.
In order to reduce amount of calculation as far as possible, the present invention uses a second order iir filter to calculate (5) and draws output signal:
A[n]＝2cos(ΔΩ)*A[n-1]-A[n-2] (6)
A[0]＝cos(Ω
start) A[1]＝cos(Ω
start+ΔΩ) (7)
(2) formula can be rewritten as like this:
y[n]＝2*A[n]*y[n-1]-y[n-2] (8)
Initial condition is:
y[0]＝C*sin(Φ) y[1]＝C*sin(Φ+Ω
start+ΔΩ)(9)
Two additions of this process need, two multiplication and six registers that are used to store.
Illustrate: if establish linear FM signal primary simulation frequency f
i=7.5MHz, the simulation cut-off frequency is f
t=33.4MHz, sample rate is f
s=90MHz, sampling N=1024 point in the linear frequency modulation cycle, then
Initial number frequency: Ω
Start=2 π * 7.5/90=0.168 π;
Adjacent sample frequency interval: Δ Ω=2 π * (33.4-7.5)/(90*1023)=0.00056 π;
The modulation signal cycle: T=1024/90 μ s=11.38 μ s.
Initial amplitude is made as C=1, and initial phase is made as Φ=0, and then by (7), (9) two formulas can get initial condition and be:
A[0]＝0.866 A[1]＝0.865 y[0]＝0 y[1]＝0.502
Bring above-mentioned initial value into (6), (8) two formula iterative computation can obtain the approximate figure sample value of linear FM signal as basic numeral sample sequence.
Fig. 4 has provided not linear FM signal time domain waveform before the compensation of output, and therefrom as can be seen, t increases in time, and waveform is more and more closeer, and promptly frequency is more and more higher, but wave-shape amplitude reduces earlier gradually, after slowly increase again.It is because y[n-1 in (8) formula that waveform is not that constant amplitude changes] with y[n-2] the sample of signal value of the different frequency of representative.Although the value of this variation can be calculated accurately, that will increase amount of calculation greatly; Noticing that the trend of changes in amplitude is approximate is index variation (exponential decrease or increase progressively), as basic numeral sample sequence.For the linear FM signal that makes output near constant amplitude, we can carry out the amplitude compensation in the output of (8) formula, the compensation sequence G[n of (by index variation) of the amplitude inverse variation that promptly multiplies each other], G[n] can provide with recursive sub equally:
Kx＝(envelop(t
max)/C
initial)^(-1/N
d) (10)
G[n]＝Kx*G[n-1] (11)
G[0]＝1 G[1]＝Kx (12)
Wherein, at the waveform interval of successively decreasing, ' envelop (t
Max) ' expression wave-shape amplitude successively decrease interval and the waveform envelope value that increases progressively interval critical point place are made as envelop (t
d), be made as N corresponding to number of samples at this moment
d, this moment C
InitialExpression the successively decrease initial value of interval waveform envelope, i.e. C
Initial=C; Increase progressively the interval at waveform, ' envelop (t
MaxThe envelope value of a linear frequency modulation cycle end sample of) ' expression is made as envelop (t
T), the corresponding sample number is that total sample number N deducts successively decrease interval sample number, i.e. N-N
d, this moment C
InitialShould be successively decrease last interval sample envelope value, i.e. envelop (t
d).In above-mentioned example of the present invention, in the interval of successively decreasing, can calculate C
Initial=1, N
d=509, corresponding envelope amplitude envelop (t
Max)=envelop (t
d)=0.7; Increase progressively in the interval, sample points is N-N
d=1024-509=515, waveform envelope amplitude envelop (t
Max)=envelop (t
T)=0.83, the C of this moment
Initial=envelop (t
d)=0.7.These values are brought into can be at interval Kx=(0.7/1) ^ (1/509)=1.007 that successively decreases in (10) formula, increasing progressively interval Kx=(0.83/0.7) ^ (1/515)=0.9997, these two values are the initial condition of conduct (12) formula respectively, utilize (11) formula iteration can obtain G[n], total last output is exactly y
Out[n]=G[n] * y[n], y[n wherein] provide by (8) formula.This compensation method will increase by two multiplication and three memory registers.
Fig. 5 has provided the time domain waveform of output compensation back linear FM signal, and therefrom as can be seen, output is near self-sustained oscillation.
Fig. 6 has provided the spectrogram (among the figure shown in the dotted line) of the linear FM signal of output, and done contrast with ideal linearity spectrum of FM signal (shown in the solid line), as can be seen, the ripple of signal envelope is less than 1dB, and the signal of generation can characterize the spectral characteristic of ideal linearity FM signal.
2, specific implementation of the present invention:
As Fig. 2, linear digital frequency modulation signal of the present invention source comprises: produce basic numeral sample sequence Y[n] auto-excitation type second order iir filter, produce sequence frequency A[n] auto-excitation type second order iir filter, produce offset G[n] multiplier, produce the numeral sample sequences y
OutThe multiplier of [n] and D/A converter.CLK is system's input clock, and the numeral sample sequence send D/A converter that digital signal is converted to analog signal output.
Numeral sample sequence of the present invention produces uses field programmable logic array FPGA or DSP to realize, uses four multipliers altogether, two adders and six d type flip flops:
Calculated rate sequence A [n] is realized by the second order iir filter that first multiplier (MUL1), first adder (SUB1), first d type flip flop (FD1) and second d type flip flop (FD2) are formed; Two of first multiplier (MUL1) are input as 2cos (Δ Ω) and A[n-1], first d type flip flop (FD1) and second d type flip flop (FD2) are used for time delay, are used for producing A[n-1 respectively] and A[n-2].Calculate the second order iir filter realization that basic numeral sample sequences y [n] is made up of second multiplier (MUL2), second adder (SUB2), 3d flip-flop (FD3) and four d flip-flop (FD4); Frequency sequence A[n] as an input of second multiplier (MUL2), 3d flip-flop (FD3) and four d flip-flop (FD4) are used for time delay, produce y[n-1 respectively] and y[n-2]; The 4th multiplier (MUL4) is used for calculating compensation sequence G[n], Kx and G[n-1] as two inputs of the 4th multiplier (MUL4), the 5th d type flip flop (FD5) is used for time delay, produces G[n-1]; G[n] and y[n] as the input of the 3rd multiplier (MUL3), be used to calculate last numeral sample sequences y
Out[n], the 6th d type flip flop (FD6) make chronomere of numeral sample sequence time-delay export.
Figure 7 shows that the program flow diagram that the present invention realizes:
Initial conditions f
i, f
t, f
sProvided the primary simulation frequency f of linear FM signal respectively
i=7.5MHz, simulation cut-off frequency f
t=33.4MHz and sample rate are f
s=90MHz; N=1024 has provided an interior sampling number of linear frequency modulation cycle; The initial amplitude C=1 of output FM signal, initial phase Φ=0.Can calculate the initial number frequency omega by initial conditions
Start, frequency interval Δ Ω, frequency modulation period T, and A[n], y[n], G[n] preceding two initial values.Initial value is brought into respectively (6), (8), (11) three can try to achieve a series of A[n in iterative], y[n] and G[n] value, last output linear FM signal y
Out[n] is by y[n], G[n] product provide: y
Out[n]=G[n] * y[n].
Fig. 3 has provided radar receiver neutral line frequency modulation signal source application principle figure.Receiver adopts " a mixing direct intermediate frequency (IF) Sampling " structure, the process of signal processing is: FMICW (the linear frequency modulation interruption continuous wave) echo-signal that enters receiver channel is through band pass filter, after curbing image frequency interference and intermediate frequency interference, send in the frequency mixer, carry out coherent demodulation with local oscillation signal, remove the frequency modulation(FM) composition in the signal, this process often is called " slope " and handles.Mixer output signal is exactly the doppler shifted signal of each radar unit in the target area, and this signal is a narrow band signal, and it amplifies through intermediate frequency, sends into after the filtering among the A/D (analog to digital converter) and carries out bandpass sampling.Sampled value is sent into and is carried out Digital Down Convert among the FPGA, signal reduction of speed rate is separated (quadrature separation) handle with I, Q, and the base band data after the processing obtains target range information through a FFT (fast fourier transform) again.At last, data are transferred to PC by usb bus (USB) and make subsequent treatment, further to obtain information such as target velocity, sea stormy waves.The clock control of whole receiver is produced by synchronization control circuit.Local oscillation signal promptly is a linear frequency modulation signal source of the present invention, and it is directly produced by the FPGA device, as the input of frequency mixer echo-signal is carried out coherent demodulation by a D/A (digital to analog converter) back.
The present invention adopts the second order iir filter to produce the numeral sample sequence, has reduced memory space, and has been easy to realize on programmable logic device such as FPGA.The linear FM signal bandwidth that produces because will satisfy Nyquist's theorem, is subjected to the restriction of sample rate; But FPGA can adopt the pipelining parallel processing, therefore can use effective bandwidth to greatest extent, and when being 90MHz as sample rate, linear FM signal bandwidth maximum can reach 45MHz.
Core of the present invention is to adopt the second order iir filter to produce the numeral sample sequence; on programmable logic device such as FPGA, realize; therefore every employing second order iir filter recursion feedback system produces the numeral sample sequence, realizes on programmable logic device, all belongs to protection scope of the present invention.
Claims (4)
1. the production method of a linear digital frequency modulation signal, comprise the generation and the D/A conversion of numeral sample sequence, it is characterized in that: utilize auto-excitation type second order iir filter to produce basic numeral sample sequence, then the basic numeral sample sequence that is produced is carried out the amplitude compensation, make output linear FM signal be the self-sustained oscillation signal, basic numeral sample sequence as shown in the formula:
y[n]＝2*A[n]*y[n-1]-y[n-2](8)
Y[n wherein] the basic numeral sample sequence of representative, two initial condition of second order filter are:
y[0]＝C*sin(Φ)?y[1]＝C*sin(Φ+Ω
start+ΔΩ)(9)
Wherein Φ is an initial phase, and C is an amplitude, Ω
StartBe the initial number frequency, Δ Ω is a frequency interval; A[n] be frequency sequence, A[n]=cos (Ω
n), Ω wherein
n=Ω
Start+ n* Δ Ω represents numerical frequency;
The amplitude compensation is that basic numeral sample sequences y [n] be multiply by a compensation sequence G[n]; G[n] provide with recursive sub:
G[n]＝Kx*G[n-1](11)
G[0]＝1G[1]＝Kx(12)
G[n wherein] representative compensation sequence, Kx represent the speed of offset variation, and Kx is provided by following formula:
Kx＝(envelop(t
max)/C
initial)^(-1/N
d)(10)
Wherein ' envelop (t
MaxLast envelope value of waveform between) ' expression compensating basin, C
InitialThe initial envelope value of waveform between the expression compensating basin, compensation increase progressively with waveform two intervals of successively decreasing by waveform and carry out respectively, and last envelope value of previous interval waveform is as the initial value of a back interval waveform envelope, N
dCorrespond respectively to the number of samples between the compensating basin; G[n] promptly be the compensation sequence that calculates, total the output of last numeral sample sequence is exactly y
Out[n]=G[n] * y[n].
2. the production method of linear digital frequency modulation signal according to claim 1 is characterized in that: produce frequency sequence A[n with an auto-excitation type second order iir filter]:
A[n]＝2cos(ΔΩ)*A[n-1]-A[n-2](6)
A[0]＝cos(Ω
start)?A[1]＝cos(Ω
start+ΔΩ)(7)
3. the production method of linear digital frequency modulation signal according to claim 1 and 2, it is characterized in that: used linear digital frequency modulation signal source comprises: numeral sample sequence generator, system clock and D/A converter, the numeral sample sequence generator comprise produce basic numeral sample sequence Y[n] auto-excitation type second order iir filter, produce frequency sequence A[n] auto-excitation type second order iir filter, produce compensation sequence G[n] multiplier, produce the numeral sample sequences y
OutThe multiplier of [n], numeral sample sequence send D/A converter that digital signal is converted to analog signal output.
4. the production method of linear digital frequency modulation signal according to claim 3, it is characterized in that: the numeral sample sequence generator in linear digital frequency modulation signal source uses field programmable logic array to realize, specifically comprises: calculated rate sequence A [n] is realized by the second order iir filter that first multiplier (MUL1), first adder (SUB1), first d type flip flop (FD1) and second d type flip flop (FD2) are formed; Two of first multiplier (MUL1) are input as 2cos (Δ Ω) and A[n-1], first d type flip flop (FD1) and second d type flip flop (FD2) are used for time delay, are used for producing A[n-1 respectively] and A[n-2]; Calculate the second order iir filter realization that basic numeral sample sequences y [n] is made up of second multiplier (MUL2), second adder (SUB2), 3d flip-flop (FD3) and four d flip-flop (FD4); Frequency sequence A[n] as an input of second multiplier (MUL2), 3d flip-flop (FD3) and four d flip-flop (FD4) are used for time delay, produce y[n-1 respectively] and y[n-2]; The 4th multiplier (MUL4) is used for calculating compensation sequence G[n], Kx and G[n-1] as two inputs of the 4th multiplier (MUL4), the 5th d type flip flop (FD5) is used for time delay, produces G[n-1]; G[n] and y[n] as the input of the 3rd multiplier (MUL3), be used to calculate last numeral sample sequences y
Out[n], the 6th d type flip flop (FD6) make chronomere of numeral sample sequence time-delay export.
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| CN101867371B (en) * | 2010-05-31 | 2012-05-09 | 西安电子科技大学 | FPGA-based method for realizing linear frequency-modulated signal |
| CN103630882B (en) * | 2013-11-22 | 2015-05-27 | 电子科技大学 | Method for realizing distributed radar waveform by using multi-slope modulation |
| CN104898096A (en) * | 2015-05-19 | 2015-09-09 | 南京航空航天大学 | Method for processing chirp signals and system |
| US10651858B2 (en) * | 2017-11-30 | 2020-05-12 | Sony Corporation | Synthesizer and phase frequency detector |
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