CN100426478C - Three-dimensional interconnection interpolator applied in system packaging and its producing method - Google Patents

Three-dimensional interconnection interpolator applied in system packaging and its producing method Download PDF

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Publication number
CN100426478C
CN100426478C CNB2005100981412A CN200510098141A CN100426478C CN 100426478 C CN100426478 C CN 100426478C CN B2005100981412 A CNB2005100981412 A CN B2005100981412A CN 200510098141 A CN200510098141 A CN 200510098141A CN 100426478 C CN100426478 C CN 100426478C
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China
Prior art keywords
back side
wafer
pattern
contact mat
passive device
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Expired - Fee Related
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CNB2005100981412A
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Chinese (zh)
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CN1929105A (en
Inventor
陈至贤
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Touch Micro System Technology Inc
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Touch Micro System Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

This invention relates to three dimensional connection plug applicator into system sealing, wherein, the plug comprises the following parts: crystal slice; at least one imbedded part and at least one connection pattern on crystal slice positive one; several holes exposed on back of crystal slice connection inner pad; back connection pattern on back of crystal slice through inner contact pad and connection pattern and parts.

Description

Be applied to three-dimensional interconnection interpolator of system in package and preparation method thereof
Technical field
The present invention relates to a kind of three-dimensional interconnection interpolator that is applied to system in package and preparation method thereof, more specifically, relate to a kind of method of utilizing wafer as three-dimensional interconnection interpolator, wherein the front of wafer is provided with the embedded passive device, and be electrically connected with the chip in the front that is attached at wafer, and chip utilize wafer the front interconnection pattern and be electrically connected with printed circuit board (PCB) via the back side of wafer, so the volume of reduction system encapsulating structure significantly.
Background technology
(system-in-package SIP) is one of most important technology in the trend of present electronic product microminiaturization to system in package.The notion of system in package is that the chip of difference in functionality is integrated and be packaged in the same encapsulating structure, can significantly reduce the volume of individual packages in comparison, and then make electronic product have high efficiency and multi-functional advantage, and satisfy microminiaturized demand simultaneously.
Please refer to Fig. 1.Fig. 1 is the schematic diagram of prior art system encapsulating structure.As shown in Figure 1, prior art system encapsulating structure 10 comprises: base plate for packaging 12; A plurality of chips 14 with difference in functionality are attached at the surface of base plate for packaging 12; And sealant (figure does not show).Base plate for packaging 12 comprises a plurality of contact mats 16, and chip 14 also comprises a plurality of contact mats 18, and is electrically connected to the contact mat 16 of base plate for packaging 12 by lead 20.In addition, prior art system encapsulating structure 10 also comprises at least one passive device 22, is attached on the contact mat 16 of base plate for packaging 12, forms complete circuit design further to be electrically connected with chip 14.
Yet as mentioned above, because the passive device of prior art system encapsulating structure utilizes surface mount technology to be attached on the base plate for packaging, be electrically connected to chip by contact mat and lead 20 again, therefore can produce signal attenuation, passive device has also occupied the segment space of base plate for packaging simultaneously, and causes the volume of prior art system encapsulating structure further to reduce.
Given this, the objective of the invention is to solve the problem of prior art system encapsulating structure signal attenuation, and reduce the volume of system packaging structure simultaneously.
Summary of the invention
Main purpose of the present invention is to provide a kind of three-dimensional interconnection interpolator that is applied to system in package and preparation method thereof, to solve the shortcoming of above-mentioned prior art.
For achieving the above object, the invention discloses the method that a kind of making is applied to the three-dimensional interconnection interpolator of system in package.Said method comprises the following steps:
Provide wafer, and described wafer comprises the front and the back side;
Form at least one embedded passive device and at least one interconnection pattern on the front of described wafer, described embedded passive device is electrically connected with described interconnection pattern, and described interconnection pattern comprises a plurality of interior contact mats;
Form a plurality of holes at the back side of described wafer, and described hole exposes described interior contact mat; And
Form the back side at the back side of described wafer and connect pattern, and described back side connection pattern is electrically connected with described passive device with described interconnection pattern by contact mat in described.
For reaching above-mentioned purpose, the invention also discloses a kind of three-dimensional interconnection interpolator that is applied to system in package.Above-mentioned three-dimensional interconnection interpolator comprises:
Wafer, and described wafer comprises the front and the back side;
At least one embedded passive device and at least one interconnection pattern are arranged on the front of described wafer, and described embedded passive device is electrically connected with described interconnection pattern, and described interconnection pattern comprise a plurality of in contact mats;
A plurality of holes, position are at the back side of described wafer, and described hole exposes described interior contact mat; And
The back side connects pattern, is located at the back side of described wafer, and described back side connection pattern is electrically connected with described passive device with described interconnection pattern by contact mat in described.
For a nearlyer step is understood feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
Fig. 1 is the schematic diagram of prior art system encapsulating structure.
Fig. 2 to Figure 16 makes the method schematic diagram of the three-dimensional interconnection interpolator that is applied to system in package for the preferred embodiments of the present invention.
Description of reference numerals
10 system packaging structures, 12 base plate for packaging
14 chips, 16 contact mats
18 contact mats, 20 leads
22 passive devices, 50 wafers
52 connect pattern 54 embedded passive devices
56 front contact mats, 58 insulating barriers
62 mask patterns, 64 holes
Contact mat 68 insulating barriers in 66
70 back sides connect pattern 72 back side contact mats
74 protective layers, 76 protective layers
78 tin balls, 80 chips
82 contact mats, 84 adhesion layers
86 leads, 88 front protecting layers
90 transparent protective covers, 92 printed circuit board (PCB)s
Embodiment
Please refer to Fig. 2 to Figure 15.Fig. 2 to Figure 15 makes the method schematic diagram of the three-dimensional interconnection interpolator that is applied to system in package for the preferred embodiments of the present invention.What deserves to be explained is that method of the present invention is a methods for wafer-level packaging, and for convenience of description, in Fig. 2 to Figure 15, only depict the making of single three-dimensional interconnection interpolator.As shown in Figure 2, at first, wafer 50 is provided, silicon wafer for example, and utilize technology such as deposition, photoetching and etching to form at least one interconnection pattern 52 and at least one embedded passive device (embedded passive device) 54 in the front of wafer 50, wherein interconnection pattern 52 is electrically connected with embedded passive device 54, and interconnection pattern 52 also comprises a plurality of fronts contact mat 56.In addition, the numbers of the position of interconnection pattern 52, resistance value and front contact mat 56 etc. are designed according to the chip specification that desire connects, and embedded passive device 54 can be resistance, electric capacity and inductance etc., and its position, quantity and specification etc. then determine according to circuit design.Subsequently, form insulating barrier 58 in the front of wafer 50, for example silicon dioxide or silicon nitride utilize photoetching and etching technique to remove partial insulative layer 58 with exposed front surface contact mat 56 simultaneously.
As shown in Figure 3, carry out wafer grinding technology according to product demand, by the back side of wafer 50 thickness that being reduced to of wafer 50 is required, for example between 20 to 500 microns, wherein wafer grinding technology can be passed through various thinning techniques, for example grinding technics, glossing, CMP (Chemical Mechanical Polishing) process, wet etching process or plasma etch process etc., or the appointing to set up jointly and reached of above-mentioned five kinds of technologies.
As Fig. 4 and shown in Figure 5, then form mask pattern 62 at the back side of wafer 50, and utilize etching technique to form a plurality of holes 64 at the back side of wafer 50, to expose the interior contact mat 66 of interconnection pattern 52, wherein what deserves to be explained is different according to the thickness of wafer 50 and hole 64, the mode that forms hole 64 is difference to some extent also.In the present embodiment, utilize the isotropism wet etching process, make hole 64 have the sidewall of circular arc, be beneficial to the making that the follow-up back side connects pattern, and if the thickness of wafer 50 is thicker or hole 64 between apart from nearer, then can't only utilize the isotropism wet etching process to finish the making in hole 64, under this situation, must be as shown in Figure 5, remove mask pattern 62, and then utilize the anisotropic dry etch process, for example plasma etch process makes hole 64 expose the interior contact mat 66 of interconnection pattern 52.
In addition, the mode that forms hole 64 is not limited to the above-mentioned practice, and also can utilize anisotropic wet etch technology, for example utilize KOH (potassium hydroxide) etching solution, EDP (ethylenediamine-pyrocatechol-water) etching solution and TMAH (tetramethyl ammoniumhydroxide) etching solution etc., or utilize plasma etch process, make hole 64 have skewed sidewall, as shown in Figure 6.
The practice of following step hookup 4 and Fig. 5.As shown in Figure 7, then form insulating barrier 68 at the back side of wafer 50, for example silicon dioxide or silicon nitride, and utilize photoetching and etching technique to remove partial insulative layer 68, with contact mat 66 in exposing, wherein the effect of insulating barrier 68 is to avoid the back side of follow-up formation to connect pattern generating leakage current or short circuit condition.Then, form the back side again and connect pattern 70 on insulating barrier 68, wherein connection pattern 70 in the back side is electrically connected with interior contact mat 66.
As shown in Figure 8, connect in the back side again and form protective layer 74 on the pattern 70, for example silicon dioxide, silicon nitride or silicon oxynitride etc., and utilize photoetching and etching technique to remove partial protection layer 74, with the back side contact mat 72 of exposed backside connection pattern 70.
As shown in Figure 9; when the thinner thickness of wafer 50; except above-mentioned protective layer 74; also can further on protective layer 74, form another comparatively tough protective layer 76 again; its material can be as benzocyclobutene (BCB) and polyimides polymeric materials such as (polyimide); and insert in the hole 64 to strengthen the intensity of wafer 50, utilize photoetching and etching technique exposed backside contact mat 72 subsequently again.What deserves to be explained is except that the above-mentioned practice, also can form protective layer 74 and protective layer 76 earlier in regular turn, utilize same photoetching and etch process exposed backside contact mat 72 again.
As shown in figure 10, then form a plurality of tin balls 78 on the contact mat 72 overleaf, so that wafer 50 is welded on the printed circuit board (PCB) (figure does not show).The above-mentioned back process of making the three-dimensional interconnection interpolator that is applied to system in package for the present invention.Follow-up explanation then continues to instruct the present invention to make and is applied to the positive technology of the three-dimensional interconnection interpolator of system in package.
As shown in figure 11, then provide at least one chip 80, and chip 80 comprises a plurality of contact mats 82, then chip 80 is attached on the surface of insulating barrier 58 by adhesion layer 84.As shown in figure 12, utilize lead 86 to be electrically connected the contact mat 82 of chip 80 and the interior contact mat 66 of interconnection pattern 52, make chip 80 be electrically connected with interconnection pattern 52 and embedded passive device 54, and can further be electrically connected with printed circuit board (PCB) (figure does not show) again via back side connection pattern 70, constitute complete circuit.What deserves to be explained is that present embodiment utilization lead-in wire bonding mode connects chip 80 and interconnection pattern 52, but application of the present invention is not limited thereto and also can utilizes flip chip to be connected.
As shown in figure 13, then form front protecting layer 88 again on insulating barrier 58 and chip 80, wherein front protecting layer 88 can be polymeric material, and for example benzocyclobutene and polyimides etc. are to protect chip 80.As fruit chip 80 surfaces the part that can't be covered is arranged in addition; for example optics and micro electro mechanical device; then also can on chip 80, form front protecting layer 88 in the part; for example utilize screen printing mode; and utilize transparent protective cover 90 in the position that does not form front protecting layer 88; for example the glass protection lid is covered, as shown in figure 14.
As shown in figure 15, then remove the unnecessary protective layer 76 (being positioned at part beyond the hole 64) in the back side of wafer 50, and carry out cutting technique to form a plurality of system packaging structures.As shown in figure 16, the back side with wafer 50 places on the printed circuit board (PCB) 92 at last, and carries out reflow process and to utilize tin ball 78 wafer 50 is welded on the printed circuit board (PCB) 92, thereby finishes the making that the present invention is applied to the three-dimensional interconnection interpolator of system in package.
In sum, the present invention's three-dimensional interconnection interpolator of being applied to system in package and preparation method thereof has following advantage:
(1) utilizes wafer as three-dimensional interconnection interpolator, simultaneously the embedded passive element manufacturing can be reduced problem of signal attenuation and reduce the volume of system packaging structure in wafer;
(2) use wafer-class encapsulation, can promote production efficiency;
(3) making of embedded passive device and wafer-class encapsulation are carried out respectively at the front and the back side of wafer, and chip has the protection of front protecting layer, easily technology reproduction.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.

Claims (18)

1, a kind of making is applied to the method for the three-dimensional interconnection interpolator of system in package, comprising:
Provide wafer, and described wafer comprises the front and the back side;
Form at least one embedded passive device and at least one interconnection pattern in the front of described wafer, described embedded passive device is electrically connected with described interconnection pattern, and described interconnection pattern comprises a plurality of interior contact mats;
Form a plurality of holes at the back side of described wafer, and described hole exposes described interior contact mat; And
Form the back side at the back side of described wafer and connect pattern, and described back side connection pattern is electrically connected with described passive device with described interconnection pattern by contact mat in described.
2, the method for claim 1, the described back side that also is included in described wafer forms before the described hole, carries out wafer grinding technology earlier, via the described wafer of the thinning back side of described wafer.
3, method as claimed in claim 2, wherein, described wafer grinding technology comprises optionally carries out grinding technics, glossing, CMP (Chemical Mechanical Polishing) process, wet etching process or plasma etch process, or carries out appointing of above-mentioned five kinds of technologies and set up jointly.
4, the method for claim 1, wherein described hole utilizes at the described back side and forms mask pattern, and carries out the isotropism wet etching process and made, and the sidewall of each described hole with circular arc.
5, method as claimed in claim 4, also be included in described isotropism wet etching process after, remove described mask pattern, carry out the anisotropic dry etch process again so that each described hole expose described in contact mat.
6, the method for claim 1, wherein described hole utilizes at the described back side and forms mask pattern, and carries out anisotropic wet etch or plasma etch process is made, and each described hole has skewed sidewall.
7, the method for claim 1 also is included in the described back side and connects after the pattern formation, connects pattern at the described back side and is deposited into few back-protective layer.
8, method as claimed in claim 7, wherein, the material of described back-protective layer is selected from least a of silicon dioxide, silicon nitride, nitrogen base silicon and polymeric material.
9, method as claimed in claim 7; wherein; the described back side connects pattern and also comprises a plurality of back sides contact mat, and also is included in a plurality of openings corresponding to described back side contact mat of formation in the described back-protective layer after the formation of described back-protective layer, is used to expose described back side contact mat.
10, method as claimed in claim 9 comprises that also the back side contact mat with described wafer is welded on the printed circuit board (PCB), and described interconnection pattern is electrically connected with described printed circuit board (PCB) by described back side contact mat with described embedded passive device.
11, the method for claim 1, wherein, described interconnection pattern also comprises a plurality of fronts contact mat, after described method comprises that also described embedded passive device and described interconnection pattern form, on described embedded passive device and described interconnection pattern, form insulating barrier, and described insulating barrier also comprises a plurality of openings, is used to expose described front contact mat.
12, method as claimed in claim 11 also is included on the described insulating barrier and attaches chip, and described chip is electrically connected with described interconnection pattern and described embedded passive device by described front contact mat.
13, method as claimed in claim 12 also is included in and forms the front protecting layer on the described insulating barrier.
14, method as claimed in claim 13, the material of wherein said front protecting layer comprises polymeric material.
15, method as claimed in claim 13, wherein said front protecting layer comprises at least one transparent protective cover in addition, is positioned on the described chip.
16, a kind of three-dimensional interconnection interpolator that is applied to system in package comprises:
Wafer, and described wafer comprises the front and the back side;
At least one embedded passive device and at least one interconnection pattern are arranged on the described front of described wafer, and described embedded passive device is electrically connected with described interconnection pattern, and described interconnection pattern comprise a plurality of in contact mats;
A plurality of holes, position are at the back side of described wafer, and described hole exposes described interior contact mat; And
The back side connects pattern, is located at the back side of described wafer, and described back side connection pattern is electrically connected with described passive device with described interconnection pattern by contact mat in described.
17, as claim the 16 described three-dimensional interconnection interpolators, wherein, the described back side connects pattern and also comprises a plurality of back sides contact mat, be soldered on the printed circuit board (PCB) in order to the described back side, and described interconnection pattern is electrically connected with described printed circuit board (PCB) by described back side contact mat with described embedded passive device described wafer.
18, as claim the 16 described three-dimensional interconnection interpolators, wherein, described embedded passive device and described interconnection pattern also comprise a plurality of fronts contact mat, and described front contact mat is electrically connected with the chip that at least one is attached at described front.
CNB2005100981412A 2005-09-08 2005-09-08 Three-dimensional interconnection interpolator applied in system packaging and its producing method Expired - Fee Related CN100426478C (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW494560B (en) * 2001-04-16 2002-07-11 Megic Corp Ceramic package
US20040178491A1 (en) * 1997-12-18 2004-09-16 Salman Akram Method for fabricating semiconductor components by forming conductive members using solder
TWI234261B (en) * 2004-09-10 2005-06-11 Touch Micro System Tech Method of forming wafer backside interconnects

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040178491A1 (en) * 1997-12-18 2004-09-16 Salman Akram Method for fabricating semiconductor components by forming conductive members using solder
TW494560B (en) * 2001-04-16 2002-07-11 Megic Corp Ceramic package
TWI234261B (en) * 2004-09-10 2005-06-11 Touch Micro System Tech Method of forming wafer backside interconnects

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
TW234261B B 2005.06.11
TW494560B B 2002.07.11

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