The application requires to merge its whole contents at this by reference in the korean patent application 10-2004-95979 of submission on November 22nd, 2004 and right of priority and the rights and interests of 10-2004-95980.
Embodiment
In the following detailed description, with way of illustration, illustrate and described specific example embodiment of the present invention. should be realized that as those of ordinary skill in the art, as long as just can make amendment to described example embodiment in various manners without departing from the spirit and scope of the present invention. therefore, accompanying drawing and description are considered to illustrative in essence, rather than restrictive.
Fig. 2 shows the structure of the active display of first embodiment of the present invention. and with reference to Fig. 2, this active display comprises image-display units 100a, data driver 200a and scanner driver 300a.
Image-display units 100a be included in the multi-strip scanning line S0 that arranges in the line direction, S1, S2 ... .Sn-1 and Sn, many first launch-control line E11, E12 that in line direction, arrange ... .E1n-1 and E1n and many second launch-control line E21, E22 ... .E2n-1 and E2n, many data line D1, D2 that in column direction, arrange ... .., Dm-1 and Dm, be used for providing many pixel power lead (not shown) and a plurality of image element circuit 110a of pixel power (pixel power) from the pixel power supply.In the present embodiment, the first and second OLED (not shown) are connected with each image element circuit 110a.
Will be from sweep trace S0, S1, S2, ... .Sn-1 and Sn, data line D1, D2, ... .., Dm-1 and Dm, and the next sweep signal of pixel power lead transmission, data-signal and pixel power are transferred to image element circuit 110a, thereby the transistor seconds (not shown) that comprises in image element circuit 110a produces the drive current corresponding with data-signal. according to passing through the first launch-control line E11, E12, ... .E1n-1 and E1n and the second launch-control line E21, E22, ... first and second emissioning controling signals of .E2n-1 and E2n transmission, thus drive current is transferred to the OLED display image.
First and second OLED are with an image element circuit 110a connection and be placed on different rows, same column. the color that first and second OLED emission is identical.
Therefore, owing to electric current is offered two OLED by an image element circuit 110a, promptly, first and second OLED, thereby so can reduce the aperture ratio that the quantity of image element circuit 110a improves image-display units 100a. because first and second OLED launch identical color and are placed on identical listing, so, and can easily carry out gamma correction by a data line input same color data-signal.
With data driver 200a and data line D1, D2 ... .., Dm-1 are connected with Dm to give image-display units 100a. with data signal transmission
Scanner driver 300a be formed on image-display units 100a a side and with sweep trace S0, S1, S2, ... .Sn-1 and Sn, the first launch-control line E11, E12, ... .E1n-1 and E1n and the second launch-control line E21, E22, ... .E2n-1 is connected with E2n, to provide the sweep signal and first and second emissioning controling signals to image-display units 100a, therefore sequentially select each row of image-display units 100a. then, by data driver 200a data-signal is put on selected row, thereby image element circuit 110a comes according to data-signal and first and second emissioning controling signal luminous.
Fig. 3 shows the circuit diagram according to first embodiment of the pixel of the active display of Fig. 2 of the present invention. and with reference to Fig. 3, pixel comprises image element circuit (for example image element circuit 110a) and OLED.
Image element circuit comprises driving circuit 111a, the first on-off circuit 112a and second switch circuit 113a.Driving circuit 111a comprises that the first, second, third, fourth, the 5th and the 6th transistor M11, M21, M31, M41, M51 and M61 and the capacitor Csta. first on-off circuit 112a comprise that the 7th transistor M71. second switch circuit 113a comprises that the 8th each transistor of transistor M81. all comprises source electrode, drain and gate. capacitor Csta comprises first electrode and second electrode.
Because first to the 8th transistor M11 does not have the physics difference to drain electrode and the source electrode of M81, so each source electrode and drain electrode can be called first electrode and second electrode.
The source electrode of the first transistor M11 is connected with first node A1, the drain electrode of the first transistor M11 is connected with Section Point B1, and the grid of the first transistor M11 is connected with the 3rd node C1, thereby according to the voltage of the 3rd node C1, electric current flows to Section Point B1. from first node A1
The source electrode of transistor seconds M21 is connected with data line Dm, the drain electrode of transistor seconds M21 is connected with Section Point B1, the grid of transistor seconds M21 is connected with the first sweep trace Sn, thereby transistor seconds M21 carries out switching manipulation optionally will put on Section Point B1. from the data-signal that data line Dm transmission comes according to the first sweep signal sn by first sweep trace Sn transmission
The source electrode of the 3rd transistor M31 is connected with the 3rd node C1, the drain electrode of the 3rd transistor M31 is connected with first node A1, and the grid of the 3rd transistor M31 is connected with the first sweep trace Sn, thereby make the electromotive force of first node A1 equate with the electromotive force of the 3rd node C1 by the first sweep signal sn by first sweep trace Sn transmission. therefore, the first transistor M11 can be carried out similar diode connection so that electric current (in a direction) the first transistor M11. flows through
The source electrode of the 4th transistor M41 is connected with the second sweep trace Sn-1 with grid, and the drain electrode of the 4th transistor M41 is connected with the 3rd node C1, thereby it is the second sweep signal sn-1 that the 4th transistor M41 is transferred to the 3rd node C1. initialize signal with initializing signal, it is imported be chosen in the row of the input first sweep signal sn with delegation before the row of selecting. just, the row that second sweep trace Sn-1 indication and the first sweep trace Sn are attached thereto is the sweep trace that is connected of the row of delegation before.
The source electrode of the 5th transistor M51 is connected with pixel power supply Vdd, the drain electrode of the 5th transistor M51 is connected with Section Point B1, and the grid of the 5th transistor M51 is connected with the first launch-control line E1n, thereby the 5th transistor M51 comes optionally the pixel power of pixel power supply Vdd is put on Section Point B1 according to the first emissioning controling signal e1n by first launch-control line E1n transmission.
The source electrode of the 7th transistor M71 is connected with first node A1, the drain electrode of the 7th transistor M71 is connected with an OLED (being OLED11), and the grid of the 7th transistor M71 is connected with the first launch-control line E1n, thereby the 7th transistor M71 will be according to putting on an OLED by the electric current of first node A1 input by the first emissioning controling signal e1n of first launch-control line E1n transmission, and promptly OLED 11.
The source electrode of the 6th transistor M61 is connected with pixel power supply Vdd, the drain electrode of the 6th transistor M61 is connected with Section Point B1, and the grid of the 6th transistor M61 is connected with the second emissioning controling signal E2n, thereby the 6th transistor M61 comes optionally the pixel power of pixel power supply Vdd is put on Section Point B1. according to the second emissioning controling signal e2n by second emissioning controling signal E2n transmission
The source electrode of the 8th transistor M81 is connected with first node A1, the drain electrode of the 8th transistor M81 is connected with the 2nd OLED (being OLED 21), and the grid of the 8th transistor M81 is connected with the second launch-control line E2n, thereby the 8th transistor M81 puts on the 2nd OLED according to the second emissioning controling signal e2n by second launch-control line E2n transmission with the electric current by first node A1 input, and promptly OLED 21.
First electrode of capacitor Csta is connected with pixel power supply Vdd, and second electrode of capacitor Csta is connected with the 3rd node C1, thereby comes initialization capacitor Csta. capacitor Csta to keep voltage one preset time of the grid that is applied in the first transistor M11 through the signal that the 4th transistor M41 transmits by initialization.
The OLED of the pixel of Fig. 3 comprises an OLED (being OLED 11) and the 2nd OLED (being OLED 21). an OLED (being OLED 11) is connected with the 8th transistor M81 with the 7th transistor M71 respectively with the 2nd OLED (being OLED 21), with received current. come the input of Control current by the first launch-control line E1n and the second launch-control line E2n. and an OLED (being OLED 11) and the 2nd OLED (being OLED 21) are placed on different rows, same column.
Fig. 4 shows the circuit diagram of second embodiment of pixel of the active display of Fig. 2. and with reference to Fig. 4, pixel comprises an image element circuit and a plurality of OLED.
Image element circuit comprises that driving circuit 111b, the first on-off circuit 112b and second switch circuit 113b. driving circuit 111b comprise that the first, second, third, fourth, the 5th and the 6th transistor M12, M22, M32, M42, M52 and M62 and the capacitor Cstb. first on-off circuit 112b comprise that the 7th transistor M72. second switch circuit 113b comprises that the 8th each transistor of transistor M82. comprises source electrode, drain and gate. capacitor Cstb comprises first electrode and second electrode.
Because first to the 8th transistor M12 does not have the physics difference to source electrode and the drain electrode of M82, so each source electrode and drain electrode can be called first electrode and second electrode.
The drain electrode of the first transistor M12 is connected with first node A2, the source electrode of the first transistor M12 is connected with Section Point B2, and the grid of the first transistor M12 is connected with the 3rd node C2, thereby electric current flows to Section Point B2 according to the voltage of the 3rd node C2 from first node A2.
The source electrode of transistor seconds M22 is connected with data line Dm, the drain electrode of transistor seconds M22 is connected with first node A2, and the grid of transistor seconds M22 is connected with the first sweep trace Sn, thereby transistor seconds M22 carries out switching manipulation according to the first sweep signal sn by first sweep trace Sn transmission, optionally will put on first node A2. by data line Dm data signals transmitted
The source electrode of the 3rd transistor M32 is connected with Section Point B2, the drain electrode of the 3rd transistor M32 is connected with the 3rd node C2, and the grid of the 3rd transistor M32 is connected with the first sweep trace Sn, thereby make that by the first sweep signal sn electromotive force of Section Point B2 is identical with the electromotive force of the 3rd node C2 through first sweep trace Sn transmission. therefore, the first transistor M12 can work in the diode mode, and the first transistor M12. flows through to make electric current (in a direction)
The source electrode of the 4th transistor M42 is connected with the anode electrode of OLED 22, the grid of the 4th transistor M42 is connected with the second sweep trace Sn-1, and the drain electrode of the 4th transistor M42 is connected with the 3rd node C2. according to the second sweep signal sn-1 by second sweep trace Sn-1 transmission, when not having electric current to flow to the 3rd node C2 by OLED 22, the 4th transistor M42 applies voltage between OLED22 and cathode electrode voltage Vss, and the voltage between use OLED22 and the cathode voltage Vss is as initializing signal.
The source electrode of the 5th transistor M52 is connected with pixel power supply Vdd, the drain electrode of the 5th transistor M52 is connected with Section Point B2, and the grid of the 5th transistor M52 is connected with the first launch-control line E1n, thereby the 5th transistor M52 comes optionally the pixel power of pixel power supply Vdd is put on Section Point B2 according to the first emissioning controling signal e1n by first launch-control line E1n transmission.
The source electrode of the 6th transistor M62 is connected with pixel power supply Vdd, the drain electrode of the 6th transistor M62 is connected with Section Point B2, and the grid of the 6th transistor M62 is connected with the second emissioning controling signal E2n, thereby the 6th transistor M62 comes optionally the pixel power of pixel power supply Vdd is put on Section Point B2. according to the second emissioning controling signal e2n by second launch-control line E2n transmission
The source electrode of the 7th transistor M72 is connected with first node A2, the drain electrode of the 7th transistor M72 is connected with an OLED (being OLED12), and the grid of the 7th transistor M72 is connected with the first launch-control line E1n, thereby the 7th transistor M72 puts on an OLED (being OLED12) according to the first emissioning controling signal e1n by first launch-control line E1n transmission with the electric current by first node A2 input.
The source electrode of the 8th transistor M82 is connected with first node A2, the drain electrode of the 8th transistor M82 is connected with the 2nd OLED (being OLED22), and the grid of the 8th transistor M82 is connected with the second launch-control line E2n, thereby the 8th transistor M82 puts on the 2nd OLED (being OLED22) according to the second emissioning controling signal e2n by second launch-control line E2n transmission with the electric current by first node A2 input.
First electrode of capacitor Cstb is connected with pixel power supply Vdd and second electrode of capacitor Cstb is connected with the 3rd node C2, thus by initialization through the signal of the 4th transistor M42 transmission with capacitor Cstb initialization. capacitor Cstb keeps a preset time with the grid voltage of the first transistor M12.
The OLED of the pixel of Fig. 4 comprises an OLED (being OLED 12) and the 2nd OLED (being OLED 22). an OLED (being OLED 12) is connected with the 8th transistor M82 with the 7th transistor M71 respectively with the 2nd OLED (being OLED 22), with received current. come the input of Control current by the first launch-control line E1n and the second launch-control line E2n. and an OLED (being OLED 12) and the 2nd OLED (being OLED 22) are placed on different rows, same column.
Fig. 5 shows the sequential chart of operation of the pixel of Fig. 3 and 4. with reference to Fig. 5, operate each pixel by the first sweep signal sn, the second sweep signal sn-1, the first emissioning controling signal e1n and the second emissioning controling signal e2n. the division of operations of pixel is an OLED wherein, be the luminous very first time section Ta1 of OLED1 (for example OLED11 or OLED12) and wherein the 2nd OLED, the i.e. second luminous time period Ta2. of OLED2 (for example OLED21 or OLED22)
In very first time section Ta1, when with the first sweep signal sn, the first emissioning controling signal e1n, at first the second sweep signal sn-1 is transformed to low level from high level when all maintaining high level with each of the second emissioning controling signal e2n, thereby conducting the 4th transistor M4 (for example M41 or M42). therefore, initializing signal is transferred to the 3rd node C (for example C1 or C2) with initialization capacitor Cst (for example Csta or Cstb). at this moment, in Fig. 3, form initializing signal by the second sweep signal sn-1. in Fig. 4, when the 7th and the 8th transistor M7 (for example M72) and M8 (for example M82) being ended, form initializing signal by the voltage that is applied to OLED (for example OLED22) by the first and second emissioning controling signal e1n and e2n.
Then, when in very first time section Ta1 with the second sweep signal sn-1 after low level is transformed to high level, when each of the first and second emissioning controling signal e1n and e2n is all maintained high level, the first sweep signal sn is transformed to low level from high level, thereby with the second and the 3rd transistor M2 (for example M21 or M22) and M3 (for example M31 or M32) conducting. when with the second and the 3rd transistor M2 and M3 conducting, make the electromotive force of first node A (for example A1) or Section Point B (for example B2) equate, thereby electric current is flowed through with the first transistor M1 (for example M11 or M12) of diode operation with the electromotive force of the 3rd node C (for example C1 or C2); Thereby flow through by electric current wherein, with the first transistor M1 of diode operation, will put on the 3rd node C1 by the data line data signals transmitted; Thereby and will put on second electrode of capacitor Cst with the poor corresponding voltage between the threshold voltage of the voltage of data-signal and the first transistor M.
The first sweep signal sn is transformed to high level and is maintaining high level after one schedule time, when the first emissioning controling signal e1n is transformed to low level and maintains low level during one schedule time, at the first emissioning controling signal e1n is low level simultaneously with the first sweep signal sn, the second sweep signal sn-1, all maintain high level with each of the second emissioning controling signal e2n. at this moment, by the first emissioning controling signal e1n conducting the 5th and the 7th transistor M5 (for example M51 or M52) and M7 (for example M71 or M72), thereby will be applied between the grid and source electrode of the first transistor M1 by the voltage that equation 1 obtains.
[equation 1]
Vgs=Vdd-(Vdata-|Vth|)
Wherein, Vgs, Vdd, Vdata and Vth are illustrated respectively in source electrode and the voltage between the grid, pixel supply voltage, the voltage of data-signal and the threshold voltage of the first transistor M1 of the first transistor M1.
The 7th transistor M7 is switched on, thereby the electric current that is obtained by equation 2 flows to OLED OLED1.
[equation 1]
I wherein
OLED, Vsg, Vdd, Vth and Vdata represent to flow to the threshold voltage of the electric current of OLED OLED1, the voltage that is applied to the grid of the first transistor M1, pixel power source voltage, the first transistor M1 and the voltage of data-signal respectively.
Therefore, shown in equation 2, regardless of the threshold voltage of the first transistor M1, electric current all flows to an OLED, i.e. OLED1.
At the second time period Ta2, the second sweep signal sn-1 be in once more low level with initialization capacitor Cst after, the first sweep signal sn is in low level data-signal is sent to first node A (for example A1 or A2). because the 3rd transistor M3 electric current flows through with the first transistor M1 of diode mode work, thereby store voltages that will be corresponding with the voltage of data-signal applies the voltage that obtains by equation 1 in capacitor Cst and between the source electrode of the first transistor M1 and grid.
Then, when the second emissioning controling signal e2n maintains low level one preset time, the 6th and the 8th transistor M6 (for example M61 or M62) and M8 (for example M81 or M82) thus being switched on the electric current that obtains by equation 2 flows to the 2nd OLED, i.e. OLED2.
Therefore, first and second OLED that are connected with an image element circuit, promptly OLED1 and OLED2 are sequentially luminous.
Fig. 6 shows wherein the sequential chart of operation of situation that forms the pixel of Fig. 3 and 4 with nmos pass transistor rather than PMOS transistor. with reference to Fig. 6, operate each pixel by the first sweep signal sn, the second sweep signal sn-1, the first emissioning controling signal e1n and the second emissioning controling signal e2n. the division of operations of pixel is luminous very first time section Tb1 of an OLED (for example OLED11 or OLED12) wherein and the second luminous time period Tb2. of the 2nd OLED (for example OLED21 or OLED22) wherein
Fig. 7 shows the sequential chart of the luminescence process of active display according to the embodiment of the present invention. with reference to Fig. 7, with the serial input data division of signal is the first data-signal d1 that is input to odd-numbered line, d3, ... .dm-3 and dm-1 and the second data-signal d2 that is input to even number line, d4, ... .dm-2 and dm. are when exporting the first data-signal d1 from data driver (for example data driver 200a), d3, ... .dm-3 and dm-1 and when being input to odd-numbered line, with the second data-signal d2, d4, ... .dm-2 and dm (for example are input to data driver, data driver 200a). here, number between 1 and the numeral of line number of indication active display between. wherein the luminous time period of odd-numbered line is called first son, and wherein the luminous time period of even number line is called second son. a frame comprises first son and the second son field.
In operation, at first according to sweep signal (for example s1, s2, s3 ... .. and sn) with the first data-signal d1, d3 ... .dm-3 and dm-1 sequentially are input to odd-numbered line. at this moment, sequentially import first emissioning controling signal (for example e11, e12, e13....e1n), thereby the OLED in each image element circuit (for example OLED11 or OLED12) is luminous, therefore odd-numbered line is luminous. therefore, with reference to Fig. 8 A, the first son field is luminous shown in Fig. 8 A.
Then, according to sweep signal with the second data-signal d2, d4 ... .dm-2 and dm are input to even number line in proper order. at this moment, second emissioning controling signal sequentially is input to even number line, thereby the 2nd OLED in each image element circuit (for example OLED21 or OLED22) is luminous, therefore even number line is luminous. therefore, with reference to Fig. 8 B, the second son field is luminous shown in Fig. 8 B.
When the first and second son fields were luminous, all OLED were luminous to finish a frame.
Fig. 9 shows the structure of the active display of second embodiment of the present invention. and with reference to Fig. 9, this active display comprises image-display units 100b, data driver 200b and scanner driver 300b.
Image-display units 100b comprises a plurality of image element circuit 110b, the a plurality of sweep trace S1 that in line direction, arrange, S2, ... Sn-1 and Sn, many first launch-control line E11 that in line direction, arrange, E12, ... .E1n-1 and E1n, many second launch-control line E21, E22, ... .E2n-1 and E2n, many articles the 3rd launch-control line E31, E32, ... .E3n-1 and E3n and many articles the 4th launch-control line E41, E42, ... .E4n-1 and E4n, many data line D1 that in column direction, arrange, D2, ... Dm-1 and Dm, and many pixel power lead (not shown) that are used to provide pixel power. the pixel power lead receives pixel power from the external pixels power supply that pixel power is provided.
According to from sweep trace S1, S2 ... sweep signal and sweep signal that Sn-1 and Sn transmission comes, will from data line D1, D2 ... the data signal transmission that Dm-1 and Dm transmission comes is in image element circuit 110b. image element circuit 110b produces the electric current corresponding with data-signal, according to from the first launch-control line E11, E12 ... .E1n-1 and E1n to the four launch-control line E41, E42 ... the first, second, third and the 4th emissioning controling signal that .E4n-1 and E4n transmission comes, thus with this current delivery to the OLED display image.
With data driver 200b and data line D1, D2 ... Dm-1 be connected with Dm with data signal transmission to image-display units 100b. data driver 200b sequentially with red and green, green and blue or blue and red data transmission to a data line.
Scanner driver 300b be formed on image-display units 100b a side and with multi-strip scanning line S1, S2 ... Sn-1 and Sn and many first launch-control line E11, E12 ... .E1n-1 and E1n to many articles the 4th launch-control line E41, E42 ... .E4n-1 is connected with E4n, thereby sweep signal and the first, second, third and the 4th emissioning controling signal are transferred to image-display units 100b.
Figure 10 shows the structure according to the active display of third embodiment of the invention. and with reference to Figure 10, active display comprises image-display units 100c, data driver 200c and scanner driver 300c.
Image-display units 100c comprises a plurality of image element circuit 110c, four OLED (not shown) that are connected with each image element circuit 110c, the multi-strip scanning line S0 that in line direction, arranges, S1, S2, ... Sn-1 and Sn, many first launch-control line E11 that in line direction, arrange, E12, ... .E1n-1 and E1n, many second launch-control line E21, E22, ... .E2n-1 and E2n, many articles the 3rd launch-control line E31, E32, ... .E3n-1 and E3n and many articles the 4th launch-control line E41, E42, ... .E4n-1 and E4n, many data line D1 that in column direction, arrange, D2, ... Dm-1 and Dm, and many pixel power lead (not shown) that are used to provide pixel power. the pixel power lead receives pixel power from the external pixels power supply that pixel power is provided.
Each image element circuit 110c by sweep trace S0, S1, S2 ... Sn-1 and Sn receive the sweep signal of current scan line and the sweep signal of sweep trace (for example Sn-1 and Sn) before, and produce with from data line D1, D2 ... the electric current of the data-signal correspondence that Dm-1 and Dm transmission come. according to by the first launch-control line E11, E12 ... .E1n-1 and E1n to the four launch-control line E41, E42 ... thereby .E4n-1 and E4n transmit the first, second, third and the 4th next emissioning controling signal drive current is transferred to four OLED display images.
With data driver 200c and data line D1, D2 ... Dm-1 be connected with Dm with data signal transmission to image-display units 100c. data driver 200c sequentially with red and green, green and blue or blue and red data transmission to a data line.
Scanner driver 300c be formed on image-display units 100c a side and with a plurality of sweep trace S0, S1, S2 ... Sn-1 and Sn and many first launch-control line E11, E12 ... .E1n-1 and E1n to the four launch-control line E41, E42 ... .E4n-1 is connected with E4n, thereby sweep signal and the first, second, third and the 4th emissioning controling signal are transferred to image-display units 100c.
Figure 11 shows the circuit diagram of embodiment of pixel of the active display of Fig. 9. and with reference to Figure 11, pixel comprises four OLED and an image element circuit (for example image element circuit 110b). and with four OLED is that OLED13, OLED23, OLED33 and OLED43 are connected with an image element circuit. and image element circuit (for example image element circuit 110b) comprises driving circuit 111c, the first on-off circuit 112c and second switch circuit 113c.
Driving circuit 111c comprises that the first and second transistor M13 and M23 and the capacitor Cstc. first on-off circuit 112c comprise that the third and fourth transistor M33 and M43. second switch circuit 113c comprise the 5th and the 6th transistor M53 and M63.
First to the 6th transistor M13 comprises source electrode, drain and gate to each of M63. because first to the 6th transistor M13 does not have physics to distinguish to the drain electrode of M63 and source electrode, so, each source electrode and drain electrode can be called first electrode and second electrode. and, capacitor Cstc comprises first electrode and second electrode. four OLED are called first to the 4th OLED, and promptly OLED13 is to OLED43.
The source electrode of the first transistor M13 is connected with pixel power lead Vdd, the drain electrode of the first transistor M13 is connected with first node A3, and the grid of the first transistor M13 is connected with Section Point B3, thereby determines to flow to from the source electrode of the first transistor M13 the magnitude of current of the drain electrode of the first transistor M13 according to the voltage of the grid that is applied to the first transistor M13.
The source electrode of transistor seconds M23 is connected with data line Dm, the drain electrode of transistor seconds M23 is connected with Section Point B3, and the grid of transistor seconds M23 is connected with sweep trace Sn, thereby transistor seconds M23 carries out conducting and ends operation optionally data-signal is put on Section Point B3. according to the sweep signal sn by sweep trace Sn transmission
The source electrode of the 3rd transistor M33 is connected with first node A3, the drain electrode of the 3rd transistor M33 and an OLED, be OLED13, connect, and the grid of the 3rd transistor M33 is connected with the first launch-control line E1n, thereby the 3rd transistor M33 carries out conducting and is applied to an OLED, i.e. OLED13. by the electric current of operating with the first node A3 that optionally will flow through according to the first emissioning controling signal e1n that receives by the first launch-control line E1n
The source electrode of the 4th transistor M43 is connected with first node A3, the drain electrode of the 4th transistor M43 and the 2nd OLED, be OLED23, connect, and the grid of the 4th transistor M43 is connected with the second launch-control line E2n, thereby the 4th transistor M43 carries out conducting and is applied to the 2nd OLED, i.e. OLED23. by the electric current of operating with the first node A3 that optionally will flow through according to the second emissioning controling signal e2n that receives by the second launch-control line E2n
The source electrode of the 5th transistor M53 is connected with first node A3, the drain electrode of the 5th transistor M53 and the 3rd OLED, be that OLED33 connects, and the grid of the 5th transistor M53 is connected with the 3rd launch-control line E3n, thereby according to the 3rd emissioning controling signal e3n by the 3rd launch-control line E3n transmission, the electric current that the 5th transistor M53 optionally will flow to the drain electrode of the 5th transistor M53 from the source electrode of the 5th transistor M53 puts on the 3rd OLED, be OLED33, with from the 3rd OLED, promptly OLED33 is luminous.
The source electrode of the 6th transistor M63 is connected with first node A3, the drain electrode of the 6th transistor M63 is that OLED43 is connected with the 4th OLED, and the grid of the 6th transistor M63 is connected with the 4th launch-control line E4n, thereby the 6th transistor M63 puts on the 4th OLED according to the electric current that the 4th emissioning controling signal e4n that receives by the 4th launch-control line E4n comes optionally to flow to the drain electrode of the 6th transistor M63 from the source electrode of the 6th transistor M63, be OLED4, with from the 4th OLED, promptly OLED4 is luminous.
Figure 12 shows the waveform of the signal of the active display that is transferred to the pixel of using Figure 11. with reference to Figure 12, operate pixel to e4n by sweep signal sn, data-signal and the first, second, third and the 4th emissioning controling signal e1n. and the sweep signal sn and first to the 4th emissioning controling signal e1n are to have the cyclical signal of first to the 4th time period T1 to T4 to e4n.
In very first time section Tc1, the first emissioning controling signal e1n is a low level. in the second time period Tc2, the 3rd emissioning controling signal e3n is a low level. in the 3rd time period Tc3, the second emissioning controling signal e2n is a low level. in the 4th time period Tc4, the 4th emissioning controling signal e4n is a low level. in the moment at the starting point place of each time period, sweep signal sn is a low level.
In very first time section Tc1, thereby thereby by sweep signal sn with transistor seconds M23 conducting data-signal by by transistor seconds M23 be transferred to Section Point B3. pixel power be transferred to capacitor Cstc first electrode will and pixel power supply and data-signal between poor Vdd-Vdata corresponding voltage value be stored among the capacitor Cstc.
Capacitor Cstc will put on the grid of the first transistor M13 by Section Point B3 with poor corresponding voltage between pixel power supply and the data-signal, thereby the first transistor M13 flows to first node A3. with the electric current corresponding with data-signal
Thereby flowing to an OLED by the first emissioning controling signal e1n conducting the 3rd transistor M33 electric current is OLED13.
At the second time period Tc2, by sweep signal sn and data-signal will and pixel power supply and data-signal between poor corresponding voltage value be stored among the capacitor Cstc, thereby, the first transistor M13 flows to the 3rd OLED, i.e. OLED33. by the 3rd emissioning controling signal e3n conducting the 5th transistor M53 electric current thereby will the electric current corresponding with data-signal flowing to first node A3.
At third and fourth time period Tc3 and the Tc4, the same electric current that produces at the first and second time period Tc1 and Tc2, and electric current flows to first node A3. in the 3rd time period Tc3, by the second emissioning controling signal e2n, electric current flows to the 2nd OLED, be OLED23. at the 4th time period Tc4, flow to the 4th OLED, i.e. OLED43. by the 4th emissioning controling signal e4n electric current
Therefore, first to the 4th OLED, promptly OLED13 is to OLED43, and is luminous in order with said sequence.
Figure 13 shows the circuit diagram of first embodiment of pixel of the active display of Figure 10. with reference to Figure 13, pixel comprises four OLED and an image element circuit (for example image element circuit 110c). and four OLED, promptly OLED14, OLED24, OLED34 and OLED44 are connected with an image element circuit. and image element circuit (for example image element circuit 110c) comprises driving circuit 111d, the first on-off circuit 112d and second switch circuit 113d.
Driving circuit 111d comprises that first to the 8th transistor M14 comprises that to M84 and the capacitor Cstd. first on-off circuit 112d the 9th and the tenth transistor M94 and M104. second switch circuit 113d comprise that the 11 and the tenth two-transistor M114 and each transistor of M124. all comprise source electrode, drain and gate. capacitor Cstd comprises first electrode and second electrode.
Because first to the tenth two-transistor M14 does not have the physics difference to drain electrode and the source electrode of M124, so each source electrode and drain electrode can be called first electrode and second electrode.
The drain electrode of the first transistor M14 is connected with first node A4, the source electrode of the first transistor M14 is connected with Section Point B4, and the grid of the first transistor M14 is connected with the 3rd node C4, thereby according to the voltage of the 3rd node C4, electric current flows to first node A4. from Section Point B4
The source electrode of transistor seconds M24 is connected with data line Dm, the drain electrode of transistor seconds M24 is connected with Section Point B4, and the grid of transistor seconds M24 is connected with the first sweep trace Sn, thereby transistor seconds M24 carries out switching manipulation optionally will be transferred to Section Point B4. by data line Dm data signals transmitted according to the first sweep signal sn by first sweep trace Sn transmission
The source electrode of the 3rd transistor M34 is connected with first node A4, the drain electrode of the 3rd transistor M34 is connected with the 3rd node C4, and the grid of the 3rd transistor M34 is connected with the first sweep trace Sn, thereby make the electromotive force of first node A4 equate so that electric current is flowed through the first transistor M14. with the electromotive force of the 3rd node C4 therefore according to the first sweep signal sn by first sweep trace Sn transmission, the first transistor M14 works in the diode mode.
The source electrode of the 4th transistor M44 is connected with the second sweep trace Sn-1 with grid, and the drain electrode of the 4th transistor M44 is connected with the 3rd node C4, thereby it is the second sweep signal sn-1 that the 4th transistor M44 is applied to the 3rd node C4. initializing signal with initializing signal, it is transfused to the row that is chosen in delegation before the row that the input first sweep signal sn selects, and receive by the second sweep trace Sn-1. just, the second sweep trace Sn-1 be meant with the row that is connected at the first sweep trace Sn before the sweep trace that connects of the row of delegation.
The source electrode of the 5th transistor M54 is connected with pixel power supply Vdd, the drain electrode of the 5th transistor M54 is connected with Section Point B4, and the grid of the 5th transistor M54 is connected with the first launch-control line E1n, thereby the 5th transistor M54 basis optionally is applied to Section Point B4. with the pixel power of pixel power supply Vdd by the first emissioning controling signal e1n of first launch-control line E1n transmission
The source electrode of the 6th transistor M64 is connected with pixel power supply Vdd, the drain electrode of the 6th transistor M64 is connected with Section Point B4, and the grid of the 6th transistor M64 is connected with the second launch-control line E2n, thereby the 6th transistor M64 basis optionally is applied to Section Point B4. with the pixel power of pixel power supply Vdd by the second emissioning controling signal e2n of second launch-control line E2n transmission
The source electrode of the 7th transistor M74 is connected with pixel power supply Vdd, the drain electrode of the 7th transistor M74 is connected with Section Point B4, and the grid of the 7th transistor M74 is connected with the 3rd launch-control line E3n, thereby the 7th transistor M74 basis optionally is applied to Section Point B4. with the pixel power of pixel power supply Vdd by the 3rd emissioning controling signal e3n of the 3rd launch-control line E3n transmission
The source electrode of the 8th transistor M84 is connected with pixel power supply Vdd, the drain electrode of the 8th transistor M84 is connected with Section Point B4, and the grid of the 8th transistor M84 is connected with the 4th launch-control line E4n, thereby the 8th transistor M84 basis optionally is applied to Section Point B4. with the pixel power of pixel power supply Vdd by the 4th emissioning controling signal e4n of the 4th launch-control line E4n transmission
The source electrode of the 9th transistor M94 is connected with first node A4, the drain electrode of the 9th transistor M94 is that OLED14 is connected with an OLED, and the grid of the 9th transistor M94 is connected with the first launch-control line E1n, thereby according to the first emissioning controling signal e1n by first launch-control line E1n transmission, the electric current of first node A4 of flowing through flows to an OLED, be OLED14, with from an OLED, promptly OLED14 is luminous.
The source electrode of the tenth transistor M104 is connected with first node A4, the drain electrode of the tenth transistor M104 is that OLED24 is connected with the 2nd OLED, and the grid of the tenth transistor M104 is connected with the second launch-control line E2n, thereby according to the second emissioning controling signal e2n by second launch-control line E2n transmission, the electric current of first node A4 of flowing through flows to the 2nd OLED, be OLED24, with from the 2nd OLED, promptly OLED24 is luminous.
The source electrode of the 11 transistor M114 is connected with first node A4, the drain electrode of the 11 transistor M114 is that OLED34 is connected with the 3rd OLED, and the grid of the 11 transistor M114 is connected with the 3rd launch-control line E3n, thereby according to the 3rd emissioning controling signal e3n by the 3rd launch-control line E3n transmission, the electric current of first node A4 of flowing through flows to the 3rd OLED, be OLED34, with from the 3rd OLED, promptly OLED34 is luminous.
The source electrode of the tenth two-transistor M124 is connected with first node A4, the drain electrode of the tenth two-transistor M124 is that OLED44 is connected with the 4th OLED, and the grid of the tenth two-transistor M124 is connected with the 4th launch-control line E4n, thereby according to the 4th emissioning controling signal e4n by the 4th launch-control line E4n transmission, the electric current of first node A4 of flowing through flows to the 4th OLED, be OLED44, with from the 4th OLED, promptly OLED44 is luminous.
First electrode of capacitor Cstd is connected with pixel power supply Vdd and second electrode of capacitor Cstd is connected with the 3rd node C4, thereby by the initializing signal that is transferred to the 3rd node C4 through the 4th transistor M44 with capacitor Cstd initialization, and therefore the voltage corresponding with data-signal be transferred to the 3rd node C4. then by capacitor Cstd storage, and the grid voltage of the first transistor M14 is kept a preset time.
Figure 14 shows the circuit diagram of second embodiment of pixel of the active display of Figure 10. and with reference to Figure 14, pixel comprises four OLED and an image element circuit (for example image element circuit 110c). and four OLED are that OLED15, OLED25, OLED35 and OLED45 are connected with an image element circuit. and image element circuit (for example image element circuit 110c) comprises driving circuit 111e, the first on-off circuit 112e and second switch circuit 113e.
Driving circuit 111e comprises that first to the 8th transistor M15 comprises that to M85 and the capacitor Cste. first on-off circuit 112e the 9th and the tenth transistor M95 and M105. second switch circuit 113e comprise that the 11 and the tenth two-transistor M115 and each transistor of M125. comprise source electrode, drain and gate. capacitor Cste comprises first electrode and second electrode.
Because first to the tenth two-transistor M15 does not have the physics difference to drain electrode and the source electrode of M125, so each source electrode and drain electrode can be called first electrode and second electrode.
The drain electrode of the first transistor M15 is connected with first node A5, the source electrode of the first transistor M15 is connected with Section Point B5, and the grid of the first transistor M15 is connected with the 3rd node C5, thereby according to the voltage of the 3rd node C5, electric current flows to first node A5. from Section Point B5
The source electrode of transistor seconds M25 is connected with data line Dm, the drain electrode of transistor seconds M25 is connected with first node A5, and the grid of transistor seconds M25 is connected with the first sweep trace Sn, thereby according to the first sweep signal sn by first sweep trace Sn transmission, transistor seconds M25 carries out switching manipulation optionally will be transferred to first node A5. by data line Dm data signals transmitted
The source electrode of the 3rd transistor M35 is connected with Section Point B5, the drain electrode of the 3rd transistor M35 is connected with the 3rd node C5, and the grid of the 3rd transistor M35 is connected with the first sweep trace Sn, thereby according to the first sweep signal sn by first sweep trace Sn transmission, make the electromotive force of Section Point B5 equate with the electromotive force of the 3rd node C5, so that electric current is flowed through the first transistor M15. therefore, the first transistor M15 works in the diode mode.
The source electrode of the 4th transistor M45 is connected with the anode electrode of OLED (for example OLED35), the drain electrode of the 4th transistor M45 is connected with the 3rd node C5, and the grid of the 4th transistor M45 is connected with the second sweep trace Sn-1, thereby when there not being electric current to flow to first to the 4th OLED, be that OLED15 is during to OLED45, the 4th transistor M45 is applied to the 3rd node C5. this moment according to the second sweep signal sn-1 with voltage, will be transferred to the initializing signal of the voltage of the 3rd node C5 as initialization capacitor Cste according to the second sweep signal sn-1.
The source electrode of the 5th transistor M55 is connected with pixel power supply Vdd, the drain electrode of the 5th transistor M55 is connected with Section Point B5, and the grid of the 5th transistor M55 is connected with the first launch-control line E1n, thereby the 5th transistor M55 basis optionally is applied to Section Point B5. with the pixel power of pixel power supply Vdd by the first emissioning controling signal e1n of first launch-control line E1n transmission
The source electrode of the 6th transistor M65 is connected with pixel power supply Vdd, the drain electrode of the 6th transistor M65 is connected with Section Point B5, and the grid of the 6th transistor M65 is connected with the second launch-control line E2n, thereby the 6th transistor M65 basis optionally is applied to Section Point B5. with the pixel power of pixel power supply Vdd by the second emissioning controling signal e2n of second launch-control line E2n transmission
The source electrode of the 7th transistor M75 is connected with pixel power lead Vdd, the drain electrode of the 7th transistor M75 is connected with Section Point B5, and the grid of the 7th transistor M75 is connected with the 3rd launch-control line E3n, thereby the 7th transistor M75 basis optionally is applied to Section Point B5. with the pixel power of pixel power supply Vdd by the 3rd emissioning controling signal e3n of the 3rd launch-control line E3n transmission
The source electrode of the 8th transistor M85 is connected with pixel power supply Vdd, the drain electrode of the 8th transistor M85 is connected with Section Point B5, and the grid of the 8th transistor M85 is connected with the 4th launch-control line E4n, thereby the 8th transistor M85 is according to optionally the pixel power supply being applied to Section Point B5. by the 4th emissioning controling signal e4n of the 4th launch-control line E4n transmission
The source electrode of the 9th transistor M95 is connected with first node A5, the drain electrode of the 9th transistor M95 is that OLED15 is connected with an OLED, and the grid of the 9th transistor M95 is connected with the first launch-control line E1n, thereby according to the first emissioning controling signal e1n by first launch-control line E1n transmission, the electric current of first node A5 of flowing through flows to an OLED, be OLED15, with from an OLED, promptly OLED15 is luminous.
The source electrode of the tenth transistor M105 is connected with first node A5, the drain electrode of the tenth transistor M105 is that OLED25 is connected with the 2nd OLED, and the grid of the tenth transistor M105 is connected with the second launch-control line E2n, thereby according to the second emissioning controling signal e2n by second launch-control line E2n transmission, the electric current of first node A5 of flowing through flows to the 2nd OLED, be OLED25, with from the 2nd OLED, promptly OLED25 is luminous.
The source electrode of the 11 transistor M115 is connected with first node A5, the drain electrode of the 11 transistor M115 is that OLED35 is connected with the 3rd OLED, and the grid of the 11 transistor M115 is connected with the 3rd launch-control line E3n, thereby according to the 3rd emissioning controling signal e3n by the 3rd launch-control line E3n transmission, the electric current of first node A5 of flowing through flows to the 3rd OLED, be OLED35, with from the 3rd OLED, promptly OLED35 is luminous.
The source electrode of the tenth two-transistor M125 is connected with first node A5, the drain electrode of the tenth two-transistor M125 is that OLED45 is connected with the 4th OLED, and the grid of the tenth two-transistor M125 is connected with the 4th launch-control line E4n, thereby according to the 4th emissioning controling signal e4n by the 4th launch-control line E4n transmission, the electric current of first node A5 of flowing through flows to the 4th OLED, be OLED45, with from the 4th OLED, promptly OLED45 is luminous.
First electrode of capacitor Cste is connected with pixel power supply Vdd, and second electrode of capacitor Cste is connected with the 3rd node C5, thereby by the initializing signal that is transferred to the 3rd node C5 by the 4th transistor M45 with capacitor Cste initialization, thereby the 3rd node C5. is stored and be transferred to subsequently to the voltage corresponding with data-signal therefore by capacitor Cste, and the grid voltage of the first transistor M15 is kept a preset time.
Figure 15 shows the waveform of the signal that is transferred to the active display that uses the pixel shown in Figure 13 and 14. with reference to Figure 15, operate pixel by the first and second sweep signal sn and sn-1, data-signal and the first, second, third and the 4th emissioning controling signal e1n, e2n, e3n and e4n. and the first and second sweep signal sn and sn-1 and first to the 4th emissioning controling signal e1n are to have the cyclical signal of first to the 4th time period Td1 to Td4 to e4n.
In very first time section Td1, the first emissioning controling signal e1n is a low level. in the second time period Td2, the 3rd emissioning controling signal e3n is a low level. in the 3rd time period Td3, the second emissioning controling signal e2n is a low level. in the 4th time period Td4, the 4th emissioning controling signal e4n is a low level. and the second sweep signal sn-1 is the sweep signal that is used to be chosen in the row before the row that the input first sweep signal sn selects. and for the moment of the starting point of each time period, the first sweep signal sn and the second sweep signal sn-1 sequentially are in low level.
In very first time section Td1, by the second sweep signal sn-1 conducting the 4th transistor M4 (for example M44 and M45), and by the 4th transistor M4 with initializing signal be transferred to capacitor Cst (for example Cstd or Cste) with initialization capacitor Cst. by the first sweep signal sn conducting transistor seconds M2 (for example M24 or M25) and the 3rd transistor M3 (for example M34 and M35), thereby make the electromotive force of first node A4 or Section Point B5 equate with the electromotive force of the 3rd node C (for example C4 or C5), the first transistor M1 so that electric current is flowed through (for example M14 or M15). therefore, the first transistor M1 (for example M14 or M15) is by being connected as diode. by transistor seconds M2 (for example M24 or M25) therefore data-signal is applied to Section Point B4 or Section Point B5., by transistor seconds M2 (for example M24 or M25), the first transistor M1 (for example M14 or M15), with the 3rd transistor M3 (for example M34 or M35) data signal transmission is arrived second electrode of capacitor Cst (for example Cstd or Cste), thereby will arrive second electrode of capacitor Cst (for example Cstd or Cste) with the poor corresponding voltage transmission between data-signal and the threshold voltage.
After the first sweep signal sn is transformed to high level, when the first emissioning controling signal e1n is transformed low level and is maintained at low level during one schedule time, by the first emissioning controling signal e1n with the 5th transistor M5 (for example M54 or M55) and the 9th transistor M9 (for example M94 or M95) conducting, thereby the voltage corresponding with equation 1 is put between the grid and source electrode of the first transistor M1 (for example M14 or M15).
The 9th transistor M9 (for example M94 or M95) is switched on, thereby the electric current corresponding with equation 2 flows to an OLED, i.e. OLED1 (for example OLED14 or OLED15).
Therefore, referring now to Figure 13 and 14 and equation 2, regardless of the threshold voltage of the first transistor M14 and M15, it is OLED14 and OLED15. that electric current all flows to an OLED
In the second time period Td2, by first and second sweep signal sn and the sn-1, and the poor corresponding voltage value between pixel power supply and the data-signal is stored among the capacitor Cst (for example Cstd or Cste), and voltage and the data voltage corresponding with equation 1 is transferred to the first transistor M1 (for example M14 or M15). by the 3rd emissioning controling signal e3n, with the 7th transistor M7 (for example M74 or M75) and the 11 transistor M11 (for example M114 or M115) conducting, and the electric current corresponding with equation 2 the 3rd OLED that flows through is OLED3 (for example OLED34 and OLED35).
In the third and fourth time period Td3 and Td4, with with the first and second time period Td1 and Td2 in essentially identical mode produce electric current. just, in the 3rd time period Td3, by the second emissioning controling signal e2n conducting the 6th transistor M6 (for example M64 or M65), it is OLED2 (for example OLED24 or OLED25) that thereby electric current flows to the 2nd OLED. at the 4th time period Td4, by the 4th emissioning controling signal e4n conducting the 8th transistor M8 (for example M84 or M85) and the tenth two-transistor M12 (for example M124 or M125), be OLED4 (for example OLED44 or OLED45) thereby electric current flows to the 4th OLED.
Therefore, to be OLED1 luminous in order with above-mentioned order to OLED4 (for example OLED14 to OLED44 or OLED15 to OLED45) for first to the 4th OLED.
Figure 16 A shows the emission process of the active display of Fig. 9 to 16D. in image-display units 100b, vertically arrange three image element circuits, thereby arrange 12 OLED. with the form of 2 * 6 matrixes and can be called first image element circuit, second image element circuit and the 3rd image element circuit going up image element circuit, middle image element circuit and following image element circuit. with reference to Figure 16 A to 16D, because all four OLED are connected with an image element circuit sequentially to be that a frame is luminous, so a frame can be divided into four son fields.
The OLED that an image element circuit owing to coexist among two image element circuits adjacent with data line is connected is that OLED13 and the 3rd OLED are that OLED33 reception red data signal R is with red-emitting, and the 2nd OLED is that OLED23 and the 4th OLED are that OLED43 receives green data signal G with transmitting green light, the OLED that the one other pixel circuit among two circuit of coexisting connects is that OLED13 and the 3rd OLED are that OLED33 receives green data signal G with transmitting green light, so and the 2nd OLED be that OLED23 and the 4th OLED are that OLED43 receives red data signal R with red-emitting. alternately transmit red data and green data by a data line.
Figure 16 A shows first son field among four son fields. shown in Figure 16 A, first image element circuit and the 3rd image element circuit are that OLED13 comes red-emitting by an OLED who receives red data, and second image element circuit is the OLED13 transmitting green light by an OLED who receives green data, thereby ruddiness and green component are launched simultaneously.
In Figure 16 B that the second son field is shown, first image element circuit and the 3rd image element circuit are that OLED33 comes transmitting green light by the 3rd OLED that receives green data, and second image element circuit is the OLED33 red-emitting by the 3rd OLED that receives red data, thereby ruddiness and green component are launched simultaneously. and in of third and fourth shown in Figure 16 C and 16D field, ruddiness and green component are launched simultaneously.
When the light time of only launching a kind of color from a son field, the generation color is discontinuous. still, because from each son while red-emitting and green component, consider the entire image display unit, from each son while red-emitting, green glow and blue light components, thereby can prevent that by the present invention color is discontinuous. the active display of Figure 10 is operating with the essentially identical mode of the display of above-mentioned Fig. 9, thereby the display of Figure 10 also can prevent the discontinuous generation of color.
As mentioned above, according to active display of the present invention, thereby compensated transistorized threshold voltage regardless of the deviation in the threshold voltage, consistent electric current all flows to OLED, therefore make brightness consistent more. and, thereby a plurality of OLED can reduce the quantity of data line and the quantity of pixel power lead by image element circuit is luminous.
Particularly, because four OLED are connected with an image element circuit of an embodiment, so can reduce the quantity of the image element circuit of active display. therefore, needed image element circuit lacks with the traditional monitor that an OLED is connected than one of them pixel. owing to reduced the quantity of image element circuit, so can reduce the sweep trace of transmission signals, the quantity of data line and launch-control line. therefore, can reduce the size of scanner driver and the size of data driver, thereby can reduce unnecessary space. and, because wiring quantity reduces, so increased the aperture ratio of active display.
And, because reduced the quantity of data line, so thereby the size that can reduce data driver reduces the manufacturing cost of active display.
And, can control the shooting sequence of OLED, so prevent that the color of active display is discontinuous.
Though described the present invention in conjunction with some example embodiment, but it should be appreciated by those skilled in the art that the present invention is not limited to disclosed embodiment, but on the contrary, the present invention attempts to cover the interior various distortion of spirit and scope of claims and equivalent thereof.