CN100423265C - Three dimension complementary metal oxide semiconductor transistor structure and it spreparing method - Google Patents
Three dimension complementary metal oxide semiconductor transistor structure and it spreparing method Download PDFInfo
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Abstract
The present invention provides a high-speed three-dimensional complementary metal oxide semiconductor transistor (CMOS) structure and a preparation method thereof. The present invention is characterized in that pMOS is prepared on the surface of monocrystalline silicon (110) with large area and high quality, nMOS is prepared on the surface of the monocrystalline silicon (100) with large area and high quality, and the pMOS and the nMOS are separated on different layers. The present invention has the preparation method that the surface of a monocrystalline silicon film (110), which is the surface of the monocrystalline silicon (100), is diverted on an insulating layer after the nMOS is formed on the surface of the monocrystalline silicon (100) and the insulating layer is covered on the surface of the monocrystalline silicon (100), and the pMOS is prepared on the surface of the monocrystalline silicon (100) so as to form a high-speed CMOS structure after line connection. The surface of the monocrystalline silicon film (110), which is the surface of the monocrystalline silicon (100), can also be diverted on the insulating layer after the pMOs is formed on the surface of the monocrystalline silicon (100) and the insulating layer is covered on the surface of the monocrystalline silicon (100), and the nMOS is prepared on the surface of the monocrystalline silicon (100). The metal oxide semiconductor transistor structure and the preparation method thereof, which are provided by the present invention, can obtain high mobility, high integration level and low cost.
Description
Technical field
The present invention relates to structure of a kind of high speed three-dimensional CMOS (Complementary Metal Oxide Semiconductor) transistor (CMOS) and preparation method thereof, belong to microelectronics technology.
Background technology
Along with fast development of information technology, amount of information is increasing, and the acquisition of information, storage and conversion require more and more faster, and as the MOS transistor of integrated circuit elementary cell, speed is one of its important performance indexes.In order to improve transistorized speed, proposition uses the material of high mobilities such as germanium silicon, strained silicon as backing material, still prematurity of these technology at present.Discover: for the electronics in the silicon, the mobility maximum on (100) face, the mobility minimum of (110) face, then opposite for the hole, the mobility minimum on (100) face, the mobility maximum of (110) face (T.Sato et al., J.J.Appl.Phys., 8 (1969) 588; S.Takagi et al., IEEE TED, 1994, P2363).Therefore, if pMOS is prepared on (110) face, nMOS prepares on (100) face, then can improve the mobility of CMOS on the silicon process technology of maturation greatly, and some major companies such as IBM have been noted that this point.(M.Yang such as Yang, et al., IEDM, 2003, P453) propose to utilize special soi structure preparation CMOS at a high speed, soi structure is obtained by the method for smart peeling, top layer silicon has different crystal faces with substrate silicon, is respectively (100) and (110) face, carries out silicon epitaxy after by the method for etching substrate silicon being exposed, on substrate surface, form (100) and (110) two kinds of crystal faces like this, be used to prepare nMOS and pMOS.It is not that preparation is on the SOI substrate that but a MOS transistor is arranged among the CMOS that this method is prepared certainly.Doris (B.Doris, et al., 2004 Symposium on ULSITechnology Digest of Technical Papers, P86) new ideas of SHOT (Simplified Hybrid Orientation Technology) are adopted in proposition, FinFET (FinFETs) and ultra-thin SOI MOSFET are integrated, here the FinFET technology can prepare the transistor of (100) orientation, the transistor that also can prepare (110) orientation, but this method technology is complicated.These two kinds of methods all are to prepare the transistor of two kinds of crystal orientations at grade.
Summary of the invention
The object of the present invention is to provide a kind of three-dimensional complementary metal oxide semiconductor transistor arrangement and preparation method thereof, to obtain high mobility, high integration and low cost.
The objective of the invention is to implement by following structure: on (110) monocrystalline silicon thin film, pMOS prepares on (100) monocrystalline silicon thin film with the nMOS preparation, and (110) monocrystalline silicon thin film and (100) monocrystalline silicon thin film are on the different layers.Isolate by insulating barrier each other.This CMOS structure has kept characteristics at a high speed, and technology is simple, because the device layer multilayer is arranged, integrated level is also improved greatly, and corresponding cost also reduces.
The invention provides the structure of a kind of high speed three-dimensional CMOS (Complementary Metal Oxide Semiconductor) transistor (CMOS), the preparation of p type metal oxide semiconductor transistor is on monocrystalline silicon (110) face, the n-type metal oxide semiconductor transistor preparation is on monocrystalline silicon (100) face, and p type metal oxide semiconductor transistor and n-type metal oxide semiconductor transistor are separately on different layers.
Concrete structure has two kinds:
The preparation on (100) face n-type metal oxide semiconductor transistor in the above, the preparation on (110) face p type MOS transistor below.
The preparation on (100) face n-type metal oxide semiconductor transistor below, the preparation on (110) face p type MOS transistor in the above.
The manufacture method of above-mentioned two kinds of structures of high speed three-dimensional CMOS (Complementary Metal Oxide Semiconductor) transistor provided by the invention is respectively:
(1) after forming n-type metal oxide semiconductor transistor on (100) face and covering last insulating barrier, the surface is transferred on the insulating barrier for the monocrystalline silicon thin film of (110) face, preparation p type metal oxide semiconductor transistor on (110) face, line forms CMOS (Complementary Metal Oxide Semiconductor) transistor structure at a high speed
(2) or form p type metal oxide semiconductor transistor on (110) face and cover go up insulating barrier after, the surface is transferred on the insulating barrier for the monocrystalline silicon thin film of (100) face, on (100) face, prepare n-type metal oxide semiconductor transistor.
The concrete processing step of first kind of structure comprises:
1. adopt (100) silicon chip or surface be the silicon-on-insulator (SOI) of (100) face as substrate, metal oxide semiconductor transistor (MOS) the prepared n-type metal oxide semiconductor transistor of usefulness routine;
2. after n-type metal oxide semiconductor transistor formed, insulating barrier in the covering was thrown surface of insulating layer flat with cmp method;
3. (110) monocrystalline silicon substrate with substrate and another potting defectiveness layer at room temperature carries out the plasma bonding;
4. bonding pad is peeled off at the defect layer place under heat or mechanical force, and large tracts of land (110) monocrystalline silicon thin film is transferred on the insulating barrier that contains device;
5. on (110) monocrystalline silicon thin film, prepare p type metal oxide semiconductor transistor;
6. line.
The manufacture method of second kind of structure is:
1. adopt (110) silicon chip or surface be the silicon-on-insulator (SOI) of (110) face as substrate, metal oxide semiconductor transistor (MOS) the prepared p type metal oxide semiconductor transistor of usefulness routine;
2. after p type metal oxide semiconductor transistor formed, insulating barrier in the covering was thrown surface of insulating layer flat with cmp method;
3. (100) monocrystalline silicon substrate with substrate and another potting defectiveness layer at room temperature carries out the plasma bonding;
4. bonding pad is peeled off at the defect layer place under heat or mechanical force, and large tracts of land (100) monocrystalline silicon thin film is transferred on the insulating barrier that contains device;
5. on (100) monocrystalline silicon thin film, prepare n-type metal oxide semiconductor transistor;
6. line.
Defect layer of the present invention is annotated layer, hydrogen helium altogether and is annotated a kind of in layer or the porous silicon altogether for annotating hydrogen layer, boron hydrogen.
1. the hydrogen in the described defect layer, boron, helium plasma are introduced by ion implantor, and the position of defective buried regions and the thickness of top layer silicon are by the energy decision of ion implantor.The dosage of hydrogen ion and helium ion is (1-9) * 10
16m
-2, the dosage of boron ion is 5 * 10
14Cm
-2～5 * 10
15Cm
-2
2. imbedding of described porous layer is to adopt earlier electrochemical method to prepare porous silicon, below the epitaxy single-crystal silicon layer on the porous silicon substrate again, such monocrystalline silicon with regard to potting porous silicon.
(a) described (100) silicon chip preparation technology who contains the porous silicon defect layer: adopting P type, (100) crystal orientation, resistivity is the silicon chip of 0.01-0.02 Ω cm, then at 1: 1 HF/C
2H
5Anodic oxidation under the condition of COOH solution, unglazed photograph, anodised current density are 5mA/cm
2For stablizing the pre-oxidation 1 hour under 400 ℃ oxygen atmosphere of porous silicon structure.Remove the porous silicon surface oxide layer with the HF weak solution before the epitaxial silicon.The vacuum degree of outer time-delay ultra high vacuum plated film instrument is 10
-9Mbar, beginning 10nm silicon epitaxy speed is 0.02nm/S, is 0.04nm/S afterwards, underlayer temperature is 800 ℃.
(b) described (110) silicon chip preparation technology who contains the porous silicon defect layer is similar to 3, adopts (110) silicon chip, and what extension was come out silicon fiml also is (110).
Bonding method of the present invention is the plasma bonding.Plasma treatment is carried out on the para-linkage surface before bonding, in annealing below 400 ℃, improves bond strength behind the bonding.
Before bonding with two bonding surfaces deionized water=1: 3: 10) and RCA2 (hydrochloric acid: hydrogen peroxide: clean deionized water=1: 1: 5), then the oxygen plasma activation is carried out on two bonding pad surfaces at the RCA1 that adjusts (ammoniacal liquor: hydrogen peroxide:.The condition of oxygen plasma is: 15 millibars of air pressure, plasma power are 100W, and oxygen flow is 80sccm.After cleaning in the deionized water and drying, with the at room temperature face-to-face bonding of two substrates.
The method that defect layer of the present invention is peeled off is that heat treatment, wedge are inserted, a kind of in dashing of water under high pressure, and exfoliation temperature is less than 400 ℃.
Description of drawings
Fig. 1 is a kind of high speed three-dimensional CMOS structural representation that the embodiment of the invention 1 is provided, in this structure the preparation on (100) nMOS below, the preparation on (110) pMOS in the above.
Fig. 2 is the another kind of high speed three-dimensional CMOS structural representation that the embodiment of the invention 2 is provided, in this structure the preparation on (100) nMOS in the above, the preparation on (110) pMOS below.
Fig. 3 is a transistor preparation method's shown in Figure 1 main technique step schematic diagram.
(A) surface is the initial SOI material of (100) silicon thin film
(B) on (100) silicon thin film, prepare pMOS
(C) the CMP surface is thrown flat
(D) low temperature plasma bonding
(E) annealing
(F) on (110) silicon thin film, prepare pMOS
Fig. 4 is a transistor preparation method's shown in Figure 2 main technique step schematic diagram.
(A) initial SOI material
(B) on (110) silicon thin film, prepare pMOS
(C) the CMP surface is thrown flat
(D) low temperature plasma bonding
(E) annealing
(F) on (100) silicon thin film, prepare pMOS
Fig. 5 is (100) the silicon chip preparation technology schematic diagram that contains bubble defective buried regions.
(A) ion injects and produces bubble layer
(B) form (100) silicon thin film on the bubble layer
Fig. 6 is (110) the silicon chip preparation technology schematic diagram that contains bubble defective buried regions.
(A) ion injects and produces bubble layer
(B) form (110) silicon thin film on the bubble layer
Fig. 7 is (100) the silicon chip preparation technology schematic diagram that contains porous silicon defective buried regions.
(A) electrochemical method forms porous silicon
(B) form (100) silicon thin film on the porous silicon
Fig. 8 is (110) the silicon chip preparation technology schematic diagram that contains porous silicon defective buried regions.
(A) electrochemical method forms porous silicon
(B) form (110) silicon thin film on the porous silicon
Among the figure,
11-(100) silicon substrate
11 '-(110) silicon substrate
Insulating buried layers such as 12-silicon dioxide
13-nMOS
The layer insulation medium of 14-chemical vapour deposition technique preparation
15-pMOS
The 16-medium isolation
17-(100) silicon thin film
18-(110) silicon thin film
The 19-line
21-peels off required defective buried regions, is a kind of in 211 and 212
The 211-hydrogen ion injects the bubble layer that produces
The porous silicon that the 212-electrochemical method forms
22-contains (110) silicon support chip of defective buried regions substrate
22 '-contain (100) silicon support chip of defective buried regions substrate
Specific embodiment
Following examples will help to understand the present invention, further illustrate the invention process characteristics and obvious improvement, but the present invention only limits to embodiment by no means.
Embodiment 1: the manufacture method of high speed three-dimensional CMOS shown in Figure 1
1. original material is the SOI material, and top layer silicon is the p type, and the surface is (100) silicon thin film, shown in Fig. 3 (A).
2. adopt conventional SOI nMOS prepared nMOS, key step is: (1) long thin oxygen 60nm; (2) deposit silicon nitride 150nm on oxide layer; (3) place photoetching and place boron inject; (4) surfaces nitrided silicon and silica protective layer are removed in place oxidation; (5) form gate oxide; (6) polysilicon deposition; (7) polysilicon photoetching; (8) source, drain region are injected; (9) low-temperature oxidation; (10) lead-in wire.(shown in Fig. 3 (B))
3. the method with low-pressure chemical vapor deposition (LPCVD) covers a silicon dioxide layer on nMOS top, the surface is thrown flat with chemico-mechanical polishing (CMP).(Fig. 3 (C))
4. the substrate shown in and another contain (110) substrate of peeling off required defect layer and carry out the low temperature plasma bonding.Before bonding with two bonding surfaces deionized water=1: 3: 10) and RCA2 (hydrochloric acid: hydrogen peroxide: clean deionized water=1: 1: 5), then the oxygen plasma activation is carried out on two bonding pad surfaces at the RCA1 that adjusts (ammoniacal liquor: hydrogen peroxide:.The condition of oxygen plasma is: 15 millibars of air pressure, plasma power are 100W, and oxygen flow is 80sccm.After cleaning in the deionized water and drying, with the at room temperature face-to-face bonding of two substrates.(Fig. 3 (D))
5. bonding pad was annealed 5 minutes down at 300-400 ℃, bonding pad is peeled off at notes hydrogen layer place.In order to improve bond strength, annealed 4 hours down at 400 ℃.The surface is thrown flat with CMP.(referring to Fig. 3 (E))
6. prepare pMOS on (110) film, technology is identical with conventional SOI pMOS technology.(referring to Fig. 3 (F))
7. line obtains CMOS structure shown in Figure 1.
Embodiment 2: the manufacture method of high speed three-dimensional CMOS shown in Figure 2
1. original material is the SOI material, and top layer silicon is the n type, and the surface is (110) silicon thin film, shown in Fig. 4 (A).
2. adopt conventional SOI pMOS prepared pMOS.(Fig. 4 (B))
3. the method with low-pressure chemical vapor deposition (LPCVD) covers a silicon dioxide layer on nMOS top, the surface is thrown flat with chemico-mechanical polishing (CMP).(Fig. 4 (C))
4. the substrate shown in Fig. 4 (C) and another are contained (100) substrate of peeling off required defect layer and carry out the low temperature plasma bonding.Bonding technology is with embodiment 1.(Fig. 4 (D))
5. bonding pad was annealed 5 minutes down at 300-400 ℃, bonding pad is peeled off at notes hydrogen layer place.In order to improve bond strength, annealed 4 hours down at 400 ℃.The surface is thrown flat with CMP.(Fig. 4 (E))
6. prepare nMOS on (100) film, technology is identical with conventional SOI nMOS technology.(Fig. 4 (F))
7. line obtains CMOS structure shown in Figure 2.
Embodiment 3:
The preparation of peelable defect layer in the silicon chip:
1. (100) the silicon chip preparation technology who contains bubble defective buried regions: implantation dosage is 1 * 10 in (100) silicon chip
15m
-2The boron ion, implantation dosage is 5 * 10 then
16m
-2Hydrogen ion.(Fig. 5)
2. (110) silicon chip preparation technology who contains bubble defective buried regions: inject ion and dosage with 1, adopt (110) silicon chip to get final product.(Fig. 6)
3. (100) the silicon chip preparation technology who contains porous silicon defective buried regions: adopting P type, (100) crystal orientation, resistivity is the silicon chip of 0.01-0.02 Ω cm, then at 1: 1 HF/C
2H
5Anodic oxidation under the condition of COOH solution, unglazed photograph, anodised current density are 5mA/cm
2For stablizing the pre-oxidation 1 hour under 400 ℃ oxygen atmosphere of porous silicon structure.Remove the porous silicon surface oxide layer with the HF weak solution before the epitaxial silicon.The vacuum degree of outer time-delay ultra high vacuum plated film instrument is 10
-9Mbar, beginning 10nm silicon epitaxy speed is 0.02nm/S, is 0.04nm/S afterwards, underlayer temperature is 800 ℃.(Fig. 7)
4. (110) the silicon chip preparation technology who contains porous silicon defective buried regions is similar to 3, adopts (110) silicon chip, and what extension was come out silicon fiml also is (110).(Fig. 8)
Claims (7)
1. transistorized preparation method of three-dimensional complementary metal oxide semiconductor, after it is characterized in that forming on (100) face n-type metal oxide semiconductor transistor and covering last insulating barrier, the surface is transferred on the insulating barrier for the monocrystalline silicon thin film of (110) face, preparation p type metal oxide semiconductor transistor on (110) face, line forms CMOS (Complementary Metal Oxide Semiconductor) transistor structure at a high speed, and concrete preparation process is:
1. use (100) silicon chip or surface for the silicon-on-insulator of (100) face as substrate, with conventional metal oxide semiconductor transistor prepared n-type metal oxide semiconductor transistor;
2. after the n-type metal oxide semiconductor transistor that 1. step prepares formed, insulating barrier in the covering was thrown surface of insulating layer flat with cmp method;
3. (110) monocrystalline silicon substrate with substrate and another potting defectiveness layer at room temperature carries out the plasma bonding;
4. bonding pad is peeled off at the defect layer place under heat or mechanical force, and (110) monocrystalline silicon thin film is transferred on the insulating barrier that contains device;
5. on (110) monocrystalline silicon thin film, prepare p type metal oxide semiconductor transistor;
6. line.
2. according to the transistorized preparation method of the described three-dimensional complementary metal oxide semiconductor of claim 1, it is characterized in that defect layer is to annotate hydrogen layer, boron hydrogen to annotate layer, hydrogen helium altogether and annotate a kind of in layer or the porous silicon altogether, specifically:
1. the dosage of hydrogen ion and helium ion is 1 * 10 in the described defect layer
16～9 * 10
16Cm
-2, the dosage of boron ion is 5 * 10
14Cm
-2～5 * 10
15Cm
-2
2. imbedding of described porous layer is to adopt earlier electrochemical method to prepare porous silicon, epitaxy single-crystal silicon layer on the porous silicon substrate again, and the porous silicon that made below the monocrystalline silicon potting, specifically: adopt the silicon chip in (100) crystal orientation, then at 1: 1 HF/C
2H
5Anodic oxidation under the condition of COOH solution, unglazed photograph, anodised current density are 5mA/cm
2, the oxide layer of porous silicon surface is removed in and pre-oxidation 1 hour under 400 ℃ oxygen atmosphere with the HF weak solution before the epitaxial silicon, and the vacuum degree of the ultra high vacuum plated film instrument of delaying time outward is 10
-9Mbar, beginning 10nm silicon epitaxy speed is 0.02nm/S, is 0.04nm/S afterwards, underlayer temperature is 800 ℃.
3. prepare the transistorized method of three-dimensional complementary metal oxide semiconductor as claimed in claim 1, the method that it is characterized in that bonding is the plasma bonding, plasma treatment is carried out on the para-linkage surface before bonding, annealing below 400 ℃ behind the bonding, improve bond strength, concrete technology is: the ammoniacal liquor of before bonding two bonding surfaces being adjusted: hydrogen peroxide: deionized water=1: 3: 10 RCA1 and hydrochloric acid: hydrogen peroxide: clean among the RCA2 of deionized water=1: 1: 5, then oxygen plasma being carried out on two bonding pad surfaces activates, the condition of oxygen plasma is: 15 millibars of air pressure, plasma power is 100W, oxygen flow is 80sccm, after cleaning in the deionized water and drying, with the at room temperature face-to-face bonding of two substrates.
4. by the transistorized preparation method of the described three-dimensional complementary metal oxide semiconductor of claim 2, it is characterized in that method that defect layer is peeled off is that heat treatment, wedge insert, a kind of in dashing of water under high pressure, exfoliation temperature is less than 400 ℃.
5. transistorized preparation method of three-dimensional complementary metal oxide semiconductor, it is characterized in that preparation p type metal oxide semiconductor transistor on (110) silicon chip earlier, then (100) monocrystalline silicon thin film is transferred to the p type metal oxide semiconductor transistor top that has covered insulating barrier, prepare n-type metal oxide semiconductor transistor again on (100) face, concrete technology is:
1. use (110) silicon chip or surface for the silicon-on-insulator of (110) face as substrate, with conventional metal oxide semiconductor transistor prepared p type metal oxide semiconductor transistor;
2. 1. prepare p type metal oxide semiconductor transistor in step and form insulating barrier in the covering of back, surface of insulating layer is thrown flat with cmp method;
3. (100) monocrystalline silicon substrate with substrate and another potting defectiveness layer at room temperature carries out the plasma bonding;
4. bonding pad is peeled off at the defect layer place under heat or mechanical force, and (100) monocrystalline silicon thin film is transferred on the insulating barrier that contains device;
5. prepare n-type metal oxide semiconductor transistor on (100) monocrystalline silicon thin film;
6. line.
6. by the transistorized preparation method of the described three-dimensional complementary metal oxide semiconductor of claim 5, the method that it is characterized in that bonding is the plasma bonding, plasma treatment is carried out on the para-linkage surface before bonding, annealing below 400 ℃ behind the bonding, improve bond strength, concrete technology is: the ammoniacal liquor of before bonding two bonding surfaces being adjusted: hydrogen peroxide: deionized water=1: 3: 10 RCA1 and hydrochloric acid: hydrogen peroxide: clean among the RCA2 of deionized water=1: 1: 5, then oxygen plasma being carried out on two bonding pad surfaces activates, the condition of oxygen plasma is: 15 millibars of air pressure, plasma power is 100W, oxygen flow is 80sccm, after cleaning in the deionized water and drying, with the at room temperature face-to-face bonding of two substrates.
7. by the transistorized preparation method of the described three-dimensional complementary metal oxide semiconductor of claim 5, it is characterized in that defect layer is to annotate hydrogen layer, boron hydrogen to annotate layer, hydrogen helium altogether and annotate a kind of in layer or the porous silicon altogether, specifically:
1. the dosage of hydrogen ion and helium ion is 1～9 * 10 in the described defect layer
16Cm
-2, the dosage of boron ion is 5 * 10
14Cm
-2～5 * 10
15Cm
-2
2. imbedding of described porous layer is to adopt earlier electrochemical method to prepare porous silicon, epitaxy single-crystal silicon layer on the porous silicon substrate again, and the porous silicon that made below the monocrystalline silicon potting, specifically: adopt the silicon chip in (100) crystal orientation, then at 1: 1 HF/C
2H
5Anodic oxidation under the condition of COOH solution, unglazed photograph, anodised current density are 5mA/cm
2, the oxide layer of porous silicon surface is removed in and pre-oxidation 1 hour under 400 ℃ oxygen atmosphere with the HF weak solution before the epitaxial silicon, and the vacuum degree of the ultra high vacuum plated film instrument of delaying time outward is 10
-9Mbar, beginning 10nm silicon epitaxy speed is 0.02nm/S, be 0.04nm/S afterwards, and underlayer temperature is 800 ℃, and the method that defect layer is peeled off is a kind of during heat treatment, wedge insertion, water under high pressure are dashed, and exfoliation temperature is less than 400 ℃.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4768076A (en) * | 1984-09-14 | 1988-08-30 | Hitachi, Ltd. | Recrystallized CMOS with different crystal planes |
| US5384473A (en) * | 1991-10-01 | 1995-01-24 | Kabushiki Kaisha Toshiba | Semiconductor body having element formation surfaces with different orientations |
| CN1536676A (en) * | 2003-04-04 | 2004-10-13 | ̨������·����ɷ�����˾ | Chip with covered silicon on multiaspect insulating layer and its making method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4768076A (en) * | 1984-09-14 | 1988-08-30 | Hitachi, Ltd. | Recrystallized CMOS with different crystal planes |
| US5384473A (en) * | 1991-10-01 | 1995-01-24 | Kabushiki Kaisha Toshiba | Semiconductor body having element formation surfaces with different orientations |
| CN1536676A (en) * | 2003-04-04 | 2004-10-13 | ̨������·����ɷ�����˾ | Chip with covered silicon on multiaspect insulating layer and its making method |
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