CN100423246C - 包含金属层顶部钨或钨化合物之连结垫 - Google Patents

包含金属层顶部钨或钨化合物之连结垫 Download PDF

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CN100423246C
CN100423246C CNB038097001A CN03809700A CN100423246C CN 100423246 C CN100423246 C CN 100423246C CN B038097001 A CNB038097001 A CN B038097001A CN 03809700 A CN03809700 A CN 03809700A CN 100423246 C CN100423246 C CN 100423246C
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bond pad
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tungsten
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H·-J·巴思
A·布林辛格
G·弗里塞
W·罗布尔
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Abstract

一种形成于IC衬底的预先决定区域的连结垫结构包括在光刻及通过氟化学的等离子体蚀刻时可快速地及容易地移除的冗余及保护层，该连结垫结构包括：形成于该IC衬底的预先决定区域的内衬层或下方金属层；形成于该内衬层上的铝基底金属层作为连结目的的最后金属层；形成于该铝基底最后金属层的顶部的钨基底冗余与抗反射层；及形成于该IC衬底及该钨基底冗余与抗反射层的保护层。

Description

包含金属层顶部钨或钨化合物之连结垫
技术领域
本发明是关于使用Al做为连结目的的最后金属的集成电路(IC)或半导体装置的连结垫结构，及利用钨或钨化合物层做为最后金属堆叠的顶部层，及其中该钨或钨化合物层可做为在该连结垫结构的顶部金属层的顶部的冗余或抗反射涂布。
背景技术
一种用于具可熔连结的存储器阵列的保护层蚀刻方法被揭示于美国专利第6,180,503B1号。具可熔连结的存储器阵列乃由使用暂时蚀刻中止层于第一及第二步骤间以两步骤蚀刻该激光通道开孔而得到。在熔丝形成于多晶硅层后，蚀刻中止垫在熔丝的破裂带上方的较高层金属或多晶硅层图案化。该熔丝通道开孔接著与穿透厚IMD层的通孔蚀刻部分同时形成。该蚀刻中止垫限制在破裂带上方的穿透仅至该IMD层。在金属图案化蚀刻期间，该蚀刻中止垫被移除。该通道开孔的第二及最后部份接著在保护层的图案化期间形成。因为该蚀刻中止垫已在保护蚀刻时被移除，该连结垫开口及该最后熔丝通道开孔可由单一掩模达到。
美国专利第6,319,758号揭示在自动对准接触方法的冗余结构，进行位于半导体衬底的IC内的冗余电路的冗余结构包括可熔连结。
该可熔连结由沉积于在冗余电路及存在于该集成电路的其他电路间连接的半导体衬底的绝缘层的传导材料层形成。该绝缘层一般为位于半导体衬底表面的场氧化层。该传导材料层由金属如铝(Al)或钨(W)、高度掺杂多晶硅、或金属如钨(W)及高度掺杂多晶硅的合金所组成。
连结垫结构及其制造方法被揭示于美国专利第6,365,970B1号。该连结垫结构包括：
形成于预先决定区域上的下方金属层；
形成于该下方金属层上的介电体层，该介电体层具分别仅在该第一、第二及第三区域的介电体层穿过形成的通孔开孔；
形成于该介电体层及该通孔开孔的侧面或底部的第一扩散阻挡层；
由填充金属材料进入该通孔开孔所形成的通孔塞；
形成于该第一扩散阻挡层及通孔塞的第二扩散阻挡层；及
形成于该第二扩散阻挡层的上方金属层。
美国专利第5,882,999号揭示在集成电路的绝缘层的金属化方法，该方法包括沉积如TiN材料的抗反射涂布层于绝缘层上，以一系列通道或孔洞通孔图案化ARC与绝缘体及沉积如钨的金属于ARC及在通道及孔洞。
非反应抗反射涂布揭示于美国专利第5,834,125号，该抗反射涂布由阻挡层及抗反射层组成。阻挡层由防止在抗反射层及下方层或衬底间的反应，不会使得抗反射层为反射的，及较佳为不与反射层或抗反射层反应的材料组成。在本发明的特别具体实施例中，该阻挡层为二氧化硅SiO2或氮化硅Si3N4的薄层，及该抗反射层为钛-钨TiW、氮化钛TiN、或无定形硅。
Tao等，在多层中间连接及阻挡层材料的电子迁移失效的特徵及模型，电子装置I EEE汇刊43卷，11期，十一月1996，1819-1824页，揭示TiN/Al-合金/TiN多层中间连接及TiN与TiW阻挡层材料的电子迁移性能，其中在多层中间连接观察的损伤回复被证实为原因为在Al电子迁移所诱发的应力而非焦耳加热。
存在一种发现及布置Ti及Ti化合物的代替品的需求因为Ti及其化合物不易及缓慢以氟化学移除，当该Ti材料被用做IC或半导体装置的最后金属堆叠的顶部层，如连结垫结构，此处连结垫结构提供具连结线或其他连接器位置的IC晶片。当考虑IC晶片被制造时，晶片的良率直接相关于连结垫本身的可靠度时，此需求为明显的，此是因为当该连结垫被制造时，IC晶片的连结垫倾向于因在稍后的探针测试步骤及连结线加工期间损伤而衰坏。
发明内容
在IC或DRAM胞元装置或晶片中，其中熔丝形成于多晶硅层，及其中Al或其合金沉积于内衬层做为金属层传导材料，接著为冗余层及保护层的沉积，本发明目的为发现及布置冗余层及抗反射涂布做为在Al或其合金的顶部金属，使得在光刻及通过氟化学的等离子体蚀刻时，在该连结区域的最后保护被快速地及完全地移除，不像当使用Ti及其化合物做为冗余层的情况。
本发明另一目的为在IC或DRAM胞元装置或晶片的情况下，其中熔丝形成于多晶硅层，利用W及其化合物做为在Al或其合金上的顶部金属，使得在光刻及通过氟化学的等离子体蚀刻时，在该连结区域的最后保护被快速地及完全地移除。
一般，本发明IC或DRAM胞元装置或晶片的连结垫结构(其中熔丝形成于多晶硅层)是使用已知DRAM制造步骤得到，除此之外，W或其化合物取代Ti或其化合物被用做在用做连结垫材料的最后金属或Al的顶部上的顶部或冗余层。而且，W或其化合物(非钛)亦用做在光刻的冗余层及抗反射涂布。
附图说明
第1图为本发明IC的简化截面区段视图，其说明已知Ti基底内衬层，Al或其化合物的金属层、在中间连接线路的顶部的W基底冗余层、及保护层被沉积于此。
第2图为本发明IC的简化截面区段视图，其说明Ti基底内衬层，Al或其化合物的金属层沉积于其上，如第1图所示，接著为连结垫要被形成的熔丝区域及/或其他区域或面积的通过氟化学的等离子体蚀刻。
具体实施方式
现在参考第1图，其为集成电路(IC)、DRAM胞元装置或晶片10的简化截面区段视图，其形成于多晶硅层，在制造此记忆晶片时某些步骤被进行以阻遏缺陷元件且这些步骤可包括额外部分的记忆电路提供于该IC晶片做为缺陷部分的取代，及冗余部分被使用及缺陷部分删除的方式是通过使用激光对齐的方式。
第1图IC晶片结构包括已知Ti基底内衬层11及Al或Al化合物的金属层12如AlCu沉积于其上，以达到形成连结的目的。由溅镀沉积的冗余层13(其存在于中间连接线路的顶部)被沉积于层12；然而，在本发明内文中该冗余层为W或其化合物(非钛)而非已知的Ti或其化合物，以能够快速及完全的移除在熔丝上的W及保护层14及/或所形成的连结垫区域。
保护层14可由光光刻图案化技术及通过氟化学的等离子体蚀刻的已知已知方法图案化以产生至该连结垫的开口。
部分该W基底冗余层13及保护层14，如在第2图的IC晶片结构所示，如上文所叙述，通过已知光光刻图案化方法及通过氟化学的等离子体蚀刻被图案化以产生开口0，于此该W基底冗余层已在连结垫区域15移除，以提供该IC晶片的优秀封装。
而且，当在该连结垫上的最后保护被移除时，以该W的氟基底化学进行的等离子体蚀刻产生大的优点在于W被快速地及完全地移除，不像Ti及其化合物。
总之，本发明连结垫结构形成于IC衬底的预先决定区域，其包括在光刻及通过氟化学的等离子体蚀刻时可快速地及完全地移除的冗余层及保护层，该连结垫结构包括：
形成于该IC衬底的预先决定区域的内衬层或下方金属层；
形成于该内衬层上的铝基底金属层作为连结目的的最后金属层；
形成于该铝基底最后金属层的顶部的钨基底冗余与抗反射层；及
形成于该IC衬底及该钨基底冗余与抗反射层的保护层。
虽然本发明是参考其较佳具体实施例叙述，本领域技术人员要了解一些在形式上及细节上的变化可被进行且不偏离由所附权利要求所限定的本发明构思及范围。

Claims (10)

1. 一种形成于IC衬底的预先决定区域的连结垫结构，包括：
形成于该IC衬底的预先决定区域的内衬层(11)；
形成于该内衬层上的铝基底金属层(12)作为连结目的的最后金属层；
形成于该铝基底最后金属层的顶部的一钨基底冗余与抗反射层(13)，该钨基底冗余与抗反射层在光刻及通过氟化学的等离子体蚀刻时可快速地及容易地被移除；及
形成于该IC衬底及该钨基底冗余与抗反射层的保护层(14)，该保护层在光刻及通过氟化学的等离子体蚀刻时可快速地及容易地被移除；
其特征在于，
该钨基底冗余与抗反射层(13)为W或WSi2。
2. 权利要求1的连结垫结构，其中该内衬层(11)为Ti基底内衬层。
3. 权利要求2的连结垫结构，其中该Ti基底内衬层(11)由Ti、TiN及TiW所组成族群选出。
4. 权利要求3的连结垫结构，其中该Ti基底内衬层(11)为Ti。
5. 权利要求3的连结垫结构，其中该Ti基底内衬层(11)为TiN。
6. 权利要求3的连结垫结构，其中该Ti基底内衬层(11)为TiW。
7. 权利要求2的连结垫结构，其中该铝基底金属层(12)由Al、AlCu及AlCuSi所组成族群选出。
8. 权利要求7的连结垫结构，其中该铝基底金属层(12)为Al。
9. 权利要求7的连结垫结构，其中该铝基底金属层(12)为AlCu。
10. 权利要求7的连结垫结构，其中该铝基底金属层(12)为AlCuSi。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7215000B2 (en) * 2004-08-23 2007-05-08 Texas Instruments Incorporated Selectively encased surface metal structures in a semiconductor device
US7361581B2 (en) * 2004-11-23 2008-04-22 International Business Machines Corporation High surface area aluminum bond pad for through-wafer connections to an electronic package
US7875546B1 (en) 2006-09-01 2011-01-25 National Semiconductor Corporation System and method for preventing metal corrosion on bond pads
US7557455B1 (en) 2007-02-27 2009-07-07 National Semiconductor Corporation System and apparatus that reduce corrosion of an integrated circuit through its bond pads
US8282846B2 (en) * 2010-02-27 2012-10-09 National Semiconductor Corporation Metal interconnect structure with a side wall spacer that protects an ARC layer and a bond pad from corrosion and method of forming the metal interconnect structure
US9259932B2 (en) * 2011-05-27 2016-02-16 Hewlett-Packard Development Company, L.P. Assembly to selectively etch at inkjet printhead
JP6002437B2 (ja) * 2012-05-17 2016-10-05 新日本無線株式会社 半導体装置及びその製造方法
US9590157B2 (en) 2015-06-04 2017-03-07 The Silanna Group Pty Ltd Efficient dual metal contact formation for a semiconductor device
CN109725107A (zh) * 2017-10-29 2019-05-07 天津市业洪检测技术发展有限公司 水泥中氧化镁的精准检测方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4824803A (en) * 1987-06-22 1989-04-25 Standard Microsystems Corporation Multilayer metallization method for integrated circuits
JPH04731A (ja) * 1989-01-27 1992-01-06 Nec Corp 半導体装置及びその製造方法
JPH06177200A (ja) * 1992-12-09 1994-06-24 Hitachi Ltd 半導体集積回路装置の形成方法
US5985765A (en) * 1998-05-11 1999-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings
US6258706B1 (en) * 1998-06-22 2001-07-10 Taiwan Semiconductor Manufacturing Company, Ltd Method for fabricating a stress buffered bond pad

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862232A (en) 1986-09-22 1989-08-29 General Motors Corporation Transistor structure for high temperature logic circuits with insulation around source and drain regions
US5404047A (en) * 1992-07-17 1995-04-04 Lsi Logic Corporation Semiconductor die having a high density array of composite bond pads
US5834125A (en) 1993-06-16 1998-11-10 Integrated Device Technology, Inc. Non-reactive anti-reflection coating
US5384284A (en) * 1993-10-01 1995-01-24 Micron Semiconductor, Inc. Method to form a low resistant bond pad interconnect
EP0697723A3 (en) 1994-08-15 1997-04-16 Ibm Method of metallizing an insulating layer
US5703408A (en) * 1995-04-10 1997-12-30 United Microelectronics Corporation Bonding pad structure and method thereof
US5960306A (en) * 1995-12-15 1999-09-28 Motorola, Inc. Process for forming a semiconductor device
US6051369A (en) 1998-01-08 2000-04-18 Kabushiki Kaisha Toshiba Lithography process using one or more anti-reflective coating films and fabrication process using the lithography process
US6147409A (en) 1998-06-15 2000-11-14 Lsi Logic Corporation Modified multilayered metal line structure for use with tungsten-filled vias in integrated circuit structures
US6365967B1 (en) 1999-05-25 2002-04-02 Micron Technology, Inc. Interconnect structure
US6365511B1 (en) 1999-06-03 2002-04-02 Agere Systems Guardian Corp. Tungsten silicide nitride as a barrier for high temperature anneals to improve hot carrier reliability
US6306749B1 (en) 1999-06-08 2001-10-23 Winbond Electronics Corp Bond pad with pad edge strengthening structure
US6319758B1 (en) 1999-06-10 2001-11-20 Taiwan Semiconductor Manufacturing Company Redundancy structure in self-aligned contact process
US6180503B1 (en) * 1999-07-29 2001-01-30 Vanguard International Semiconductor Corporation Passivation layer etching process for memory arrays with fusible links
US6365970B1 (en) 1999-12-10 2002-04-02 Silicon Integrated Systems Corporation Bond pad structure and its method of fabricating
US6373137B1 (en) * 2000-03-21 2002-04-16 Micron Technology, Inc. Copper interconnect for an integrated circuit and methods for its fabrication

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4824803A (en) * 1987-06-22 1989-04-25 Standard Microsystems Corporation Multilayer metallization method for integrated circuits
JPH04731A (ja) * 1989-01-27 1992-01-06 Nec Corp 半導体装置及びその製造方法
JPH06177200A (ja) * 1992-12-09 1994-06-24 Hitachi Ltd 半導体集積回路装置の形成方法
US5985765A (en) * 1998-05-11 1999-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings
US6258706B1 (en) * 1998-06-22 2001-07-10 Taiwan Semiconductor Manufacturing Company, Ltd Method for fabricating a stress buffered bond pad

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