CN100423228C - Dual-metal inserting structure and producing method thereof - Google Patents
Dual-metal inserting structure and producing method thereof Download PDFInfo
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- CN100423228C CN100423228C CNB2005101038651A CN200510103865A CN100423228C CN 100423228 C CN100423228 C CN 100423228C CN B2005101038651 A CNB2005101038651 A CN B2005101038651A CN 200510103865 A CN200510103865 A CN 200510103865A CN 100423228 C CN100423228 C CN 100423228C
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Abstract
The invention is concerned with the dual metal mosaic structure, including: the base, the dielectric layer, the hard mask layer, the touching window, and the lead; the dielectric layer is located on the base; the hard mask layer is located on the dielectric layer; the touching window is located in the dielectric layer, the horizontal section of the touching is the dissymmetry circled outline; the lead is located in the hard mask layer and the dielectric layer, it is also on the touching window and electronic connection with it, the lead is with a side protuberance and located on the edge of the touching window.
Description
Technical field
The present invention relates to a kind of structure and manufacture method of semiconductor element, particularly relate to a kind of double-metal inlaid structure and manufacture method thereof.
Background technology
Dual-metal inserting technology is the technology that a kind of design with metal interconnecting is embedded in insulating barrier.Owing to adopt the mode of dual-metal inserting technology, the method that can avoid typical case's elder generation's formation contact structures (contact) to form plain conductor again faces the problem of overlay error (overlay error) and process deviation (process bias) in photoetching process, and the reliability of element is increased, and technological ability is promoted.Therefore, after element heights is integrated, a kind of technology that dual-metal inserting technology becomes semi-conductor industry gradually and adopted.
Yet dual-metal inserting technology still has some problems and exists.For instance, groove defines with the hard mask layer with channel patterns in some dual-metal inserting technology, and contact window defines with the photoresist layer with contact window pattern that forms after a while.Therefore, in case photomask is to punctual generation aligning mistake (misalignment), then hard mask layer can stop the etching of contact window, make the opening size of contact window reduce, the contact area of its formed contact structures and suprabasil element after inserting metal level also will thereby be dwindled, and cause contact resistance value to increase, can reduce the service speed of element thus.In addition, can cause contact structures fully to produce even and contact, and cause short circuit between the two adjacent elements with contiguous element.
Summary of the invention
Purpose of the present invention is exactly that a kind of manufacture method of double-metal inlaid structure is being provided, and can improve to have now because of aligning mistake causes contact resistance value increases, and then reduces the problem of element operation speed.
Another object of the present invention provides a kind of double-metal inlaid structure, can increase the contact area of contact structures and element, improves the reliability and the rate of finished products of element.
The present invention proposes a kind of manufacture method of double-metal inlaid structure, and the method is prior to forming dielectric layer and hard mask layer in regular turn in the substrate.Then, in hard mask layer, form channel patterns.Afterwards, form the photoresist layer of a patterning in substrate top, and the photoresist layer of patterning has the predetermined patterns of openings that forms contact hole, wherein patterns of openings is formed on the channel patterns.Then, carry out a top rake step, the part hard mask layer that removes in the patterns of openings to be exposed.Continuing it, is mask with the photoresist layer of patterning, removes the part dielectric layer, to form opening in dielectric layer.Then, removing the photoresist layer of patterning, is mask with the hard mask layer subsequently, removes the part dielectric layer to exposing substrate surface, with the formation contact window, and forms groove simultaneously on contact window.Then, in groove and contact window, form a conductor layer.
Described according to embodiments of the invention, above-mentioned hard mask layer for example is a metal hard mask layer, the material of metal hard mask layer for example is titanium, titanium nitride, tantalum, tantalum nitride and tungsten nitride, and the formation method of hard mask layer for example is chemical vapour deposition technique (CVD) or physical vaporous deposition (PVD).
Described according to embodiments of the invention, above-mentioned top rake step comprises carries out a bombardment technology.
Described according to embodiments of the invention, the material of above-mentioned conductor layer for example is a metallic copper.
Described according to embodiments of the invention, the formation method of above-mentioned channel patterns is the photo anti-corrosion agent material layer that forms a patterning on hard mask layer, and wherein the pattern of the photo anti-corrosion agent material layer of patterning is positioned on the element region.Then, be mask with the photo anti-corrosion agent material layer of patterning, remove the part hard mask layer to exposing part dielectric layer surface.
Described according to embodiments of the invention, the material of above-mentioned dielectric layer for example is an advanced low-k materials.
A kind of double-metal inlaid structure, this structure comprise substrate, dielectric layer, hard mask layer, first contact structures and lead.Wherein, dielectric layer is positioned in the substrate, and hard mask layer is positioned on the dielectric layer.First contact structures are arranged in dielectric layer, and the horizontal cross-section of first contact structures has asymmetric sphering profile.Lead is arranged in hard mask layer and dielectric layer, and is positioned on first contact structures and with it and is electrically connected, and lead has side direction protuberance, and it is positioned on the contact structures edge.
Described according to embodiments of the invention, above-mentioned hard mask layer for example is a metal hard mask layer, and the material of metal hard mask layer for example is titanium, titanium nitride, tantalum, tantalum nitride and tungsten nitride.
Described according to embodiments of the invention, double-metal inlaid structure also comprises second contact structures, be disposed between substrate and the lead, and adjacent with first contact structures, and the horizontal cross-section of second contact structures has the sphering profile of symmetry.
Described according to embodiments of the invention, above-mentioned first contact structures, second contact structures are identical with conductor material, and its material for example is a conductor material, and conductor material for example is a metallic copper.
Described according to embodiments of the invention, the material of above-mentioned dielectric layer for example is an advanced low-k materials.
The present invention carried out a top rake step before contact window forms, to remove the corner, top of the hard mask layer that exposes because of aligning mistake, so that the patterns of openings of hard mask layer becomes big.Thus, the contact area of formed contact structures of subsequent technique and element is increased.Therefore, can avoid dwindling and cause contact resistance value to increase, reduce the problems such as service speed of element because of contact area.And, can improve the reliability and the rate of finished products of element widely.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Figure 1A to Fig. 1 F is the manufacturing process profile according to the double-metal inlaid structure that the embodiment of the invention illustrated.
Fig. 2 is the top view according to the contact structures in the double-metal inlaid structure that the embodiment of the invention illustrated.
Fig. 3 is the top view according to the contact structures in the double-metal inlaid structure that another embodiment of the present invention illustrated.
The simple symbol explanation
100: substrate
102: element region
104: dielectric layer
106: insulating barrier
108: hard mask layer
109: the corner, top
110,110a: channel patterns
111: the contact window pattern
114: the photoresist layer of patterning
116,118: opening
116a, 118a: contact window
116b, 118b: contact structures
120: conductor layer
122: lead
Embodiment
Figure 1A to Fig. 1 F is the manufacturing process profile according to the double-metal inlaid structure that the embodiment of the invention illustrated.
Please refer to Figure 1A, in the present invention, at first provide a substrate 100, this substrate 100 can be the substrate that any technology is suitable for, and has been formed with an element region 102 in the substrate 100.Then, in substrate 100, form one dielectric layer 104, the material of dielectric layer 104 for example is that dielectric constant is lower than 4 advanced low-k materials, advanced low-k materials comprises the material of mineral-type, silane sesquichloride (Hydrogen Silsesquioxane for example, HSQ), mix silica (the Fluorinated Silicate Glass of fluorine, FSG) etc., and the material of organic class, poly aromatic alkene ether (Fluorinated Poly-(AryleneEther) for example, Flare), aromatic hydrocarbons (Poly-(Arylene Ether), SILK), poly-arylene ether (Parylene) etc., and the formation method of dielectric layer 104 for example is chemical vapour deposition technique (CVD).
Afterwards, on dielectric layer 104, form one deck hard mask layer 108, hard mask layer 108 can for example be a metal hard mask layer, and the material of metal hard mask layer can for example be titanium, titanium nitride, tantalum, tantalum nitride and tungsten nitride, and the formation method of hard mask layer 108 for example is chemical vapour deposition technique or physical vaporous deposition (PVD).
In addition, in one embodiment, can before forming hard mask layer 108, on the surface of dielectric layer 104, form a layer insulating 106.Wherein, the material of insulating barrier 106 for example is to be the silica that reacting gas source forms with tetraethoxysilane (TEOS), and its formation method for example is a chemical vapour deposition technique.Insulating barrier 106 in the time of can avoiding again carrying out chemical mechanical milling method (CMP), may have the anxiety that is ground to dielectric layer 104 except grinding easily than dielectric layer 104.
Then, please refer to Figure 1B, form a channel patterns 110 in hard mask layer 108, wherein channel patterns 110 is formed at element region 102 tops, and channel patterns 110 bottom-exposed go out partial insulative layer 106 surfaces.The formation method of above-mentioned channel patterns 110 for example is the photo anti-corrosion agent material layer (not illustrating) that forms one deck patterning on hard mask layer 108, and the pattern of the photo anti-corrosion agent material layer of patterning is positioned on the element region 102.Then, photo anti-corrosion agent material layer with patterning is a mask, remove part hard mask layer 108 to exposing insulating barrier 106 surfaces, can form channel patterns 110 in hard mask layer 108, the method that wherein removes part hard mask layer 108 for example is reactive ion-etching (RIE).
Then, please refer to Fig. 1 C, form the photoresist layer 114 of a patterning in substrate 100 tops, and the photoresist layer 114 of patterning has contact window pattern 111.In another embodiment, can before the photoresist layer 114 that forms patterning, form an anti-reflecting layer (not illustrating), cover insulating barrier 106 and hard mask layer 108 in substrate 100 tops.Wherein, the material of anti-reflecting layer for example is silicon oxynitride or other antireflecting material, and its formation method for example is a chemical vapour deposition technique.
The contact window pattern 111 of photoresist layer 114 should be aimed at channel patterns 110, person shown in dotted line.Yet, when the patterns of openings of the photoresist layer 114 of define patternization, if technology has deviation or control that aligning mistake (misalignment) takes place accidentally slightly, then the patterns of openings of the photoresist layer 114 of patterning can produce displacement, and the contact window pattern 111 of the photoresist layer 114 of patterning can expose hard mask layer 108.If will not influence the contact structures of the follow-up double-metal inlaid structure of producing with the contact area of element is dwindled, and to cause contact resistance value to increase, the service speed of reduction element through suitably handling.Therefore, the present invention proposes a kind of double-metal inlaid structure and manufacture method thereof, to solve the above problems.
Continue it, please refer to Fig. 1 D, carry out a top rake step, remove the part hard mask layer 108 that is exposed in the contact window pattern 111 of photoresist layer 114 of patterning.Above-mentioned top rake step for example is to carry out bombardment (bombard) technology, and it for example is to utilize radio frequency (RF) that the hard mask layer 108 that is exposed is carried out a bombardment technology, the corner, top 109 of the hard mask layer 108 that is exposed to remove.
Then, please refer to Fig. 1 E, is mask with the photoresist layer 114 of patterning, removes partial insulative layer 106 and part dielectric layer 104, to form opening 116,118 in insulating barrier 106 and dielectric layer 104.Because the top rake step has been removed the corner, top 109 of the hard mask layer 108 that exposes before, also can be removed with part dielectric layer 104 so before be positioned at the insulating barrier 106 of these 109 belows, corner, top.
Then, please refer to Fig. 1 F, remove the photoresist layer 114 of patterning, is mask with hard mask layer 108 then, and the part dielectric layer 104 that removes opening 116,118 bottoms is to exposing substrate 100 surfaces, to form contact window 116a, 118a.Because the corner, top 109 of the hard mask layer 108 that exposes in removing before, can be removed by above-mentioned two etching steps so before be positioned at the dielectric layer 104 of these 109 belows, corner, top fully.
Subsequently, in channel patterns 110a and contact window 116a, 118a, form a conductor layer 120, to form lead 122 and contact structures 116b, 118b.Because before being positioned at the insulating barrier 106 of these 109 belows, corner, top has been removed with dielectric layer 104, so having side direction protuberance, lead 122 is positioned on the edge part of contact structures 116b, the area coincidence of the corner, top 109 before the horizontal profile of this side direction protuberance and marginal portion and the removal is shown in Fig. 2 bend district.The material of conductor layer 120 for example is metallic copper or other metal, and its formation method can for example be to utilize chemical vapour deposition technique to form one deck conductor material layer in substrate 100 tops, removes the segment conductor material layer then to exposing hard mask layer 108 surfaces.The above-mentioned method that removes the segment conductor material layer for example is a chemical mechanical milling method.
What be worth paying special attention to is, the corner, top 109 of the hard mask layer 108 that is exposed in the photoresist layer 114 of the above-mentioned removable patterning of top rake step, and it can make hard mask layer 108 have bigger patterns of openings (shown in Fig. 1 E).Therefore, can increase, cause contact resistance value to increase, reduce the problems such as service speed of element and can avoid dwindling because of contact area in the contact structures of the follow-up double-metal inlaid structure that produces and the contact area of element.
Next, the formed double-metal inlaid structure of the manufacture method of utilizing double-metal inlaid structure of the present invention is described.
Please referring again to Fig. 1 F, double-metal inlaid structure of the present invention comprises substrate 100, dielectric layer 104, hard mask layer 108, contact structures 116b and lead 122.Dielectric layer 104 is positioned in the substrate 100, and the material of dielectric layer 104 for example is that dielectric constant is lower than 4 advanced low-k materials.Hard mask layer 108 is positioned on the dielectric layer 104, and hard mask layer 108 can for example be a metal hard mask layer, and the material of metal hard mask layer for example is titanium, titanium nitride, tantalum, tantalum nitride and tungsten nitride.Lead 122 is arranged in hard mask layer 108 and dielectric layer 104, and is positioned at contact structures 116b and goes up and be electrically connected with it, and lead 122 has side direction protuberance, and it is positioned on the contact structures 116b edge, shown in Fig. 2 bend district; And contact structures 116b is identical with lead 122 materials, and its material for example is a conductor material, and conductor material for example is a metallic copper.
Be described in more detail, in the manufacture method of double-metal inlaid structure of the present invention, the top rake step of being carried out can increase the horizontal cross-section of contact structures 116b, and wherein the oblique line among Fig. 2 partly is the part of increase.Therefore, can increase the contact area of contact structures and element, cause contact resistance value to increase, reduce the problems such as service speed of element to improve to dwindle because of contact area.
The foregoing description is to do explanation with the aligning mistake of photomask generation X-direction, and the present invention is not limited to this.If photomask produces the aligning mistake of Y direction, the top view of then formed contact structures 116b, 118b can be as shown in Figure 3, and contact structures 116b, 118b all can make the contact area of itself and element increase because of the top rake step, and wherein the oblique line among Fig. 3 is partly for utilizing the horizontal cross-section of the contact structures that the present invention increases.Certainly, the present invention also can be applicable to if photomask produces the aligning mistake of other direction.
In sum, the present invention carried out a top rake step, to remove the corner, top of the hard mask layer that exposes because of aligning mistake before contact window forms, so that hard mask layer has bigger patterns of openings, and make that next the horizontal cross-section of preformed contact structures becomes big.Thus, the contact area of formed contact structures of subsequent technique and element can increase.Therefore, can avoid dwindling and cause contact resistance value to increase, reduce the problems such as service speed of element, and can improve the reliability and the rate of finished products of technology widely because of contact area.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (15)
1. the manufacture method of a double-metal inlaid structure comprises:
In a substrate, form a dielectric layer and a hard mask layer in regular turn;
In this hard mask layer, form a channel patterns;
Form the photoresist layer of a patterning in this substrate top, and the photoresist layer of this patterning has a contact window pattern, expose this hard mask layer of part in this contact window pattern;
Carry out a top rake step, remove the corner, top that exposes this hard mask layer in this contact window pattern;
Photoresist layer with this patterning is a mask, removes this dielectric layer of part, to form an opening in this dielectric layer;
Remove the photoresist layer of this patterning;
With this hard mask layer is mask, removes this dielectric layer of part to exposing this substrate surface, forming a contact window, and forms a groove simultaneously on this contact window; And
In this groove and this contact window, form a conductor layer.
2. the manufacture method of double-metal inlaid structure as claimed in claim 1, wherein this hard mask layer is a metal hard mask layer.
3. the manufacture method of double-metal inlaid structure as claimed in claim 2, wherein the material of this metal hard mask layer comprises titanium, titanium nitride, tantalum, tantalum nitride and tungsten nitride.
4. the manufacture method of double-metal inlaid structure as claimed in claim 1, wherein the formation method of this hard mask layer comprises chemical vapour deposition technique or physical vaporous deposition.
5. the manufacture method of double-metal inlaid structure as claimed in claim 1, wherein this top rake step comprises and carries out a bombardment technology.
6. the manufacture method of double-metal inlaid structure as claimed in claim 1, wherein the material of this conductor layer comprises metallic copper.
7. the manufacture method of double-metal inlaid structure as claimed in claim 1, wherein the formation method of this channel patterns comprises:
On this hard mask layer, form the photo anti-corrosion agent material layer of a patterning; And
Photo anti-corrosion agent material layer with this patterning is a mask, removes this hard mask layer of part to exposing this dielectric layer surface of part.
8. the manufacture method of double-metal inlaid structure as claimed in claim 1, wherein the material of this dielectric layer comprises advanced low-k materials.
9. double-metal inlaid structure comprises:
One substrate;
One dielectric layer is positioned in this substrate;
One hard mask layer is positioned on this dielectric layer;
One first contact structures are arranged in this dielectric layer, and the horizontal cross-section of these first contact structures has asymmetric sphering profile; And
One lead is arranged in this hard mask layer and this dielectric layer, and is positioned on these first contact structures and with it and is electrically connected, and wherein this lead has side direction protuberance, and this side direction protuberance is positioned on this first contact structures edge.
10. double-metal inlaid structure as claimed in claim 9, wherein this hard mask layer is a metal hard mask layer.
11. double-metal inlaid structure as claimed in claim 10, wherein the material of this metal hard mask layer comprises titanium, titanium nitride, tantalum, tantalum nitride and tungsten nitride.
12. double-metal inlaid structure as claimed in claim 9 also comprises one second contact structures, is disposed between this substrate and this lead, and adjacent with these first contact structures, the horizontal cross-section of these second contact structures has the sphering profile of symmetry.
13. double-metal inlaid structure as claimed in claim 9, wherein these first contact structures, these second contact structures are identical with this conductor material, and its material comprises a conductor material.
14. double-metal inlaid structure as claimed in claim 13, wherein this conductor material comprises metallic copper.
15. double-metal inlaid structure as claimed in claim 9, wherein the material of this dielectric layer comprises advanced low-k materials.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005101038651A CN100423228C (en) | 2005-09-16 | 2005-09-16 | Dual-metal inserting structure and producing method thereof |
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| CNB2005101038651A CN100423228C (en) | 2005-09-16 | 2005-09-16 | Dual-metal inserting structure and producing method thereof |
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| CN1933123A CN1933123A (en) | 2007-03-21 |
| CN100423228C true CN100423228C (en) | 2008-10-01 |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127263A (en) * | 1998-07-10 | 2000-10-03 | Applied Materials, Inc. | Misalignment tolerant techniques for dual damascene fabrication |
| US6156643A (en) * | 1998-11-06 | 2000-12-05 | Advanced Micro Devices, Inc. | Method of forming a dual damascene trench and borderless via structure |
| US6376366B1 (en) * | 2001-05-21 | 2002-04-23 | Taiwan Semiconductor Manufacturing Company | Partial hard mask open process for hard mask dual damascene etch |
| CN1459844A (en) * | 2002-04-17 | 2003-12-03 | 三星电子株式会社 | Method for forming double Damascus interconnecting by using low-K dielectric material |
| CN1490867A (en) * | 2002-08-21 | 2004-04-21 | �����ɷ� | Semiconductor device and manufacturing method thereof |
| US20040137711A1 (en) * | 2002-10-30 | 2004-07-15 | Takatoshi Deguchi | Method for manufacturing semiconductor device |
| US20040157453A1 (en) * | 2002-12-31 | 2004-08-12 | Applied Materials, Inc. | Method of forming a low-K dual damascene interconnect structure |
| US20040166666A1 (en) * | 2000-07-24 | 2004-08-26 | Tatsuya Usami | Semiconductor device and method of manufacturing the same |
| US20040219796A1 (en) * | 2003-05-01 | 2004-11-04 | Chih-Ning Wu | Plasma etching process |
-
2005
- 2005-09-16 CN CNB2005101038651A patent/CN100423228C/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127263A (en) * | 1998-07-10 | 2000-10-03 | Applied Materials, Inc. | Misalignment tolerant techniques for dual damascene fabrication |
| US6156643A (en) * | 1998-11-06 | 2000-12-05 | Advanced Micro Devices, Inc. | Method of forming a dual damascene trench and borderless via structure |
| US20040166666A1 (en) * | 2000-07-24 | 2004-08-26 | Tatsuya Usami | Semiconductor device and method of manufacturing the same |
| US6376366B1 (en) * | 2001-05-21 | 2002-04-23 | Taiwan Semiconductor Manufacturing Company | Partial hard mask open process for hard mask dual damascene etch |
| CN1459844A (en) * | 2002-04-17 | 2003-12-03 | 三星电子株式会社 | Method for forming double Damascus interconnecting by using low-K dielectric material |
| CN1490867A (en) * | 2002-08-21 | 2004-04-21 | �����ɷ� | Semiconductor device and manufacturing method thereof |
| US20040137711A1 (en) * | 2002-10-30 | 2004-07-15 | Takatoshi Deguchi | Method for manufacturing semiconductor device |
| US20040157453A1 (en) * | 2002-12-31 | 2004-08-12 | Applied Materials, Inc. | Method of forming a low-K dual damascene interconnect structure |
| US20040219796A1 (en) * | 2003-05-01 | 2004-11-04 | Chih-Ning Wu | Plasma etching process |
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| CN1933123A (en) | 2007-03-21 |
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