CN100417224C - Optical fiber transmitting and housekeeping method of charge coupled camera image data - Google Patents
Optical fiber transmitting and housekeeping method of charge coupled camera image data Download PDFInfo
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- CN100417224C CN100417224C CNB2005100300878A CN200510030087A CN100417224C CN 100417224 C CN100417224 C CN 100417224C CN B2005100300878 A CNB2005100300878 A CN B2005100300878A CN 200510030087 A CN200510030087 A CN 200510030087A CN 100417224 C CN100417224 C CN 100417224C
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Abstract
The present invention relates to an optical fiber transmission and housekeeping method of charge coupled camera image data. The steps of the present invention is combined with a CCD imaging fibre transmission circuit for serially connecting and connecting in parallel / connecting in parallel and serially connecting a converting circuit to implement point-to-point optical fiber transmission. The detection and recovery are carried out by an 8 B / 10 B encode circuit when the optical fiber transmission has error. A frame synchronization signal, a word synchronization signal and other sequence control signals are generated by a logic programmable device, and a synchronous head and a serial number are added on each frame of data. The CCD image data is transmitted and recovered to a frame of data after packed, and an optical fiber link is formed by conversion of electro-optic / optic-electro by using an optical fiber receiver-transmitter module. The method of the present invention is suitable for optical fiber transmission and computer collection of linear array and surface array CCD image data.
Description
Technical field
The present invention relates to the Optical Fiber Transmission and the method for sorting that are used for electric charge coupling (CCD) camera remote sensing system of a kind of optical fiber transmission method of remote sensing camera view data, particularly a kind of simple general-purpose.
Background technology
Along with fast development of computer technology, the remote sensing system begins to adopt computer to control.But the preposition amplification system of remote-sensing detector very easily is subjected to the interference of the high-frequency digital signal of computer-internal, influences the signal to noise ratio of CCD camera image.Solution commonly used is to utilize the photoelectricity coupling that preposition amplification system and computer are isolated.
Optical fiber is to utilize light to carry out an emerging technology of communication.Increasingly mature and popular along with optical fiber transmission technique used the transmission medium of optical fiber as first-selection more and more in the remotely sensed image system.Utilize the natural characteristic of optical fiber, can avoid the high-frequency digital signal of computer-internal to be coupled into responsive detector circuit by communication link.Moreover, optical fiber can also provide great communication bandwidth and speed, and the distance of communication and transmission is extended greatly.
Summary of the invention
The object of the present invention is to provide a kind of optical fiber transmission method that is used for CCD camera remote sensing system of simple general-purpose.During CCD work, at first empty by the residual charge of reset pulse with the shift LD output, then under exposure and transfer pulse control, CCD is as quick cell translation light signal, parallel transferring in the shift register, last, the charge signal serial output in the transfer signal control shift register, after the A/D conversion, will simulate the ccd image data conversion is digital video signal.In view of the DID of CCD is a frame one frame, come the transmission of CCD view data with optical fiber, key is in the view data packing of transmitting terminal with a frame one frame, and correctly recover the view data of a frame one frame at receiving terminal, at last view data is put in order, and correctly be transferred to computer PCI bus and store and handle.
Technical scheme of the present invention is as follows:
According to a kind of CCD imaging fibre transmission circuit that is used for the remote sensing system of the present invention, comprise string also/parallel-to-serial converter, 8/10 encoding and decoding and checking circuit, programable logic device, framer (realizing), metadata cache device, optical fiber transceiver module etc. by the programable logic device programming.Wherein go here and there also/also the string conversion is the step that point-to-point Optical Fiber Transmission must be carried out, 8/10 codings make and can detect and recover when Optical Fiber Transmission is made mistakes, programable logic device is used to produce frame synchronization, word sync signal and other timing control signals, simultaneously, for the ease of follow-up data processing, need in every frame data, add synchronous head and sequence number by programable logic device.Framer is used for and will reverts to the data of a frame one frame after the ccd image packing data again, and the metadata cache device is used for buffer memory ccd image data and exports to the optical fiber transmission circuit, and the optical fiber transceiver module is used to carry out electric light/opto-electronic conversion and forms optical fiber link.
Step according to the Optical Fiber Transmission of a kind of airborne CCD camera image data of the present invention and method for sorting is as follows: wherein,
The step of the transmission of the optical fiber of view data is mainly:
1, ccd image is carried out the A/D conversion, become digital picture, and be buffered in the buffer memory device;
2, by programable logic device every frame data are added synchronous head and sequence number;
If 3 A/D conversion back bit data number is 16, then it is divided into most-significant byte and least-significant byte, and exports to the optical fiber transmission circuit successively; If not enough 16, then replenish into 16 with 0; If greater than 16 (relatively rare), the figure place that then will exceed 16 also is transformed into 8 outputs, 8 of less thaies are replenished into 8 with 0, and are high-order preceding, low level after;
4,8 parallel-by-bits input data (D0-D7) are carried out 8/10 codings, and produce control word simultaneously, for framing is prepared;
5, be converted to the high-speed-differential serial bit stream again, send the optical fiber sending module then, carry out the electric light conversion, pass through Optical Fiber Transmission;
The key step that the optical fiber of view data receives is:
1, carries out opto-electronic conversion by optic fiber transceiver module, convert PECL high-speed-differential serial bit stream to;
2, the high-speed-differential serial bit stream is gone here and there and change and 10/8 decodings, obtain 8 parallel-by-bit data flow;
3, judge that by control word the parallel data stream of receiving is ccd image data or control character, and the recovery view data is frame data;
4, by 8/10 coding checkouts, control makes mistakes;
5,8 parallel-by-bit data flow are sent into FPGA and be merged into 32, to make full use of pci bus;
6,32 bit data streams after merging are sent into the buffer memory device, for Computer Storage is got ready;
7, use programable logic device to produce needed clock of PCI high-speed data acquisition card and frame synchronizing signal, view data is correctly collected computer memory system.
Advantage of the present invention is a simple general-purpose, is applicable to the Optical Fiber Transmission and the computer acquisition of linear array and Array CCD data.
Description of drawings
Fig. 1 is the optical fiber transmitting terminal data format schematic diagram among the present invention.
Fig. 2 is the optical fiber transmitting terminal hardware handles block diagram among the present invention.
Fig. 3 is the CPLD program flow diagram among the present invention.
Fig. 4 is the optical fiber receiving terminal hardware handles block diagram among the present invention.
Fig. 5 is the whole transmission farming status of processes transition diagram among the present invention.
Embodiment
Provide one of the present invention embodiment preferably according to Fig. 1-Fig. 5 below, and elaborate for example to grow alignment three-linear array CCD (each alignment comprises 10200 pixels, comprises three alignments of red, green, blue).
After the CCD simulated image data is changed (16 quantifications) through AD, become the DID of a frame one frame, add synchronous head and sequence number by programming device again.Synchronous head is the sign that every frame image data begins, with high-low level sequence 0101010110101010 (0 * 55AA) expression clocklike; Sequence number then can be used for checking and leak frame, represents that with the 16bits signless integer excursion is 0～65535, progressively increases to 65535 back circulations from 0.
After 1 pair of picture signal of one tunnel AD converter part was carried out the A/D conversion among Fig. 1,16 ccd image data were converted to 8 parallel-by-bit data and deposit dual port RAM 2 in, and produced synchronous head and sequence number by 3 pairs of every frame data of programming device, and form is 0 * 55; 0XAA; Sequence number H; Sequence number L; Pixel H; Pixel L (as shown in Figure 1) enters optical fiber link 4 again.
8 parallel-by-bit data enter the hardware handles circuit block diagram of the arrangement before the optical fiber link 4 such as Fig. 2 (total identical three road ccd signal treatment circuits only draw a tunnel) shown in.Control with 3 pairs three road signals of programming device, produce needed timing control signal.Hardware encoding among Fig. 2 shown in empty frame arrangement unit 4 ' realizes that with discrete component or integrated chip CY7B923 or other chip phase-locked loop 43 ' produces via 10 required frequency multiplication high-frequency clocks of data flow behind 42 ' 8/10 codings of encoder.The 8 parallel-by-bit data flow that have synchronous head and sequence number enter input register 41 ', 8/10 codings that encoded device 42 ' carried out have the double action that makes the Optical Fiber Transmission current balance type and be convenient to error detection, are specific filling control character or valid data according to the coding control signal SCD and the marking signal SVS that makes mistakes with digital coding simultaneously.In rising edge of clock signal, if the SCD signal is a high level, 8 parallel-by-bit digital coding are specific control word, if be low level, 8 parallel-by-bits input digital coding is valid data; Simultaneously, if the SVS signal is a high level, by SCD state and 8 parallel-by-bit data decision coded system, if low level shows and make a mistake that 8 parallel-by-bits input data are left in the basket, and are encoded to the control word of makeing mistakes and send to receiving terminal.The function of optical fiber sending module 5 is that highspeed serial data stream PECL is converted to light signal, and arrives photoelectric conversion module 6 shown in Figure 4 through Optical Fiber Transmission.
At the optical fiber transmitting terminal, the flow process of programmable logic device (CPLD) program 100 as shown in Figure 3.The digital coding output of ENA signal controlling input or insertion null character (NUL) coding (1, insert null character (NUL); 0, coding output), the output of OEL control dual port RAM (1, can not export; 0, output); RWL be the dual port RAM read-write control signal (1, read effectively; 0, with imitating); Counter is 16 digit counters, represents the pixel number of every frame.
After said procedure 100 starts, execution in step 1000,100 initialization of CPLD program, the address of dual port RAM is 0, counting=1, then is execution in step 1001 judged counting=1? if counting does not wait 1, execution in step 1003; If counting=1, then execution in step 1002, read OEL=1, EVA=1, and RWL=0 writes 0 * 55 to dual port RAM, and the dual port RAM address adds 1, and counts adds 1, and is execution in step 1003 judged counting=2? if be not equal to 2, execution in step 1005; If equal 2, then execution in step 1004, read OEL=1, ENA=1, and RWL=0 writes 0 * 55 to dual port RAM, and the dual port RAM address adds 1, and counts adds 1, and execution in step 1005 judges whether counts equals 3, if be not 3, execution in step 1007; If equal 3, then execution in step 1006, as state OEL=1, ENA=1, RWL=0, just to the most-significant byte counting, send dual port RAM, the dual port RAM address adds 1, and counts adds 1, execution in step 1007 judges whether counts equals 4, if be not equal to 4, execution in step 1009; If equal 4, then execution in step 1008, as state DEL=1, and ENA=1, RWL=0, the counting least-significant byte is delivered to dual port RAM, the zero clearing of dual port RAM address, execution in step 1009; Judge whether 5≤counts≤20408? if not, execution in step 10011; If true, then execution in step 10010, as state OEL=0, ENA=0, RWC=1, the AD data output to optical fiber, and the dual port RAM address adds 1, and counts adds 1, is execution in step 10011 judged Counter=others? if not, execution in step 10013, EP (end of program); If true, then execution in step 10012, as state DEL=1, and ENA=1, the zero clearing of dual port RAM address, counting zero clearing, execution in step 10013, EP (end of program).
The block diagram of optical fiber receiving terminal data processing is seen Fig. 4.Light signal becomes the high-speed-differential serial bit stream behind photoelectric conversion module 5, go here and there again and change with 10/8 be decoded as 8 parallel-by-bit data.Shown in the empty frame among Fig. 4, data hardware arrangement decoding unit 7 can be realized by discrete component or integrated chip (as CY7B933).8 bit data enter field programmable gate array (FPGA) 9 by dual mode, a kind of is directly to link to each other with FPGA, another is through synchronous fifo device (FIFO) 8 (can realize with inside FIFO or the external independent F IFO of FPGA) control word to be filtered earlier, and valid data are deposited FIFO 8.The sequencing control slightly more complicated of first kind of implementation.Be organized into 32 data flow (after also can adding synchronous head and sequence number arrangement so that frame is leaked in check) again through 8 bit data through FPGA 9, the inside FIFO that sends to FPGA 9 again (realizes SOC (system on a chip), reduce wiring, also can use external FIFO), will become the pci bus that continuous data flow outputs to computer 10 behind the metadata cache.Line synchronizing signal and external trigger word that the row that FPGA 9 also be responsible for to produce FIFO is read enable signal and wordclock signal, pci data capture card 101 allow read clock signal, write pci bus when data are read FIFO, deposit data in SCSI hard disk 102 (not describing in detail) here by dma mode.
FPGA realizes that with synchronous finite state machine sequencing control and data shift as shown in Figure 5, and one has 14 states.The process of subordinate list 1 explanation data preparation state exchange.
Table 1 data preparation state exchange
| Clock sequence | State machine state | R passage input data (8bit) | G passage input data (8bit) | B passage input data (8bit) | Dateout (32bit) | |
| 0 | S0 | × | × | × | ×××× | Init |
| 1 | S1 | × | × | × | ×××× | |
| 2 | S2 | A0 | B0 | C0 | ×××× | * expression output is invalid |
| 3 | S3 | A1 | B1 | C1 | ×××× | |
| 4 | S4 | A2 | B2 | C2 | ×××× | |
| 5 | S5 | A3 | B3 | C3 | ×××× | |
| 6 | S6 | A4 | B4 | C4 | A0A1A2A3 | |
| 7 | S7 | A5 | B5 | C5 | B0B1B2B3 | |
| 8 | S8 | A6 | B6 | C6 | C0C1C2C3 | |
| ? ? 9 | ? ? S9 | ? ? A3 | ? ? B3 | ? ? C3 | ? ? ×××× | A4A5A6 is deposited respectively in the A0A1A2 register, and B4B5B6C4C5C6 changes 6 then in the B0B1B2C0C1C2 register, repeats to finish up to delegation between 6 and 9 |
| ? 10 | ? S10 | ? × | ? × | ? × | ? A0A1A2A3 | Because it is full that delegation's end mark is a linage-counter, thus three groups of last data are sent during every line endings, otherwise lose last data |
| 11 | S11 | × | × | × | B0B1B2B3 | |
| 12 | S12 | × | × | × | C0C1C2C3 | Delegation finishes, and returns 1 |
| 13 | S13 | Wait state |
Also will add state S0 and S1, S0 carries out initial work, to FIFO and register, counter initialization; After system powers on, at first enter the S0 state, then enter the S1 state.The S1 state is sought the synchronous head of delegation's view data, beginning delegation's Imagery Data Recording and arrangement.The wait state that the S13 state adds for ease of debugging.
Wherein use 3 counter: ReframeCounter, TotalFrameCounter, TotalPixelCounter.ReframeCounter is the counter in the framing procedure (S1 state).TotalFrameCounter is that the every capable view data that receives adds sequence number, count range 0～65535,16bit, cycle count.TotalPixelCounter is the image data lines counting that receives, scope 0～20404,15bit, zero clearing after the full delegation.
State machine state shifts the control that is subjected to a plurality of input signals and current state.Input control signal comprises the index signal RVS that makes mistakes, receive ready signal RDY, control word designator SCD.The indication priority of wherein makeing mistakes is the highest, if make mistakes, abandons this line data, enters S1 state framing again at once.State transitions is controlled by counter ReframeCounter and TotalFrameCounter also, and the former determines whether framing is successful, begins new delegation; The latter determines whether delegation finishes; The state machine output signal comprises data output, and the FIFO written allowance signal becomes control frame signal RF.
Claims (3)
1. the Optical Fiber Transmission of an airborne CCD camera image data and method for sorting comprise: the optical fiber forwarding step of a. view data and the optical fiber receiving step of b. view data, wherein:
A. the optical fiber forwarding step of view data has:
A1. ccd image is carried out the A/D conversion and become DID, and be buffered in the memory device;
A2. by programable logic device every frame data are added synchronous head and sequence number;
If a3. A/D conversion back data bits is 16, then is divided into most-significant byte and least-significant byte, and exports to the optical fiber transmission circuit successively; If not enough 16 of data bits then is filled to 16 with 0, is divided into most-significant byte and least-significant byte again and exports to the optical fiber transmission circuit successively; If greater than 16, the figure place that then will exceed 16 also is transformed into 8 outputs, and 8 of less thaies are replenished into 8 with 0, and is high-order preceding, low level after;
A4. 8 parallel-by-bits input data are carried out 8/10 codings, and produce control word simultaneously, for framing is prepared;
A5. will convert the high-speed-differential serial bit stream to through the parallel data of 8/10 codings again, send the optical fiber sending module then, carry out the electric light conversion, give optic fiber transceiver module by Optical Fiber Transmission;
B. the optical fiber receiving step has:
B1. receive the light signal that optical fiber transmits by optic fiber transceiver module, carry out opto-electronic conversion and become the high-speed-differential serial bit stream;
B2. electric high-speed-differential serial bit stream is gone here and there and change and 10/8 decodings, obtain 8 parallel-by-bit data flow;
B3. judge that by control word the parallel data stream of receiving is ccd image data or control character, recovering view data is frame data;
B4. by 8/10 coding checkouts, control makes mistakes;
B5. 8 parallel-by-bit data flow are sent into FPGA and be merged into 32 bit data streams;
B6. 32 bit data streams after merging are deposited in the buffer memory device, for Computer Storage is got ready;
B7. use programable logic device to produce needed clock of PCI high-speed data acquisition card and frame synchronizing signal, view data is correctly collected computer memory system.
2. the Optical Fiber Transmission of airborne CCD camera image data according to claim 1 and method for sorting is characterized in that, the memory device of said buffer memory DID is FIFO device or dual port RAM device among the step a1.
3. the Optical Fiber Transmission of airborne CCD camera image data according to claim 1 and method for sorting is characterized in that, among the said step b5,8 parallel-by-bit data are sent into FPGA be merged into 32 bit data streams, and its implementation has two kinds, the one, directly send FPGA; Another is through synchronization fifo control word to be filtered earlier, and valid data are deposited the FIFO device, sends into FPGA again.
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100496095C (en) * | 2006-04-26 | 2009-06-03 | 中国科学院自动化研究所 | Distributed data transmission based high-speed video camera system |
| CN101841698A (en) * | 2010-04-22 | 2010-09-22 | 中国科学院长春光学精密机械与物理研究所 | Long-distance transfer system for video data |
| CN102158662A (en) * | 2011-04-15 | 2011-08-17 | 中国科学院长春光学精密机械与物理研究所 | Image data transmission circuit of satellite-borne high-resolution CCD (Charge Coupled Device) camera |
| CN102749855B (en) * | 2011-04-20 | 2014-05-07 | 南京普爱射线影像设备有限公司 | Image data transmission controller for gigabit network interface |
| CN102819006B (en) * | 2012-08-08 | 2014-03-19 | 中国人民解放军信息工程大学 | Broadband direction finding control method based on frequency domain correlation interferometer |
| CN106301381B (en) * | 2015-05-28 | 2019-07-23 | 华为技术有限公司 | Electric light 3-8 decoder |
| CN112685345A (en) * | 2019-10-18 | 2021-04-20 | 北京华航无线电测量研究所 | Parallel-serial conversion method based on FPGA |
| CN113985391B (en) * | 2021-09-15 | 2024-05-24 | 北京无线电测量研究所 | General radar data packaging and transmitting device and method |
| CN114785932B (en) * | 2022-04-29 | 2023-08-11 | 北京控制工程研究所 | Virtual high-speed camera array data buffer logic design method based on optical fibers |
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| JP2000092352A (en) * | 1998-09-17 | 2000-03-31 | Sony Corp | Video signal transmitter |
| JP2002010973A (en) * | 2000-06-27 | 2002-01-15 | Aasunetsuto Internatl:Kk | Single optical fiber endoscope device |
| CN2670958Y (en) * | 2003-11-05 | 2005-01-12 | 南京春辉科技实业有限公司 | Flexible fiber-optical multipath sensing devices |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000092352A (en) * | 1998-09-17 | 2000-03-31 | Sony Corp | Video signal transmitter |
| JP2002010973A (en) * | 2000-06-27 | 2002-01-15 | Aasunetsuto Internatl:Kk | Single optical fiber endoscope device |
| CN2670958Y (en) * | 2003-11-05 | 2005-01-12 | 南京春辉科技实业有限公司 | Flexible fiber-optical multipath sensing devices |
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Assignee: Shanghai Pacific Lan Dengguang device Co., Ltd. Assignor: Shanghai Inst. of Technical Physics, Chinese Academy of Sciences Contract record no.: 2011310000050 Denomination of invention: Optical fiber transmitting and housekeeping method of charge coupled camera image data Granted publication date: 20080903 License type: Exclusive License Open date: 20060329 Record date: 20110421 |
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