CN100413030C - Projection producing process and its structure - Google Patents
Projection producing process and its structure Download PDFInfo
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- CN100413030C CN100413030C CNB2005100997694A CN200510099769A CN100413030C CN 100413030 C CN100413030 C CN 100413030C CN B2005100997694 A CNB2005100997694 A CN B2005100997694A CN 200510099769 A CN200510099769 A CN 200510099769A CN 100413030 C CN100413030 C CN 100413030C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
This invention provides one protruding block process, which comprises the following steps: providing one crystal circle; forming one main surface of circle and forming at least first open into first light resistance layer; forming first copper column into first open; then forming one second light resistance layer and forming at least second open onto second layer with second open larger then first one to expose the first copper and first light resistance layer into second open; forming one second copper column into second open; finally forming one weld layer onto second copper column; removing first and second light resistance layers.
Description
Technical field
The present invention relates to a kind of semiconductor making method, particularly about a kind of bump manufacturing method of wafer.
Background technology
In semiconductor industry, (Integrated Circuits, production IC) mainly are divided into three phases to integrated circuit: the making of the manufacturing of wafer (wafer), integrated circuit (IC) and the encapsulation (Package) of integrated circuit etc.Wherein, bare chip (die) is via steps such as wafer manufacturing, circuit design, photoetching multiple tracks technology and cutting crystal wafers and finish, and each cuts formed bare chip by wafer, electrically connect via weld pad on the bare chip (Bonding Pad) and carrier (Carrier), to form a chip-packaging structure.This chip-packaging structure can be divided into: routing engages the chip-packaging structure of (wire bonding) type, the chip-packaging structure and the winding of chip bonding (flip chip bonding) type engages the chip-packaging structure three major types of (tape automatic bonding) type automatically.
Fig. 1～5 are depicted as the schematic flow sheet of existing a kind of wafer bumps manufacture method.At first, as shown in Figure 1, formed a ball substrate layer 110 on the surface of wafer 100 comprehensively, and covered a photoresist layer 120 on ball substrate layer 110.Then, as shown in Figure 2, the imaging technique that utilize exposure, develops forms a plurality ofly opens 122 in photoresist layer 120, and the position correspondence of opening 122 is positioned on the weld pad 102 of wafer 100.Afterwards, as shown in Figure 3, be mask (mask) with the photoresist layer, carry out the copper electroplating processes, make that the precipitate of copper can form the projection cube structure of similar copper post (copperpillar) 112 attached to being on the part surface of plating seed layer with ball substrate layer 110 in the electroplate liquid.Then, as shown in Figure 4, be mask with same photoresist layer 120, carry out scolder (solder) electroplating processes, with the solder layer 114 that forms similar mushroom (mushroom) shape on the surface of copper post 112.This solder layer 114 can be low-melting leypewter, but the therefore glomerate projection of reflow, externally to electrically connect the media of a circuit board (not shown) as each chip (not shown) on the wafer 100.
At last, as shown in Figure 5, remove photoresist layer 120, and the ball substrate layer 110 (the ball substrate layer 110a that keep copper post 112 bottoms) that do not covered by copper post 112 of etching.Afterwards, reflow solder layer 114 is so that solder layer 114 fusions are the solder projection 114a of sphere-like.
It should be noted that, because the solder layer 114 of copper post 112 and top thereof is formed in the opening 122 of same photoresist layer 120, therefore opening 122 degree of depth of photoresist layer 120 must be higher than the predetermined altitude of electro-coppering post 112, thereby cause problems such as exposure, development are difficult for.And solder layer 114 will protrude in photoresist layer 120 behind the opening 122 that fills up photoresist layer 120, make two adjacent solder layers 114 electrically connect mutually easily, thereby cause short circuit phenomenon, influence the reliability of follow-up encapsulation.In addition, the solder projection 114a of sphere-like also aggravates because of the speed that the lateral margin that attaches copper post 112 makes copper loss lose.
Therefore, for overcoming the defective that above-mentioned prior art exists, be necessary to provide a kind of bump manufacturing method of innovation, it can improve imaging effect, reduces copper loss and loses, and improve the reliability of encapsulation.
Summary of the invention
Main purpose of the present invention is to provide a kind of bump manufacturing method that is applicable to wafer, and this method can improve the quality of copper post and solder layer.
Another object of the present invention is to provide a kind of new projection cube structure that is applicable to wafer.
For achieving the above object, bump manufacturing method of the present invention comprises the following steps: at first, and a wafer is provided, and this wafer has a plurality of chips, and each chip has at least one weld pad, and this weld pad is positioned on the function surface of wafer; Form one first photoresist layer on the function surface of wafer, and form at least one first opening in first photoresist layer; And form one first bronze medal post in first opening; Then, form one second photoresist layer on first photoresist layer, and form at least one second opening in second photoresist layer, this second opening is less than first opening, thereby the part surface of the first bronze medal post is exposed in second opening; And form one second bronze medal post in second opening; Afterwards, form a solder layer on the second bronze medal post; At last, remove first and second photoresist layer.
Described according to specific embodiments of the invention, above-mentioned first, second photoresist layer all forms by being coated with a photosensitive material, and above-mentioned first, second opening then all forms by exposure, visualization way.
Described according to specific embodiments of the invention, after the above-mentioned step that wafer is provided, also comprise forming a circuit rerouting layer and/or a ball substrate layer on the function surface of wafer, and first opening manifests the part surface of ball substrate layer.Wherein, the mode of formation circuit rerouting layer comprises sputter, evaporation or plating.In the step that forms the first bronze medal post, ball substrate layer is the plating seed layer in the immersion plating liquid, so that the precipitate of copper is attached on the ball substrate layer in first opening.In addition, form in the step of the second bronze medal post, ball substrate layer also is the plating seed layer as immersion plating liquid, so that the precipitate of copper is attached on the first bronze medal post and first photoresist layer on every side thereof in second opening.
The present invention has proposed a kind of projection cube structure that is applicable to chip simultaneously, and this chip has at least one weld pad, and this weld pad is positioned on the function surface of chip.This projection cube structure comprises one first cylinder, one second cylinder and a scolder.First cylinder has one first end and one second end, and first end is connected with weld pad.Second cylinder is arranged on second end of first cylinder, and the cross section of second cylinder is less than the cross section of first cylinder.Scolder then is arranged on second cylinder.
Described according to specific embodiments of the invention, above-mentioned first cylinder and second cylinder have constituted a convex cylinder jointly, and the shape of scolder is a spheroid or hemisphere shape, and scolder can attach the lateral margin at second cylinder.In addition, above-mentioned projection cube structure has also comprised a ball substrate layer, and it is electrically connected between first end of the weld pad and first cylinder.
Compared with prior art, the present invention has adopted multiple tracks technology forming first, second photoresist layer of different openings size, and forms the first bronze medal post and the second bronze medal post respectively in first opening and second opening.The convex cylinder top that first cylinder and second cylinder constitute is provided with a solder layer, and this solder layer can attach the lateral margin at the second bronze medal post after reflow, but can not attach the first bronze medal post.Therefore, can avoid effectively that the solder layer that exists in the prior art is improper to attach this phenomenon of copper post lateral margin, thereby effectively reduce the copper loss.
The present invention is further illustrated below in conjunction with accompanying drawing and embodiment.
Description of drawings
Fig. 1～5 are the schematic flow sheet of existing a kind of wafer bumps manufacture method.
Fig. 6～14 are the schematic flow sheet of a kind of bump manufacturing method of the present invention's one specific embodiment.
Embodiment
Relevant detailed description of the present invention and technology contents, existing as follows with regard to accompanying drawings:
Fig. 6～14 are the schematic flow sheet of a kind of bump manufacturing method of the present invention's one specific embodiment.At first, as shown in Figure 6, provide a wafer 200, this wafer 200 has a plurality of chips (not shown), has a plurality of weld pads 202 on the function surface of each chip and is emerging in the opening of protective layer 204.Then, form a ball substrate layer (UBM) 210 on the surface of wafer 200, this ball substrate layer 210 can be formed and constituted a multiple layer metal layer by metals such as copper, nickel, vanadium, chromium comprehensively.This ball substrate layer 210 can sputter, the mode of evaporation or plating is formed on the surface of wafer 200, with the Seed Layer as subsequent copper post and solder layer electroplating processes.In addition, the chip structure of the corresponding different connecting point positions of the function surface of wafer 200 can be made circuit rerouting layer (re-distribution layer, RDL) (not shown) again, and on circuit rerouting layer, form above-mentioned ball substrate layer 210, to carry out follow-up electroplating technology.
Then, be coated with a photosensitive material on ball substrate layer 210, to form one first photoresist layer 220.
Then, as shown in Figure 7, the imaging technique that utilize exposure, develops forms a plurality of first openings 222 in first photoresist layer 220, and this first opening 222 manifests the ball substrate layer 210 of its bottom respectively.Then, as shown in Figure 8, be that plating seed layer carries out the copper electroplating processes with ball substrate layer 210, open in 222 first with the first bronze medal post 212 that forms suitable height.Wherein, the height of copper post 212 can be by the parameters such as concentration, current time/amperage of copper ion in the control electroplate liquid, thereby the precipitate that makes copper is attached on the ball substrate layer 210 and can fill up first opening 222.As Fig. 7, shown in Figure 8, because the opening depth H 1 of first photoresist layer 220 equals the predetermined altitude of the first bronze medal post 212 substantially, therefore exposure, development will be more accurate, and be difficult for being affected.
Then, as shown in Figure 9, the coating photosensitive material is to form second photoresist layer 230.Unlike the prior art be, the present invention has formed second photoresist layer 230 of smaller opening size W on first photoresist layer 220, second opening 232 of this second photoresist layer 230 is formed on the part surface of copper post 214 with the imaging technique of exposure, development equally, and promptly the size W of second opening 232 opens 222 size less than first of its below.
Then, as shown in figure 10, on the first bronze medal post 212, carry out the copper electroplating processes second time, so that one second bronze medal post 214 is formed on the surface of the first bronze medal post 212.This second bronze medal post 214 can be cylinder or cuboid, and its cross section W1 is less than the cross section W2 of the first bronze medal post 212, thereby makes the outward appearance of first, second copper post 212,214 be a convex cylinder.Structurally, an end of the first bronze medal post 212 links to each other with the second bronze medal post 214, but the cross section W1 of the second bronze medal post 214 is less than the cross section W2 of the first bronze medal post 212, and the cross-sectional area of the second bronze medal post 214 is less than about 80% of the cross-sectional area of the first bronze medal post 212.
Then, as Figure 11, shown in Figure 12, form a solder layer 216 on the second bronze medal post 214 in the mode of electroplating or print.Form the words of solder layer 216 with plating mode, also can further form one the 3rd photoresist layer 240 on second photoresist layer 230, and can utilize exposure, the imaging technique that develops forms a plurality of the 3rd and opens 242 in the 3rd photoresist layer 240, then re-plating one scolder is in the 3rd opening 242, to form solder layer 216.Wherein, the material of solder layer 216 can be low-melting leypewter or other metal, and the height of solder layer 216 equally can be by the parameters such as concentration, current time/amperage of metal ion in the control electroplate liquid, so that the precipitate of metal is attached on the second bronze medal post 214 and fill up the 3rd and open 242, thereby form projection cube structure shown in Figure 12 on each weld pad 202 of chip.Wherein, the cross section W3 of solder layer 216 is more than or equal to the cross section W1 of the second bronze medal post 214, thereby makes the corresponding reduction of possibility of the phenomenon that is short-circuited between adjacent two solder layers 216.
Then, as shown in figure 13, remove first, second and third photoresist layer 220,230,240, and the ball substrate layer 210 (the ball substrate layer 210a that only keeps the first bronze medal post, 212 bottoms) that do not covered of etching by the first bronze medal post 212, follow reflow solder layer 216 shown in Figure 13 again, to form the solder projection 216a of sphere-like or hemisphere shape, as shown in figure 14.In the present embodiment, solder layer 216 attaches the lateral margin at the second bronze medal post 214, but can not attach the surface of the first bronze medal post 212, even therefore the copper of the second bronze medal post 214 runs off, also can not influence the height of the first bronze medal post 212.Therefore, after finishing the bump manufacturing method of electroplating first, second copper post 212,214 and solder layer 216 on the surface of wafer 200 successively, wafer 200 can be cut into a plurality of independently chips (not shown), and can electrically connect by above-mentioned projection between each chip and the external electronic (as circuit board), to transmit signal.
In sum, the technology that bump manufacturing method of the present invention utilized the coating of multiple tracks photoresistance, exposure, develop is to form the first different opening of opening size and second opening on first, second photoresist layer, in addition, the top of convex copper cylinder is provided with a solder layer, is difficult for attaching the lateral margin at the first bronze medal post after this solder layer reflow.Therefore, can effectively avoid the improper phenomenon that attaches copper post lateral margin of solder layer in the prior art, thereby effectively reduce the copper loss.In addition, the 3rd opening is more than or equal to second opening, so that the height of the 3rd photoresist layer can the 3rd opening of opening size reduces relatively because of using greatly, thereby improves imaging effect.In addition, also be difficult for the phenomenon that is short-circuited between adjacent two solder layers, thereby improved the reliability of encapsulation.
Claims (10)
1. a bump manufacturing method comprises the following steps:
One wafer is provided, and this wafer has a plurality of chips, and each chip has at least one weld pad, and this weld pad is positioned on the function surface of wafer;
Form one first photoresist layer on the function surface of described wafer, and form at least one first opening in this first photoresist layer;
Form one first bronze medal post in described first opening;
It is characterized in that: this bump manufacturing method also comprises the following steps: to form one second photoresist layer on described first photoresist layer, and form at least one second opening in this second photoresist layer, this second opening is exposed in this second opening the part surface of the described first bronze medal post less than first opening;
Form one second bronze medal post in described second opening;
Form a solder layer on the described second bronze medal post; And
Remove described first and second photoresist layer.
2. bump manufacturing method as claimed in claim 1 is characterized in that: described first, second photoresist layer all forms by being coated with a photosensitive material, and described first, second opening then all forms by exposure, visualization way.
3. bump manufacturing method as claimed in claim 1 is characterized in that: after this step of wafer is provided, also comprise forming a circuit rerouting layer on the function surface of described wafer.
4. bump manufacturing method as claimed in claim 1 is characterized in that: after this step of wafer is provided, also comprise forming a ball substrate layer on the function surface of described wafer, and described first opening manifests the part surface of this ball substrate layer.
5. bump manufacturing method as claimed in claim 4 is characterized in that: after removing this step of first and second photoresist layer, also comprise the ball substrate layer that removal is not covered by the described first bronze medal post.
6. bump manufacturing method as claimed in claim 1, it is characterized in that: before forming this step of solder layer, also comprise and form one the 3rd photoresist layer on described second photoresist layer, and form at least one the 3rd opening in the 3rd photoresist layer, to manifest the part surface of the described second bronze medal post, then this solder layer of re-plating is in the 3rd opening.
7. bump manufacturing method as claimed in claim 6 is characterized in that: after forming this step of solder layer, also comprise and remove described the 3rd photoresist layer.
8. projection cube structure, be applicable to a chip, this chip has at least one weld pad, this weld pad is positioned on the function surface of chip, this projection cube structure comprises one first cylinder, have one first end and one second end, this first end is connected with described weld pad, it is characterized in that: this projection cube structure has one second cylinder, be arranged on second end of described first cylinder, the cross section of this second cylinder is less than the cross section of described first cylinder, and first and second cylinder is common to constitute a convex cylinder thereby make; And a scolder, be arranged on described second cylinder.
9. projection cube structure as claimed in claim 8 is characterized in that: described scolder attaches the lateral margin at described second cylinder.
10. projection cube structure as claimed in claim 8 is characterized in that: projection cube structure also comprises a ball substrate layer, and this ball substrate layer is electrically connected between first end of described weld pad and described first cylinder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100997694A CN100413030C (en) | 2005-09-07 | 2005-09-07 | Projection producing process and its structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100997694A CN100413030C (en) | 2005-09-07 | 2005-09-07 | Projection producing process and its structure |
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| CN1929093A CN1929093A (en) | 2007-03-14 |
| CN100413030C true CN100413030C (en) | 2008-08-20 |
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| CNB2005100997694A Active CN100413030C (en) | 2005-09-07 | 2005-09-07 | Projection producing process and its structure |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101894766B (en) * | 2009-05-22 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing solder lug |
| CN102468186A (en) * | 2010-11-15 | 2012-05-23 | 无锡江南计算技术研究所 | Substrate manufacturing method and semiconductor chip packaging method |
| CN104768336B (en) * | 2014-12-17 | 2016-08-31 | 安捷利电子科技（苏州）有限公司 | A kind of interlayer interconnection process |
| CN110676175A (en) * | 2019-09-24 | 2020-01-10 | 浙江集迈科微电子有限公司 | Method for manufacturing large tin ball by bonding process |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6230400B1 (en) * | 1999-09-17 | 2001-05-15 | George Tzanavaras | Method for forming interconnects |
| CN1464529A (en) * | 2002-06-18 | 2003-12-31 | 联华电子股份有限公司 | Method for making welding pad |
| TW584936B (en) * | 2003-03-20 | 2004-04-21 | Advanced Semiconductor Eng | Wafer bumping process |
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2005
- 2005-09-07 CN CNB2005100997694A patent/CN100413030C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6230400B1 (en) * | 1999-09-17 | 2001-05-15 | George Tzanavaras | Method for forming interconnects |
| CN1464529A (en) * | 2002-06-18 | 2003-12-31 | 联华电子股份有限公司 | Method for making welding pad |
| TW584936B (en) * | 2003-03-20 | 2004-04-21 | Advanced Semiconductor Eng | Wafer bumping process |
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| CN1929093A (en) | 2007-03-14 |
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