CN100411146C - Method for fabricating strained-silicon CMOS transistors - Google Patents
Method for fabricating strained-silicon CMOS transistors Download PDFInfo
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- CN100411146C CN100411146C CNB2006101684367A CN200610168436A CN100411146C CN 100411146 C CN100411146 C CN 100411146C CN B2006101684367 A CNB2006101684367 A CN B2006101684367A CN 200610168436 A CN200610168436 A CN 200610168436A CN 100411146 C CN100411146 C CN 100411146C
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Abstract
A semiconductor substrate having a first active region and a second active region for fabricating a first transistor and a second transistor is provided. A first gate structure and a second gate structure are formed on the first active region and the second active region and a first spacer is formed surrounding the first gate structure and the second gate structure. A source/drain region for the first transistor and the second transistor is formed. The first spacer is removed from the first gate structure and the second gate structure and a cap layer is disposed on the first transistor and the second transistor and the cap layer covering the second transistor is removed thereafter. An etching process is performed to form a recess in the substrate surrounding the second gate structure. An epitaxial layer is formed in the recess and the cap layer is removed from the first transistor.
Description
Technical field
The present invention relates to a kind of method of making strained-silicon cmos transistors.
Background technology
Along with constantly dwindling of the live width of semiconductor technology, the size of MOS transistor also constantly develops towards microminiaturization, yet the live width of semiconductor technology has been developed under the situation of bottleneck at present, and how promoting carrier mobility has become the big problem of one in the present technical field of semiconductors with the speed that increases MOS transistor.In at present known technology, the existing MOS transistor of using strained silicon (strained silicon) as substrate, lattice constant and the different characteristic of monocrystalline silicon (single crystal Si) that it utilizes SiGe (SiGe) make silicon germanium extension layer produce on the structure strain and form strained silicon.Because the lattice constant (lattice constant) of germanium-silicon layer is bigger than silicon, this makes the band structure (band structure) of silicon change, and causes mobility of carrier to increase, and therefore can increase the speed of MOS transistor.
Please refer to Fig. 1 to Fig. 4, Fig. 1 to Fig. 4 is the existing schematic diagram of making a strained-silicon cmos transistors.As shown in Figure 1, at first provide one with shallow isolating trough (shallowtrench isolation, STI) 106 separate out the semiconductor-based end 100 of nmos pass transistor district 102 and PMOS transistor area 104, and respectively have a grid structure on each nmos pass transistor district 102 and the PMOS transistor area 104.Wherein, the NMOS grid structure comprises that a NMOS grid 108 and is located at NMOS grid 108 and the gate dielectric at the semiconductor-based end 100 114, and the PMOS grid structure comprises that then a PMOS grid 110 and is arranged at PMOS grid 110 and the gate dielectric at the semiconductor-based end 100 114.Then each forms one respectively by off normal clearance wall (offsetspacer) 112 that silica layer or silicon nitride layer constituted in the sidewall surfaces of NMOS grid 108 and PMOS grid 110.
Carry out an ion implantation technology then, respectively to form a lightly doped drain (lightly doped drain, LDD) 118 and 119 in NMOS grid 108 and PMOS grid 110 at the semiconductor-based end 100 on every side.Then on the sidewall of NMOS grid 108 and PMOS grid 110, respectively form a clearance wall 113.Carry out another ion implantation technology subsequently, 102 respectively to form source territory 116 and 117 with around the clearance wall 113 of PMOS transistor area 104 in the nmos pass transistor district.And then carry out the annealing process that is rapidly heated, utilize 900 to 1050 ℃ high temperature to activate regions and source 116 and 117 interior alloys, and repair the lattice structure on surface, the semiconductor-based ends 100 impaired in each ion implantation technology simultaneously, 102 to form nmos pass transistors 132 and to form a PMOS transistor 134 in PMOS transistor area 104 in the nmos pass transistor district.
As shown in Figure 2, utilize nmos pass transistor district 102 to be used as mask then and carry out an etch process, in the semiconductor-based end 100 that is not covered, respectively to form a groove 120 by NMOS grid 108 and PMOS grid 110 with the grid structure of PMOS transistor area 104.As shown in Figure 3, carry out a selective epitaxial growth process subsequently, in the groove 120 of nmos pass transistor district 102 and PMOS transistor area 104, to insert one by epitaxial loayer 122 that SiGe was constituted.
As shown in Figure 4, then cover one by metal level that nickel constituted (figure does not show) on nmos pass transistor 132 and PMOS transistor 134, carry out annealing (the rapid thermalanneal that is rapidly heated then, RTA) technology, make metal level become metal silicide layer 115, finish and aim at metal silicide technology (salicide) voluntarily with the partial reaction that NMOS grid 108, PMOS grid 110 and regions and source 116 contact with 117.
It should be noted that to have now when making strained-silicon cmos transistors, to form clearance wall usually earlier, and then in the relative regions and source of nmos pass transistor district and PMOS transistor area, insert epitaxial loayer in the sidewall of grid.Though this practice can utilize the SiGe in the epitaxial loayer to promote moving of charge carrier in the substrate, because the obstruct of clearance wall, SiGe also can't be especially near channel region in substrate, and then can't significantly promote the transistorized usefulness of CMOS.
Summary of the invention
Therefore main purpose of the present invention provides a kind of method of making strained-silicon cmos transistors, to improve above-mentioned existing problem.
The present invention discloses the transistorized method of a kind of making strained-silicon cmos (strained-siliconCMOS).At first, the semiconductor substrate is provided, this semiconductor-based end have one first active region in order to prepare a first transistor, at least one second active region is located between this first active region and this second active region in order to prepare a transistor seconds and an insulation system.Form then at least one first grid structure on this first active region with at least one second grid structure on this second active region.Then form one first clearance wall respectively in this first grid structure and this second grid structure periphery and the source electrode and the drain region that form source electrode and drain region and this transistor seconds of this first transistor respectively.Remove subsequently this first grid structure and this second grid structure periphery first clearance wall, cover a covering layer in this first transistor and this transistor seconds surface and this covering layer of removing this transistor seconds surface.Carry out an etch process then, around on the grid structure of this transistor seconds, reaching, respectively form a groove, (selective epitaxial growth, SEG) technology is to form an epitaxial loayer respectively in this groove then to carry out a selective epitaxial growth again.Remove this covering layer on this first transistor surface at last.
The present invention discloses the transistorized method of a kind of making strained-silicon cmos (strained-siliconCMOS), its mainly be utilize stressor layers and epitaxial loayer simultaneously should be used for promoting nmos pass transistor and the transistorized overall efficiency of PMOS.As described in previous embodiment, the present invention can cover one earlier and have the covering layer of stress on nmos pass transistor and PMOS transistor, remove the stressor layers on the PMOS transistor then, then in the transistorized regions and source of PMOS, form groove and insert epitaxial loayer, utilize epitaxial loayer to promote the transistorized hole mobility of PMOS when making stressor layers promote the nmos pass transistor electron mobility by tensile stress.In addition, the present invention can remove the clearance wall that is positioned on each transistorized grid structure earlier again before forming covering layer.This practice can make the stressor layers on the follow-up covering transistor and insert the more approaching transistorized channel region of epitaxial loayer of substrate, and then promotes transistorized electronics and hole mobility.
Description of drawings
Fig. 1 to Fig. 4 is the existing schematic diagram of making a strained-silicon cmos transistors;
Fig. 5 to Fig. 12 makes the schematic diagram of a strained-silicon cmos transistors for the present invention;
Figure 13 to Figure 20 makes the schematic diagram of a strained-silicon cmos transistors for another embodiment of the present invention.
The main element symbol description
Nmos pass transistor district, the 100 semiconductor-based ends 102
104 PMOS transistor area, 106 shallow isolating trough
108 NMOS grids, 110 PMOS grids
112 off normal clearance walls, 113 clearance walls
114 gate dielectrics, 115 metal silicide layers
116 regions and source, 117 regions and source
118 lightly doped drains, 119 lightly doped drains
120 grooves, 122 epitaxial loayers
132 nmos pass transistors, 134 PMOS transistors
Nmos pass transistor district, the 200 semiconductor-based ends 202
204 PMOS transistor area, 206 shallow isolating trough
208 NMOS grids, 210 PMOS grids
212 off normal clearance walls, 213 clearance walls
214 gate dielectrics, 215 metal silicide layers
216 regions and source, 217 regions and source
218 lightly doped drains, 219 lightly doped drains
220 covering layers, 224 grooves
226 epitaxial loayers, 228 clearance walls
230 contact hole etching stopping layer 232 nmos pass transistors
The 300 semiconductor-based ends of 234 PMOS transistors
302 nmos pass transistor districts, 304 PMOS transistor area
306 Jian ditches are isolated 308 NMOS grids
310 PMOS grids, 312 off normal clearance walls
313 clearance walls, 314 gate dielectrics
315 metal silicide layers, 316 regions and source
317 regions and source, 318 lightly doped drains
319 lightly doped drains, 320 resilient coatings
322 stressor layers, 324 grooves
326 epitaxial loayers, 328 contact hole etching stopping layers
332 nmos pass transistors, 334 PMOS transistors
Embodiment
Please refer to Fig. 5 to Figure 12, Fig. 5 to Figure 12 makes the schematic diagram of a strained-silicon cmos transistors for the present invention.As shown in Figure 5, at first provide one with shallow isolating trough (shallowtrench isolation, STI) 206 separate out the semiconductor-based end 200 of nmos pass transistor district 202 and PMOS transistor area 204, and respectively have a grid structure on each nmos pass transistor district 202 and the PMOS transistor area 204.Wherein, the NMOS grid structure comprises that a NMOS grid 208 and is located at NMOS grid 208 and the gate dielectric at the semiconductor-based end 200 214, and the PMOS grid structure comprises that then a PMOS grid 210 and is arranged at PMOS grid 210 and the gate dielectric at the semiconductor-based end 200 214.Then each forms one respectively by off normal clearance wall (offsetspacer) 212 that silica layer or silicon nitride layer constituted in the sidewall surfaces of NMOS grid 208 and PMOS grid 210.
Carry out an ion implantation technology then, respectively to form a lightly doped drain (lightly doped drain, LDD) 218 and 219 in NMOS grid 208 and PMOS grid 210 at the semiconductor-based end 200 on every side.Then on the sidewall of NMOS grid 208 and PMOS grid 210, respectively form a clearance wall 213.Carry out another ion implantation technology subsequently, 202 respectively to form source territory 216 and 217 with around the clearance wall 213 of PMOS transistor area 204 in the nmos pass transistor district.And then carry out the annealing process that is rapidly heated, utilize 900 to 1050 ℃ high temperature to activate regions and source 216 and 217 interior alloys, and repair the lattice structure on surface, the semiconductor-based ends 200 impaired in each ion implantation technology simultaneously, 202 to form nmos pass transistors 232 and to form a PMOS transistor 234 in PMOS transistor area 204 in the nmos pass transistor district.
As shown in Figure 6, then remove the clearance wall 213 that is positioned at NMOS grid 208 and PMOS grid 210 sidewalls.
Then as shown in Figure 7, cover a covering layer 220 on the nmos pass transistor 232 and PMOS transistor 234 of nmos pass transistor district 202 and PMOS transistor area 204.According to a preferred embodiment of the invention, covering layer 220 can be one by silica layer that oxide constituted or by stressor layers that silicon nitride constituted.For instance, covering layer 220 can be a high tensile stress film (high tensile stress film) with tensile stress, and nmos pass transistor of the present invention 232 can promote the electron mobility of nmos pass transistor 232 by this high tensile stress film.
As shown in Figure 8, then remove the covering layer 220 that is positioned at PMOS transistor area 204, and then utilize the covering layer 220 in nmos pass transistor district 202 and PMOS grid 210 to be used as mask and carry out an etch process, respectively form a groove 224 with regions and source 217 in PMOS grid 210 tops and PMOS transistor area 204.
As shown in Figure 9, carry out the impurity that a cleaning removes groove 224 remained on surface then, and (selective epitaxial growth, SEG) technology is to form an epitaxial loayer 226 respectively in groove 224 to carry out a selective epitaxial growth.
As shown in figure 10, then remove the covering layer 220 that is positioned at nmos pass transistor 232 surfaces.
Form a clearance wall 228 as shown in figure 11, and then respectively in the sidewall surfaces of NMOS grid 208 with PMOS grid 210.Then cover one by the metal levels that material constituted such as nickel, cobalt, titanium, molybdenum (figure do not show) on nmos pass transistor 232 and PMOS transistor 234, carry out annealing (the rapid thermal anneal that is rapidly heated then, RTA) technology, make metal level become metal silicide layer 215, finish and aim at metal silicide technology (salicide) voluntarily with the partial reaction that NMOS grid 208, PMOS grid 210 and regions and source 216 contact with 117.
As shown in figure 12, then cover one by film that silicon nitride constituted on nmos pass transistor 232 and PMOS transistor 234, as follow-up contact hole etching stopping layer 230 when contacting hole technology.
It should be noted that, the present invention removes the main clearance wall on the gate lateral wall earlier when making strained-silicon cmos transistors, as before shown in Figure 6, in the regions and source of PMOS transistor area, insert epitaxial loayer then, as before shown in Figure 9.Intercept owing to there is no clearance wall between epitaxial loayer and the channel region, therefore can significantly promote the transistorized hole mobility of PMOS by the SiGe in the epitaxial loayer.In addition, when utilizing epitaxial loayer to promote the suffered stress of PMOS transistor, the present invention covers one in addition and has the high tensile stress film of stretching effect on nmos pass transistor, and promotes the electron mobility of nmos pass transistor by this film.
In addition, be not limited to previous described making step, the present invention can adjust each doped region or the formed time point of clearance wall according to the demand of product again.For instance, the present invention can be behind the grid 208,210 and 212 formation of off normal clearance wall of NMOS and PMOS, on the sidewall of grid structure 208,210, do not form clearance wall 213 earlier, and directly carry out an ion implantation technology, in the semiconductor-based end 200, to form the regions and source 216,217 of nmos pass transistor 232 and PMOS transistor 234.Secondly, the present invention also can form lightly doped drains 219 in PMOS transistor area 204 again after off normal clearance wall 212 forms, and after covering layer 220 is removed, and 202 forms lightly doped drains 218 in the nmos pass transistor district again.In addition, the present invention can form the regions and source 216,217 of nmos pass transistor 232 and PMOS transistor 234 again again after second clearance wall 228 forms.According to a preferred embodiment of the invention, above-mentioned processing step can be arranged in pairs or groups mutually, for example carries out simultaneously in same technology or carries out respectively in different process, and this all belongs to covering scope of the present invention.
Please refer to Figure 13 to Figure 20, Figure 13 to Figure 20 makes the schematic diagram of a strained-silicon cmos transistors for another embodiment of the present invention.As shown in figure 13, at first provide one with shallow isolating trough (shallow trench isolation, STI) 306 separate out the semiconductor-based end 300 of nmos pass transistor district 302 and PMOS transistor area 304, and respectively have a grid structure on each nmos pass transistor district 302 and the PMOS transistor area 304.Wherein, the NMOS grid structure comprises that a NMOS grid 308 and is located at NMOS grid 308 and the gate dielectric at the semiconductor-based end 300 314, and the PMOS grid structure comprises that then a PMOS grid 310 and is arranged at PMOS grid 310 and the gate dielectric at the semiconductor-based end 300 314.Then form one by off normal clearance wall (offset spacer) 312 that silica layer or silicon nitride layer constituted in the sidewall surfaces of NMOS grid 308 and PMOS grid 310 is out of the ordinary.
Carry out an ion implantation technology then, respectively to form a lightly doped drain (lightly doped drain, LDD) 318 and 319 in NMOS grid 308 and PMOS grid 310 at the semiconductor-based end 300 on every side.Then on the sidewall of NMOS grid 308 and PMOS grid 310, respectively form a clearance wall 313.Carry out another ion implantation technology subsequently, 302 respectively to form source territory 316 and 317 with around the clearance wall 313 of PMOS transistor area 304 in the nmos pass transistor district.And then carry out the annealing process that is rapidly heated, utilize 900 to 1050 ℃ high temperature to activate regions and source 316 and 317 interior alloys, and repair the lattice structure on surface, the semiconductor-based ends 300 impaired in each ion implantation technology simultaneously, 302 to form nmos pass transistors 332 and to form a PMOS transistor 334 in PMOS transistor area 304 in the nmos pass transistor district.
As shown in figure 14, then deposit a resilient coating 320 and a stressor layers 322 in regular turn on nmos pass transistor 332 and PMOS transistor 334.According to a preferred embodiment of the invention, resilient coating 320 can be silica and constitutes, and stressor layers 322 then can be made of silicon nitride.Wherein, stressor layers 322 can be a high tensile stress film (high tensile stress film) with tensile stress, and nmos pass transistor of the present invention 332 can promote the electron mobility of nmos pass transistor 332 by this high tensile stress film.
As shown in figure 15, then utilize a patterning photoresist layer (figure does not show) to be used as etching mask and remove the resilient coating 320 and stressor layers 322 that is covered in PMOS transistor area 304.Carry out the annealing process that is rapidly heated then, utilize high temperature to promote the suffered tensile stress of channel region of nmos pass transistor.
Then as shown in figure 16, utilize remaining stressor layers 322 and PMOS grid 310 to be used as mask and carry out an etch process, in the regions and source 317 of PMOS grid 310 tops and PMOS transistor area 304, respectively to form a groove 324.
As shown in figure 17, carry out some impurities that a cleaning removes groove 324 remained on surface then, and (selective epitaxial growth, SEG) technology is to form an epitaxial loayer 326 respectively in groove 324 to carry out a selective epitaxial growth.
As shown in figure 18, then remove resilient coating 320 and the stressor layers 322 that is positioned at nmos pass transistor district 302.Subsequently, can in part semiconductor substrate 300, form a metal silicide barrier layer (salicideblock, SAB) (figure do not show), and on nmos pass transistor 332 that unsilicided metal barrier hid and PMOS transistor 334, form a metal silicide layer 315, as shown in figure 19.According to one embodiment of the invention, the metal silicide barrier layer can be made of previous described resilient coating and stressor layers.
As before described, the making of metal silicide layer 315 can cover earlier one by the metal levels that material constituted such as nickel, cobalt, titanium, molybdenum (figure do not show) on nmos pass transistor and PMOS transistor, carry out annealing (the rapid thermal anneal that is rapidly heated then, RTA) technology, make metal level become metal silicide layer 315, finish and aim at metal silicide technology (salicide) voluntarily with the partial reaction that NMOS grid 308, PMOS grid 310 and regions and source 316 contact with 317.At last, as shown in figure 20, can deposit another stressor layers again on nmos pass transistor 332 and PMOS transistor 334 at product demand and be used as and contact hole etching stopping layer (CESL) 328, this all belongs to the scope that the present invention is contained.
In sum, the present invention discloses the transistorized method of a kind of making strained-silicon cmos (strained-silicon CMOS), its mainly be utilize stressor layers and epitaxial loayer simultaneously should be used for promoting nmos pass transistor and the transistorized overall efficiency of PMOS.As described in previous embodiment, the present invention can cover one earlier and have the covering layer of stress on nmos pass transistor and PMOS transistor, remove the stressor layers on the PMOS transistor then, then in the transistorized regions and source of PMOS, form groove and insert epitaxial loayer, utilize epitaxial loayer to promote the transistorized hole mobility of PMOS when making stressor layers promote the nmos pass transistor electron mobility by tensile stress.In addition, the present invention can remove the clearance wall that is positioned on each grid structure earlier again before forming covering layer.This practice can make the stressor layers on the follow-up covering transistor and insert the more approaching transistorized channel region of epitaxial loayer of substrate, and then promotes transistorized electronics and hole mobility.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (32)
1. method of making strained-silicon cmos transistors, this method comprises the following steps:
The semiconductor-based end is provided, and this semiconductor-based end, has first active region and is located between this first active region and this second active region in order to preparation transistor seconds and insulation system in order to preparation the first transistor, at least one second active region;
Form at least one first grid structure on this first active region with at least one second grid structure on this second active region;
Form first clearance wall respectively in this first grid structure and this second grid structure periphery;
Form the source electrode and the drain region of source electrode and drain region and this transistor seconds of this first transistor respectively;
Remove the two first clearance wall on every side of this first grid structure and this second grid structure;
Cover covering layer in this first transistor and this transistor seconds surface;
Remove this covering layer on this transistor seconds surface;
Carry out etch process, on this second grid structure and, respectively to form groove at the semiconductor-based end on every side;
Carry out selective epitaxial growth process, with in respectively forming epitaxial loayer respectively in this groove; And
Remove this covering layer on this first transistor surface.
2. the method for claim 1, wherein this first grid structure also comprises:
The first grid dielectric layer; And
First grid is located on this first grid dielectric layer.
3. the method for claim 1, wherein this second grid structure also comprises:
The second grid dielectric layer; And
Second grid is located on this second grid dielectric layer.
4. the method for claim 1, wherein this first transistor comprises N type metal oxide semiconductor transistor, and this transistor seconds comprises the P-type mos transistor.
5. the method for claim 1, wherein this covering layer is the silica covering layer.
6. the method for claim 1, wherein this covering layer is a stressor layers.
7. method as claimed in claim 6, wherein this stressor layers is the silicon nitride stressor layers.
8. method as claimed in claim 6, wherein this stressor layers is high tensile stress film.
9. the method for claim 1, wherein this method also comprises behind this covering layer of removing this first transistor surface:
Form second clearance wall respectively in this first grid structure and this second grid structure periphery;
Cover metal level in this first transistor and this transistor seconds surface;
The annealing process that is rapidly heated is to form metal silicide layer on this first transistor and this transistor seconds; And
Remove unreacted this metal level.
10. method as claimed in claim 9, wherein this method comprises also that after forming this metal silicide layer formation contact hole etching stopping layer is on this first transistor and this transistor seconds.
11. the method for claim 1, wherein this epitaxial loayer comprises SiGe.
12. a method of making strained-silicon cmos transistors, this method comprises the following steps:
The semiconductor-based end is provided, and this semiconductor-based end, has first active region and is located between this first active region and this second active region in order to preparation transistor seconds and insulation system in order to preparation the first transistor, at least one second active region;
Form at least one first grid structure on this first active region with at least one second grid structure on this second active region;
Form clearance wall respectively in this first grid structure and this second grid structure periphery;
Form the source electrode and the drain region of source electrode and drain region and this transistor seconds of this first transistor respectively;
Cover resilient coating and stressor layers in regular turn in this first transistor and this transistor seconds surface;
Remove this resilient coating and this stressor layers on this transistor seconds surface;
Carry out etch process, on this second grid structure and, respectively to form groove at the semiconductor-based end on every side;
Carry out selective epitaxial growth process, with in respectively forming epitaxial loayer respectively in this groove; And
Remove this resilient coating and this stressor layers on this first transistor surface.
13. method as claimed in claim 12, wherein this first grid structure also comprises:
The first grid dielectric layer; And
First grid is located on this first grid dielectric layer.
14. method as claimed in claim 12, wherein this second grid structure also comprises:
The second grid dielectric layer; And
Second grid is located on this second grid dielectric layer.
15. method as claimed in claim 12, wherein this first transistor comprises N type metal oxide semiconductor transistor, and this transistor seconds comprises the P-type mos transistor.
16. method as claimed in claim 12, wherein this resilient coating is the silica resilient coating.
17. method as claimed in claim 12, wherein this stressor layers is the silicon nitride stressor layers.
18. method as claimed in claim 12, wherein this stressor layers is high tensile stress film.
19. method as claimed in claim 12, wherein this method also comprises behind this covering layer of removing this first transistor surface:
Cover metal level in this first transistor and this transistor seconds surface;
The annealing process that is rapidly heated is to form metal silicide layer on this first transistor and this transistor seconds; And
Remove unreacted this metal level.
20. method as claimed in claim 19, wherein this method comprises also that after forming this metal silicide layer formation contact hole etching stopping layer is on this first transistor and this transistor seconds.
21. method as claimed in claim 12, wherein this epitaxial loayer comprises SiGe.
22. a method of making strained-silicon cmos transistors, this method comprises the following steps:
The semiconductor-based end is provided, and this semiconductor-based end, has first active region and is located between this first active region and this second active region in order to preparation transistor seconds and insulation system in order to preparation the first transistor, at least one second active region;
Form at least one first grid structure on this first active region with at least one second grid structure on this second active region;
Form the source electrode and the drain region of source electrode and drain region and this transistor seconds of this first transistor respectively;
Cover covering layer in this first transistor and this transistor seconds surface;
Remove this covering layer on this transistor seconds surface;
Carry out etch process, on this second grid structure and, respectively to form groove at the semiconductor-based end on every side;
Carry out selective epitaxial growth process, with in respectively forming epitaxial loayer respectively in this groove; And
Remove this covering layer on this first transistor surface.
23. method as claimed in claim 22, wherein this first grid structure also comprises:
The first grid dielectric layer; And
First grid is located on this first grid dielectric layer.
24. method as claimed in claim 22, wherein this second grid structure also comprises:
The second grid dielectric layer; And
Second grid is located on this second grid dielectric layer.
25. method as claimed in claim 22, wherein this first transistor comprises N type metal oxide semiconductor transistor, and this transistor seconds comprises the P-type mos transistor.
26. method as claimed in claim 22, wherein this covering layer is the silica covering layer.
27. method as claimed in claim 22, wherein this covering layer is a stressor layers.
28. method as claimed in claim 27, wherein this stressor layers is the silicon nitride stressor layers.
29. method as claimed in claim 27, wherein this stressor layers is high tensile stress film.
30. method as claimed in claim 22, wherein this method also comprises behind this covering layer of removing this first transistor surface:
Form clearance wall respectively in this first grid structure and this second grid structure periphery;
Cover metal level in this first transistor and this transistor seconds surface;
The annealing process that is rapidly heated is to form metal silicide layer on this first transistor and this transistor seconds; And
Remove unreacted this metal level.
31. method as claimed in claim 30, wherein this method comprises also that after forming this metal silicide layer formation contact hole etching stopping layer is on this first transistor and this transistor seconds.
32. method as claimed in claim 22, wherein this epitaxial loayer comprises SiGe.
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| CN102097381B (en) * | 2009-12-14 | 2013-04-17 | 中芯国际集成电路制造(上海)有限公司 | CMOS (Complementary Metal-Oxide-Semiconductor) transistor and stress memory treatment method thereof |
| CN102129995B (en) * | 2010-01-12 | 2012-12-05 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal silicide contact layer and field effect transistor |
| CN102646636A (en) * | 2011-02-21 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing N-channel metal oxide semiconductor (NMOS) semiconductor device |
| CN102915968A (en) * | 2011-08-01 | 2013-02-06 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of CMOS (Complementary Metal oxide Semiconductor) transistor |
| CN102938415B (en) * | 2011-08-16 | 2015-07-08 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
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| US9093303B2 (en) * | 2012-07-19 | 2015-07-28 | Texas Instruments Incorported | Spacer shaper formation with conformal dielectric film for void free PMD gap fill |
| CN103681506B (en) * | 2012-09-20 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of a kind of semiconducter device |
| CN106356299B (en) * | 2015-07-13 | 2021-04-13 | 联华电子股份有限公司 | Semiconductor structure with self-aligned spacer and manufacturing method thereof |
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| US20050082522A1 (en) * | 2003-07-25 | 2005-04-21 | Yi-Chun Huang | Strained channel transistor formation |
| US20050215024A1 (en) * | 2004-03-26 | 2005-09-29 | Jeong-Yeop Nahm | Methods for forming super-steep diffusion region profiles in MOS devices and resulting semiconductor topographies |
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| US20050006637A1 (en) * | 2003-07-11 | 2005-01-13 | Toshihiko Iinuma | Semiconductor device and method of manufacturing the same |
| US20050082522A1 (en) * | 2003-07-25 | 2005-04-21 | Yi-Chun Huang | Strained channel transistor formation |
| US20050051851A1 (en) * | 2003-09-10 | 2005-03-10 | International Business Machines Corporation | Structure and method of making strained channel cmos transistors having lattice-mismatched epitaxial extension and source and drain regions |
| US20050215024A1 (en) * | 2004-03-26 | 2005-09-29 | Jeong-Yeop Nahm | Methods for forming super-steep diffusion region profiles in MOS devices and resulting semiconductor topographies |
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