CN100407281C - Grid driving method and circuit of liquid crystal displaying device - Google Patents

Grid driving method and circuit of liquid crystal displaying device Download PDF

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CN100407281C
CN100407281C CN2005100059631A CN200510005963A CN100407281C CN 100407281 C CN100407281 C CN 100407281C CN 2005100059631 A CN2005100059631 A CN 2005100059631A CN 200510005963 A CN200510005963 A CN 200510005963A CN 100407281 C CN100407281 C CN 100407281C
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gate drive
drive signal
signal
voltage square
wave
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CN1645465A (en
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许文法
易建宇
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AU Optronics Corp
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AU Optronics Corp
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Abstract

The present invention relates to a grid electrode drive method and a circuit for a liquid crystal display. The liquid crystal display is provided with a plurality of scan lines. The method comprises that a grid electrode drive signal is generated; a correcting signal with the opposite polarity to the grid electrode drive signal is superposed to the grid electrode drive signal, and a grid electrode drive correcting signal is generated to reduce the electrical level of the high potential of the grid electrode drive signal; the grid electrode drive correcting signal is output to drive one of the corresponding scan lines.

Description

The grid drive method of LCD and circuit
Technical field
The present invention relates to improving one's methods of a kind of LCD, and be particularly related to a kind of method that reduces the LCD picture flicker and increase the duration of charging.
Background technology
LCD is in recent years more and more welcome, not only can save the space, and can reduce power consumption, gradually large scale, high-resolution LCD is used for replacing traditional display now, just as cathode-ray tube display (CRT display), yet have an important problem in large-sized LCD, that is exactly that the screen size of LCD is big more, and the flicker problem on the liquid crystal display equipment screen is serious more.
Fig. 1 is LCD (Liquid Crystal Display, LCD) basic structure, thin film transistor (TFT) (Thin FilmTransistor is responsible for opening and is closed to gate drivers (Gate driver) 102, TFT), source electrode driver (Source driver) 101 then responsible output datas are given liquid crystal electric capacity, make the voltage on the liquid crystal capacitance can arrive the level that this has in the time that thin film transistor (TFT) is opened.
Traditionally, gate drivers IC on the LCD (Gate driver IC) 102a output enabling signal is opened thin film transistor (TFT) successively, source electrode driver IC (Source driverIC) 101a is sent into data in the liquid crystal capacitance, yet because the relation of the born characteristic of LCD makes picture produce flicker (flicker) phenomenon easily.
As shown in Figure 2, Fig. 2 is the synoptic diagram of display panels lining pixel (subpixel).Generally speaking, each LCD sub-pixel is by an on-off element (for example transistor T FT) and be connected the drain electrode of transistor T FT (Drain, D) the liquid crystal capacitance CLC on constitutes with keeping capacitor C st.A plurality of aforementioned sub-pixels constitute the array of an enrank shape, at the sub-pixel of same row transistor gate (Gate with each sub-pixel, G) be connected to sweep trace, then (Source S) is connected to data line with the transistor source of each sub-pixel with the sub-pixel of delegation.As shown in Figure 2, when Gn bar sweep trace is chosen to, i.e. the output of gate drivers IC on LCD enabling signal is given Gn bar sweep trace, that is arrives the grid G of transistor T FT; Then data signal waveforms is sent to the data line of Sn bar.This moment, transistor T FT just was opened, and data are sent to drain D via transistor T FT source S, and then to liquid crystal capacitance C LCCharge with keeping capacitor C st.According to liquid crystal capacitance C LCCross-pressure, sub-pixel can corresponding demonstrate the gray scale of this sub-pixel, to reach the effect of show image.Keep capacitor C st then can in this display cycle, keep liquid crystal capacitance C LCCross-pressure.
Enabling signal waveform in output shown in Figure 2 is a square wave, because the panel semiconductor technology has stray capacitance and resistance and produces, and then produces RC delay (RCdelay) on its sweep trace, causes waveform distortion.As Fig. 3 A is the startup waveform signal of the gate drivers IC output on the LCD, wherein V GH, V GLBe respectively the highest and minimum level of enabling signal waveform, Δ V GHPoor for maximum level and minimum level, Fig. 3 B is for being subjected to the waveform after stray resistance on the sweep trace, the capacitive effect through one section sweep trace, and Fig. 3 C then is the latter half of waveform of sweep trace, wherein V 1Be the maximum level after the waveform distortion, Δ V 1Poor for maximum level after the wave mode distortion and minimum level, can know thus and find out that the enabling signal waveform is because of being subjected to the influence that RC postpones on the sweep trace, different with original waveform and the situation big more distortion of panel size of waveform to the end will be serious more, so get over the startup waveform signal of rear end on the sweep trace, need the flower more time just can reach level more and (be V GH, C GL).
In addition, in order to ensure when Gn+1 bar sweep trace starts, thin film transistor (TFT)s all on the Gn bar sweep trace have cut out, gate drivers IC on the general LCD technically can be by output grid output enable (Gate Output Enable, GOE) signal guarantees that two adjacent sweep traces can not start simultaneously up and down, its sequential relationship as shown in Figure 4, originally the time of a sweep trace charging is t 4, the size of a clock pulse just, but because added grid output enable signal, the time has been shortened the length of Δ t, so the duration of charging of sweep trace reality is t 5, if panel resolution is high more, the time t in clock pulse cycle 4Also just relatively can be more little, panel size is big more again, and sweep trace relatively also can be elongated, and the situation that RC postpones also can become more serious, and Δ t just must become greatly, starts simultaneously to avoid adjacent scanning lines.
Because the LCD size is increasing at present, the trend that resolution is also more and more higher is at the time t of charging 4Length shorten relatively, and Δ t must keep under a certain size the double influence, actual duration of charging t 5Length become shorter, make the duration of charging not enough more, so this will produce very important influence to LCD on the target of large scale and high-resolution.
Shortcoming on another of LCD drives then is to produce feed-trough voltage (V Feedthrough) effect, shown in it is defined as follows:
V feedthrough = C GD C GD + C LC + C st ΔV , ΔV=(V-V GL)........(1)
C wherein GDBe the stray capacitance between thin film transistor (TFT) (TFT) grid and the drain electrode, C LCBe liquid crystal capacitance, Cst is for keeping electric capacity, the pressure reduction when Δ V finishes for the enabling signal waveform.
As shown in Figure 5, Fig. 5 is for just scheming and a negative figure synoptic diagram, when the voltage on the liquid crystal capacitance in the time that thin film transistor (TFT) is opened, be charged to required level, but signal by the time because the stray capacitance (C between film crystal tube grid and the drain electrode GD) cause, the Δ V so voltage can descend than level originally again a, cause liquid crystal capacitance (C LC) when positive and negative figure field to common voltage V ComBetween the pressure reduction difference, and this can allow picture produce flicker (flicker) phenomenon.General solution is by adjusting common voltage V at present Com, make liquid crystal capacitance identical when the positive and negative figure field to the pressure reduction between the common voltage, as shown in phantom in Figure 5, for adjusting the common voltage V ' of back ComValue, the situation that does not so just have film flicker takes place.
Said circumstances is an ideal case, if the feed-trough voltage effect of each liquid crystal sub-pixel is all the same, and then undoubtedly can be by adjusting common voltage V ComEffectively solve the phenomenon that occurs flicker on the LCD.But, then can cause the feed-trough voltage effect of each liquid crystal sub-pixel different, to such an extent as to effect is limited in fact because of other factors such as technologies.Shown in Fig. 3 A, 3B, 3C and formula (1), the pressure differential deltap V when the enabling signal waveform of same sweep trace front-end and back-end finishes is different, wherein the maximum level V after the waveform distortion 1Maximum level V less than the enabling signal waveform GH, i.e. the difference Δ V of the maximum level of sweep trace rear end enabling signal and minimum level 1Less than the maximum level of sweep trace frontal startup signal and the difference Δ V of minimum level GH, the feed-trough voltage V that causes the sweep trace front end to be produced FeedthroughThe feed-trough voltage V that is produced with the rear end FeedthroughUnequal, at this moment adjust common voltage V ComCan't make that also voltage is to common voltage V on same the sweep trace rear and front end liquid crystal capacitance ComBetween pressure reduction identical, to such an extent as to can't effectively solve the problem of film flicker.
Be different from the second way of above-mentioned solution film flicker, in order to reduce the feed-trough voltage effect, can utilize a kind of waveform of top rake function, as shown in Figure 6A, the pressure differential deltap V when making that by this function the enabling signal waveform finishes is by the difference Δ V of maximum level and minimum level GHBecome the difference Δ V ' of new maximum level and minimum level GHBecause the pressure differential deltap V when the enabling signal waveform finishes diminishes, so the feed-trough voltage effect also and then diminishes, but this method still can't change sweep trace RC postpone cause waveform distortion and the influence that brings, shown in Fig. 6 B, because the cause that RC postpones, the waveform of sweep trace rear end can rise slowly, cause the voltage level when starting the top rake function just different, that is to say maximum level V GHCan be greater than the maximum level V after the waveform distortion 2, so the level behind the top rake is also just different, the difference Δ V ' of promptly new maximum level and minimum level GHCan be greater than the difference Δ V ' of maximum level new after the waveform distortion and minimum level 2So by Fig. 6 A, 6B as can be known, though the feed-trough voltage effect reduces, the sweep trace rear and front end is to common voltage V ComPressure reduction still different, so still can't effectively solve the problem of film flicker.
From the above, LCD still has needs improved place, and one is the duration of charging that will increase liquid crystal capacitance, and another then is to reduce the influence that sweep trace is brought because of the RC effect, makes the feed-trough voltage V of front and back end FeedthroughApproaching as far as possible.
Summary of the invention
Purpose of the present invention is exactly at driving method that a kind of LCD is provided and circuit, and it can drop to the difference of the feed-trough voltage of same sweep trace front end and rear end minimum, to reduce the flicker of picture.
Another object of the present invention provides a kind of driving method and circuit of LCD, and it can increase the duration of charging of liquid crystal capacitance.
In order to reach above-mentioned purpose, the present invention proposes a kind of grid drive method of LCD, and this LCD has the multi-strip scanning line.This grid drive method comprises: produce gate drive signal, described gate drive signal is the positive voltage square wave; The corrected signal that polarity is opposite with gate drive signal is superimposed to the negative edge front side near gate drive signal, produces to revise gate drive signal, and to reduce the noble potential level of gate drive signal, described corrected signal is the negative voltage square wave; And export and revise gate drive signal, and remove to drive one of these corresponding sweep traces to revise gate drive signal.
According to an enforcement kenel of the present invention, the present invention also proposes a kind of grid drive method of LCD, and this LCD has the multi-strip scanning line.This grid drive method comprises: produce gate drive signal, described gate drive signal is the positive voltage square wave; Carry out the top rake action near the negative edge front side of gate drive signal, to reduce the noble potential level of gate drive signal; After the top rake release, at once that polarity is opposite with gate drive signal corrected signal is superimposed to the gate drive signal of top rake, produce and revise gate drive signal, to reduce the noble potential level of gate drive signal once more, corrected signal can be the negative voltage square wave; And export and revise gate drive signal, and remove to drive one of these corresponding sweep traces to revise gate drive signal.
According to an enforcement kenel of the present invention, the present invention proposes a kind of method that produces the gate drive signal of LCD, uses so that above-mentioned gate drive signal removes to drive the sweep trace of this LCD.The method comprises: produce the positive voltage square-wave signal, it has noble potential level and electronegative potential level; And first predetermined point of time before the negative edge of positive voltage square-wave signal, align voltage square wave signal stack negative voltage square-wave signal, to produce gate drive signal.
In preceding method, can also be included in the second preceding predetermined point of time of negative edge of positive voltage square-wave signal, align voltage square wave and carry out the top rake action, to reduce the noble potential level of gate drive signal, wherein first predetermined point of time is after this second ticket reserving time point.Preferably, stack negative voltage square-wave signal is to carry out at once after the top rake release.
According to an enforcement kenel of the present invention, the present invention also proposes a kind of gate drivers, in order to produce the gate drive signal of the multi-strip scanning line that drives LCD.Gate drivers comprises: positive voltage square wave generation module in order to produce the positive voltage square-wave signal, has noble potential level and electronegative potential level; And negative voltage square wave generation unit, in order to produce the negative voltage square-wave signal; And superpositing unit, be coupled to the output of positive voltage square wave generation module and negative voltage square wave generation unit, and first predetermined point of time before the negative edge of positive voltage square-wave signal is with negative voltage square-wave signal and the stack of positive voltage square-wave signal, to produce gate drive signal.
In aforementioned gate drivers, can also comprise a top rake processing unit, it can be coupled to positive voltage square wave generation module, and second predetermined point of time before the negative edge of positive voltage square-wave signal, align voltage square wave and carry out the top rake action, to reduce the noble potential level of gate drive signal, wherein first predetermined point of time is after second predetermined point of time.
According to method and the structure that the present invention proposes, before the gate drive signal of positive voltage square wave offers each sweep trace, just earlier go to revise with a negative voltage square-wave signal.Revised gate drive signal just offers sweep trace.Because the negative voltage square-wave signal also can be subjected to the stray capacitance on the sweep trace and the influence of stray resistance, so on the whole piece sweep trace from the front position to the back-end location, the high-low level pressure drop of gate drive signal negative edge just can reach unanimity.Related feed-trough voltage V FeedthroughAlso level off to equally,, can increase simultaneously the duration of charging of liquid crystal capacitance again so can improve the flicker problem of picture effectively.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and in conjunction with the accompanying drawings, be described in detail below.
Description of drawings
Fig. 1 is the basic block diagram of LCD;
Fig. 2 is a display panels lining pixel synoptic diagram;
Fig. 3 A is the startup waveform signal of the gate drivers IC output on the LCD;
Fig. 3 B is through one section sweep trace, is subjected to the waveform after stray resistance on the sweep trace, the capacitive effect;
Fig. 3 C is the latter half of waveform of sweep trace;
Fig. 4 is a timing diagram;
Fig. 5 is for just scheming a field and a negative figure synoptic diagram;
Fig. 6 A is a kind of waveform with top rake function;
Fig. 6 B is the waveform of the latter half of top rake function of a kind of sweep trace;
Fig. 7 is the synoptic diagram of negative square wave, and the negative square wave synoptic diagram that is subjected to the RC delayed impact;
Fig. 8 is for adding the voltage synoptic diagram of negative square wave when the enabling signal waveform;
Fig. 9 is the waveform that adds negative voltage after the adding top rake function again;
Figure 10 illustrates gate drive signal of the present invention and produces and the sequential chart of exporting.
Embodiment
Technical characterictic of the present invention is to be to make on same the sweep trace, makes the difference of the feed-trough voltage on each transistor reach minimum, to reduce the film flicker phenomenon.The present invention supposes the C in the formula (1) GD/ (C GD+ C LC+ C St) be definite value, focus on the part of adjusting Δ V, the pressure reduction when promptly adjusting the end of enabling signal waveform.
Because the positive voltage square-wave signal (gate drive signal) of input can produce above-mentioned known problem, so the negative voltage square-wave signal also can be subjected to identical effect through stray capacitance, resistance on the sweep trace.Therefore, in the positive voltage square-wave signal that is added to a negative voltage square-wave signal (corrected signal), produce the gate drive signal of a correction, the difference of the sweep trace front and back end pressure drop that produces when having only the positive voltage square-wave signal to be transfused to so originally can make the front and back end pressure drop reduced because of the existence of negative voltage square-wave signal.Describe the effect that adds this negative voltage square-wave signal with that in detail.
As shown in Figure 7, Fig. 7 supposes wherein that for the synoptic diagram of negative square wave equivalent stray resistance and the equivalent stray capacitance on the whole piece sweep trace is R EqualAnd C Equal, by can learning among the figure, this voltage via RC delayed impact on the sweep trace after, the waveform in the sweep trace rear end can become shown in Fig. 7 right side.When this negative voltage square-wave signal puts on liquid crystal capacitance on the sweep trace, voltage on the liquid crystal capacitance is descended, and because the RC effect on the sweep trace, can cause this negative voltage square-wave signal, voltage swing in sweep trace front end and rear end is inequality, i.e. the minimum level of negative voltage square-wave signal | V A| (front end) is greater than the minimum level after the waveform distortion | V B| (rear end).Therefore, when this negative voltage square-wave signal is superimposed on liquid crystal capacitance on the sweep trace, in the voltage fall of sweep trace rear end than next little of preceding terminal voltage fall, so more approaching in the voltage drop meeting of sweep trace rear and front end.
Fig. 8 shows the correction voltage waveform after the positive voltage square-wave signal adds the negative voltage square-wave signal.Shown in Fig. 8 left side, it shows sweep trace part foremost, and starting the time point that adds the negative voltage square-wave signal is to begin to become low level (V when the positive voltage square wave by maximum level GL, 0V for example) and preceding time point.Δ V among the figure " GHPoor for the maximum level that adds the negative voltage square-wave signal and minimum level.That is, when the negative voltage square-wave signal that applies as shown in Figure 7, the maximum level V of the positive voltage square-wave signal that applies originally GHCan by the negative value of negative voltage square-wave signal (for example Fig. 7-V A), toward being pulled down to V " GHAt this moment, the Δ V in the aforementioned formula (1) is just by V GH-V GLBecome V " GH-V GL=Δ V " GHIn other words, Δ V has reduced V GH-V " GH
Secondly, with reference to the right figure of figure 8, it demonstrates the rear end at same sweep trace.The time point that start to add the negative voltage square-wave signal remains when the positive voltage square wave and begins to become low level (V by maximum level GL, 0V for example) and preceding time point.Δ V ' among the figure 3Add the poor of maximum level behind the negative voltage square-wave signal and minimum level during for the wave mode distortion.As shown in Figure 8, when the negative voltage square-wave signal that applies as shown in Figure 7, apply the maximum level V of positive voltage square-wave signal originally in the sweep trace rear end 3Can by the negative value of negative voltage square-wave signal (for example Fig. 7-V B), toward being pulled down to V ' 3At this moment, the Δ V in the aforementioned formula (1) is just by V 3-V GLBecome V ' 3-V GL=Δ V ' 3In other words, Δ V has reduced V 3-V ' 3
Comparison diagram about 8 two figure, the negative voltage square-wave signal also can be because of the influence of stray capacitance on the sweep trace and resistance, cause in the voltage drop value of sweep trace front end and rear end also inequality, and because the negative voltage square-wave signal is opposite with the polarity of positive voltage square-wave signal, thus at the sweep trace front end voltage V GHThe amount of leaving behind and in the sweep trace rear end voltage V 3The amount of leaving behind is inequality.Therefore, two ends amount of pressure drop V GH-V " GHWith V 3-V ' 3Also different, but because the V of sweep trace front end GHV greater than the rear end 3So sweep trace front end and rear end Δ V are almost approaching.That is Δ V (front end)=Δ V, " GH=V " GH-V GL≈ Δ V ' 3=V ' 3-V GL=Δ V (rear end).
In other words, when the trigger voltage waveform is square-wave signal, after the square wave voltage signal that adding is born, add the maximum level of negative voltage square-wave signal and the difference Δ V of minimum level again " GH(sweep trace front end) can level off to the wave mode distortion and add the maximum level of negative voltage and the difference Δ V ' of minimum level 3(sweep trace rear end), its feed-trough voltage V FeedthroughThen level off to equal.At this moment adjust common voltage V ComJust can make the liquid crystal capacitance on the same sweep trace, its voltage is to common voltage V ComBetween pressure reduction identical when positive and negative figure field, so can reach the degree of the film flicker that reduces LCD.
The present invention might not limit the use of in the waveform that only adds negative voltage.Fig. 9 shows of the present invention another and implements kenel, and it is the embodiment that adds the top rake function at the positive voltage square wave of gate drive signal.In gate drive signal, align voltage square wave signal and add the mode that the top rake function is known solution flicker problem, but for the pressure reduction of common voltage bigger difference is arranged still at the liquid crystal capacitance of sweep trace front and back end, can't effectively solve the flicker problem.But, when after using the notion of negative voltage square-wave signal of the present invention, can make the feed-trough voltage of front and back end of sweep trace more approaching, further solve the problem of film flicker.
As shown in Figure 9, after it illustrates and adds the top rake function, add the waveform of negative voltage again, Fig. 9 represents on the left side front end waveform of sweep trace, and the rear end waveform is represented on the right.At first see the part of front end waveform, at first to the drive signal of gate drivers output, promptly the positive voltage square-wave signal carries out top rake, makes high level originally from V GHReduce to V ' GHWhen the top rake effect finishes, apply the negative voltage square-wave signal, make high level from V ' GHReduce to V again " ' GHThat is, when the negative voltage square-wave signal that applies as shown in Figure 7, the maximum level V ' behind the sharping of the positive voltage square wave that applies originally GHCan by the negative value of negative voltage square-wave signal (for example Fig. 7-V A), toward being pulled down to V " ' GHAt this moment, the Δ V in the aforementioned formula (1) is just by V ' GH-V GLBecome V " ' GH-V GL=Δ V " ' GHIn other words, Δ V has reduced Δ V 4=V ' GH-V " ' GH
Secondly, with reference to the right figure of figure 9, it demonstrates the rear end at same sweep trace.The time point of startup adding negative voltage square-wave signal still is the time point when the positive voltage square wave is finished by sharping by maximum level.Δ V among the figure " 5Add the poor of maximum level behind the negative voltage square-wave signal and minimum level during for the wave mode distortion.As shown in Figure 9, when the negative voltage square-wave signal that applies as shown in Figure 7, the maximum level V ' after the sweep trace rear end applies the sharping of positive voltage square wave originally 5Can by the negative value of negative voltage square-wave signal (for example Fig. 7-V B), toward being pulled down to V " 5At this moment, the Δ V in the aforementioned formula (1) is just by V ' 5-V GLBecome V " 5-V GL=Δ V " 5In other words, Δ V has reduced Δ V 5=V ' 5-V " 5
Comparison diagram about 9 two figure, the negative voltage square-wave signal also can be because of the influence of stray capacitance on the sweep trace and resistance, cause in the voltage drop value of sweep trace front end and rear end also inequality, and because the negative voltage square-wave signal is opposite with the polarity of positive voltage square-wave signal, thus at the sweep trace front end the voltage V ' of sharping GHThe amount of leaving behind and in the sweep trace rear end the voltage V ' of sharping 5The amount of leaving behind is inequality.Therefore, two ends amount of pressure drop Δ V 4With Δ V 5Also different, but because the V ' of sweep trace front end GHV ' greater than the rear end 5So sweep trace front end and rear end Δ V are almost approaching.That is Δ V (front end)=Δ V, " ' GH=V " ' GH-V GL≈ Δ V " 5=V " 5-V GL=Δ V (rear end).
In other words, when the trigger voltage waveform is square-wave signal, after starting sharping and adding negative square-wave voltage again, add the maximum level of negative voltage and the difference Δ V of minimum level " ' GH(sweep trace front end) can level off to the wave mode distortion and add the maximum level of negative voltage and the difference Δ V of minimum level " 5(sweep trace rear end), its feed-trough voltage V FeedthroughThen level off to equal.At this moment adjust common voltage V ComJust can make the liquid crystal capacitance on the same sweep trace, its voltage is to common voltage V ComBetween pressure reduction identical when positive and negative figure field, so can reach the film flicker degree that reduces LCD.
Through above-mentioned explanation, after the gate drive signal (enabling signal waveform) that gate drivers is exported applies the negative voltage square-wave signal, no matter be to have the no-trump gate drive signal to carry out the step of top rakeization, the pressure drop Δ V in the front and back end of sweep trace reaches unanimity at last.Also because feed-trough voltage V FeedthroughPressure differential deltap V when finishing with the enabling signal waveform becomes to put in order ratio, so the feed-trough voltage V of the front and back end of sweep trace FeedthroughAlso almost equal.Therefore, the problem of film flicker can solve effectively.
Aforesaid mode can be utilized at gate drivers adding negative voltage squarer and implement, and when the top rake function is arranged, can increase the circuit relevant with the top rake function.For example in originally known gate drivers, add circuit that produces aforementioned negative voltage square-wave signal and the circuit that produces aforementioned top rake effect.In addition, also can more comprise supercircuit, with aforesaid generating positive and negative voltage square-wave signal stack, to produce the gate drive signal of revising.
The shortcoming of another LCD then is the deficiency in duration of charging, and the present invention equally also can reach the effect of solution.Simple declaration the present invention reaches the mode that increases the duration of charging with that.
Figure 10 illustrates gate drive signal of the present invention and produces and the sequential chart of exporting.As shown in figure 10, Figure 10 is comprehensive aforementioned all waveform signals diagram, and wherein GCK is a gate drivers IC clock pulse waveform, X nFor starting the signal of top rake function, Y nFor starting the signal of negative voltage waveform.As shown in figure 10, after the time T 10 of clock pulse GCK, gate drivers can be at for example n bar sweep trace G nThe output gate drive signal, the maximum level of signal is V GHAfterwards, when time T 11, according to the pulse wave rising edge of the signal Xn that starts the top rake function, beginning that gate drive signal is carried out top rake and handle, with fixing slope, is V with maximum level GHPulling down to level is V ' GHThen, at time point T12, this is the pulse wave negative edge of the signal Xn of top rake function, the top rake function finishes at this moment, and the signal Yn that starts the negative voltage square wave occurs simultaneously, then 12 couples of time point T the waveform of top rake add the negative voltage square wave, make level from V ' GHPulling down to level again is V " ' GHSo at the time point of T20, pressure reduction is V " ' GH-V GLIn time T 20, grid output enable signal GOE output after signal GOE finishes, just repeats above-mentioned action, drives next bar sweep trace G N+1Output.
By aforesaid way, this negative voltage square wave is controlled at startup top rake function signal X nStart in the time of will finishing, and behind the grid output enable GOE signal enabling, this negative square-wave voltage still continues action.Thus, then the voltage level of the thin film transistor (TFT) on sweep trace will be from the maximum level V of enabling signal waveform GHGet back to the minimum level V of enabling signal waveform GLThe time, because the minimum level V of enabling signal waveform GLAlso be a negative value, direction of current is identical with this negative voltage square wave, so this negative voltage square wave will be accelerated the speed of electric current, makes its voltage level get back to the minimum level V of enabling signal waveform quickly GL, reduce the delay phenomenon that is produced because of the RC delay.Therefore, start simultaneously for fear of two adjacent sweep traces before, and the grid output enable GOE signal that adds, therefore the length of its signal just can shorten.Thus, the time of the liquid crystal capacitance of LCD charging has just increased, so the present invention also can solve the problem of duration of charging deficiency on the LCD.
In sum, at the present invention's the negative square-wave voltage that utilizes, can reduce the duration of charging of the film flicker and the increase liquid crystal capacitance of LCD.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any this area ground technician; without departing from the spirit and scope of the present invention; should do a little change and modification, so protection scope of the present invention defines and is as the criterion when looking the accompanying Claim book.

Claims (7)

1. the grid drive method of a LCD, this LCD has the multi-strip scanning line, and the grid drive method of this LCD comprises:
Produce a gate drive signal, described gate drive signal is a positive voltage square wave;
The corrected signal that polarity is opposite with this gate drive signal is added near the negative edge front side of this gate drive signal, produce one and revise gate drive signal, to reduce the noble potential level of this gate drive signal, described corrected signal is a negative voltage square wave; And
Export this correction gate drive signal, and revise one of these corresponding sweep traces of gate drive signal driving with this.
2. the grid drive method of a LCD, described LCD has the multi-strip scanning line, and the grid drive method of described LCD comprises:
Produce a gate drive signal, described gate drive signal is a positive voltage square wave;
Carry out top rake action near the negative edge front side of this gate drive signal, to reduce the noble potential level of this gate drive signal;
After this top rake release, at once that polarity is opposite with this a gate drive signal corrected signal is superimposed to this gate drive signal of top rake, produce one and revise gate drive signal, to reduce the noble potential level of this gate drive signal once more, described corrected signal is a negative voltage square wave; And
Export this correction gate drive signal, and revise one of these corresponding sweep traces of gate drive signal driving with this.
3. a method that produces the gate drive signal of LCD is used so that this gate drive signal removes to drive the sweep trace of this LCD, and the method for the gate drive signal of this generation LCD comprises:
Produce a positive voltage square-wave signal, it has a noble potential level and an electronegative potential level; And
First predetermined point of time before the negative edge of this positive voltage square-wave signal is to this positive voltage square-wave signal negative voltage square-wave signal that superposes, to produce this gate drive signal.
4. the method for the gate drive signal of generation LCD as claimed in claim 3, also be included in the second preceding predetermined point of time of negative edge of described positive voltage square-wave signal, described positive voltage square wave is carried out top rake action, to reduce the noble potential level of described gate drive signal, wherein said first predetermined point of time is after described second predetermined point of time.
5. the method for the gate drive signal of generation LCD as claimed in claim 4, the described negative voltage square-wave signal that wherein superposes is to carry out at once after described top rake release.
6. gate drivers, in order to produce the gate drive signal of the multi-strip scanning line that drives LCD, this gate drivers comprises:
One positive voltage square wave generation module in order to produce a positive voltage square-wave signal, has a noble potential level and an electronegative potential level; And
One negative voltage square wave generation unit is in order to produce a negative voltage square-wave signal; And
One superpositing unit, be coupled to the output of this positive voltage square wave generation module and this negative voltage square wave generation unit, and first predetermined point of time before the negative edge of this positive voltage square-wave signal is with this negative voltage square-wave signal and the stack of this positive voltage square-wave signal, to produce this gate drive signal.
7. gate drivers as claimed in claim 6 also comprises:
One top rake processing unit, be coupled to described positive voltage square wave generation module, second predetermined point of time before the negative edge of described positive voltage square-wave signal, described positive voltage square wave is carried out top rake action, to reduce the noble potential level of described gate drive signal, wherein said first predetermined point of time is after described second predetermined point of time.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101699552B (en) * 2009-11-16 2012-04-18 友达光电股份有限公司 Grid output control method and corresponding grid pulse modulator

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101533611B (en) * 2008-03-10 2014-03-12 群创光电股份有限公司 Liquid crystal display panel, liquid crystal display device and control method thereof
TW201209786A (en) 2010-08-27 2012-03-01 Chimei Innolux Corp Buffer and display system utilizing the same
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0651272A (en) * 1991-09-20 1994-02-25 Hosiden Corp Method for driving liquid crystal display
US5892494A (en) * 1994-12-26 1999-04-06 International Business Machines Corporation Correction of LCD drive voltage in dependence upon LCD switching element turn on time between polarity changes
CN1544975A (en) * 2003-11-18 2004-11-10 友达光电股份有限公司 Circuit and method for generating top rack wave of panel display

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0651272A (en) * 1991-09-20 1994-02-25 Hosiden Corp Method for driving liquid crystal display
US5892494A (en) * 1994-12-26 1999-04-06 International Business Machines Corporation Correction of LCD drive voltage in dependence upon LCD switching element turn on time between polarity changes
CN1544975A (en) * 2003-11-18 2004-11-10 友达光电股份有限公司 Circuit and method for generating top rack wave of panel display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101699552B (en) * 2009-11-16 2012-04-18 友达光电股份有限公司 Grid output control method and corresponding grid pulse modulator

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