CN100407033C - Liquid crystal display device, active component array substrate and testing method thereof - Google Patents
Liquid crystal display device, active component array substrate and testing method thereof Download PDFInfo
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- CN100407033C CN100407033C CN2006101388448A CN200610138844A CN100407033C CN 100407033 C CN100407033 C CN 100407033C CN 2006101388448 A CN2006101388448 A CN 2006101388448A CN 200610138844 A CN200610138844 A CN 200610138844A CN 100407033 C CN100407033 C CN 100407033C
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Abstract
The invention relates to an active element array substrate, which comprises: substrate, several scanning wires, several data lines, several independent share line pictures, and several pixels, wherein the scanning line, data line and share line picture are on the substrate, and the pixel array is above the substrate, while each pixel is connected to relative scanning line and data line; the share line picture is under each pixel; each pixel comprises several active elements and several pixel electrodes; each pixel electrode via different active elements is connected to relative scanning line and data line; the capacitor couple effects between pixel electrode and share line picture are different. And the invention also provides a relative testing method of said active element array substrate and a liquid crystal display with said active element array substrate.
Description
Technical field
The invention relates to a kind of detection method, and particularly can detect single pixel inside effectively, the detection method of the circuit defect between a plurality of pixel electrodes (short defects) relevant for a kind of.
Background technology
Existing market all develops towards height contrast (contrastratio), the counter-rotating of no GTG (gray scale inversion), high brightness (brightness), high color saturation (color saturation), rapid reaction (response) and wide viewing angle directions such as (viewing angle) for Thin Film Transistor-LCD (TFT-LCD).Common wide viewing angle technology comprises at present: stable twisted nematic liquid crystal (TN) adds view film (wide viewing film), copline suitching type (In-Plane Switching, IPS) LCD, a limit suitching type (Fringe Field Switching, FFS) LCD and multidomain vertical alignment type (Multi-doma in Vertical Alignment, MVA) LCD.With the multi-field vertical assigned LCD panel is example, it can pass through some alignment pattern (alignment patterning), as orientation protrusion (alignment protrusion) or slit (slit), so that the liquid crystal molecule in each pixel is multi-direction arrangement, and then obtain several different orientation fields (domain).For known multi-field vertical assigned LCD panel, because the orientation protrusion (alignment protrusions) or the slit (slits) that are formed on colored optical filtering substrates or the thin-film transistor array base-plate can be so that liquid crystal molecule be multi-direction arrangement, and obtain several different orientation fields (domains), so multi-field vertical assigned LCD panel can be reached the requirement of wide viewing angle.Yet when different visual angles was watched same image, the pattern colour saturation degree that the user saw can be different, and this is so-called colour cast (colorshift).
In order to improve aforesaid colour cast problem, many notions that single pixel region is divided into two kinds of different voltage regime just are suggested in succession, this notion mainly is to use two pixel electrodes that are electrically insulated each other in single pixel, and makes two pixel electrodes that are electrically insulated each other have different voltage by driving.Yet in the processing procedure of thin-film transistor array base-plate, two pixel electrodes in the single pixel probably can cause two pixel electrode short circuits and the pixel display abnormality because of indium tin oxide residual (ITO residue) after being patterned.
Summary of the invention
The purpose of this invention is to provide a kind of active component array base board, it has a plurality of common lines patterns independent of each other, in order to testing.
Another object of the present invention provides a kind of method of testing, and it can detect the circuit defect between each pixel electrode on the active component array base board effectively.
Another purpose of the present invention provides a kind of LCD, and it has higher manufacturing yields (yield rate).
For reaching above-mentioned or other purpose, the present invention proposes a kind of active component array base board, and it comprises substrate, multi-strip scanning line, many data lines, a plurality of common lines patterns independent of each other and a plurality of pixels.Sweep trace, data line and shared line pattern are disposed on the substrate, and pel array is arranged on the substrate, and wherein each pixel and corresponding scanning line and data line electrically connect, and the common lines pattern distribution is in each pixel below.In addition, each pixel comprises a plurality of active members and a plurality of pixel electrode.By different active members and corresponding scanning line and data line electric connection, wherein each pixel electrode is different with the capacitance coupling effect between each common lines pattern respectively for each pixel electrode.
In one embodiment of this invention, above-mentioned common lines pattern comprises the first common lines pattern and the second common lines pattern, and wherein the first common lines pattern and the second common lines pattern distribution are in each pixel electrode below.
In one embodiment of this invention, above-mentioned active member comprises the first film transistor and second thin film transistor (TFT), and pixel electrode comprises first pixel electrode that electrically connects with the first film transistor and second pixel electrode that electrically connects with second thin film transistor (TFT).
In one embodiment of this invention, the above-mentioned transistorized channel width/length of the first film ratio is W
1/ L
1, and the channel width/length ratio of second thin film transistor (TFT) is W
2/ L
2, and W
1/ L
1≠ W
2/ L
2In a preferred embodiment of the present invention, (W
1/ L
1)/(W
2/ L
2) 〉=2.
In one embodiment of this invention, each above-mentioned pixel also comprises a plurality of capacitance electrodes that are disposed between common lines pattern and the pixel electrode, wherein capacitance electrode and corresponding pixel electrode electrically connect, and pixel electrode is coupled with shared line pattern by capacitance electrode and forms a plurality of reservior capacitors.
In one embodiment of this invention, above-mentioned capacitance electrode comprises first capacitance electrode and second capacitance electrode.First capacitance electrode and electrically connects with first pixel electrode between the first common lines pattern and first pixel electrode.Second capacitance electrode and electrically connects with first pixel electrode between the second common lines pattern and first pixel electrode.In addition, the capacitance of the reservior capacitor that first capacitance electrode and the first common lines pattern are constituted is C1, and the capacitance of the reservior capacitor that second capacitance electrode and the second common lines pattern are constituted is C2, and C2＞C1.
In one embodiment of this invention, the capacitance of the reservior capacitor that constituted of above-mentioned second pixel electrode and the second common lines pattern is C3.
In one embodiment of this invention, above-mentioned capacitance electrode also comprises the 3rd capacitance electrode between the first common lines pattern and second pixel electrode, this the 3rd capacitance electrode and second pixel electrode electrically connect, and the capacitance of the reservior capacitor that the 3rd capacitance electrode and the first common lines pattern are constituted is C4, and C4＞C3.
In one embodiment of this invention, each above-mentioned pixel also comprises the capacitive coupling line, and wherein the capacitive coupling line and first pixel electrode electrically connect, and is positioned at second pixel electrode below.
In one embodiment of this invention, above-mentioned pixel electrode has jagged edge.
For reaching above-mentioned or other purpose, the present invention proposes a kind of method of testing, and it is suitable for testing aforesaid active component array base board.Voltage level that this method of testing comprises the following steps: to provide different or waveform are to each common lines pattern, to increase the voltage difference between each pixel electrode in each pixel; And according to voltage difference generation short circuit judgement.
In one embodiment of this invention, when the quantity of common lines pattern was 2, the common lines pattern was coupled to first voltage and second voltage that is lower than first voltage respectively.In one embodiment of this invention, first voltage for example is share voltage.In another embodiment of the present invention, first voltage can be higher than share voltage, and second voltage can be higher than, be equal to or less than share voltage.In another embodiment of the present invention, first voltage for example is lower than share voltage.
In one embodiment of this invention, when the quantity of common lines pattern was 3, the common lines pattern was coupled to first voltage respectively, is lower than second voltage and the tertiary voltage that is lower than second voltage of first voltage.In one embodiment of this invention, first voltage for example is share voltage.In another embodiment of the present invention, first voltage can be higher than share voltage, and second voltage can be higher than, be equal to or less than share voltage, and tertiary voltage can be higher than, be equal to or less than share voltage.In another embodiment of the present invention, first voltage for example is lower than share voltage.
In one embodiment of this invention, share voltage for example is between-50V and 50V.In addition, the voltage difference of first voltage and second voltage for example is between 0V and 100V.
In one embodiment of this invention, method of testing can further comprise finishes charging to each pixel electrode, and it is to carry out after each pixel electrode being finished charging that different voltage level to the step of each common lines pattern wherein is provided.
For reaching above-mentioned or other purpose, the present invention proposes a kind of LCD, and it comprises aforesaid active component array base board, subtend substrate, liquid crystal layer and control circuit board.The subtend substrate is disposed at the active component array base board top, liquid crystal layer is disposed between active component array base board and the subtend substrate, control circuit board then electrically connects with active component array base board and subtend substrate, and common lines pattern independent of each other is by the control circuit board conducting, and is coupled to share voltage.
In one embodiment of this invention, above-mentioned subtend substrate is a colored optical filtering substrates.
Because the present invention adopts a plurality of common lines patterns independent of each other, therefore the defective in active component array base board of the present invention and the LCD can be detected when the active component array base board manufacturing is finished effectively.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the top view according to the active component array base board of one embodiment of the invention.
Fig. 2 A and Fig. 2 B are the synoptic diagram of the voltage of share voltage and pixel electrode.
Fig. 3 A is the circuit diagram according to the single pixel of one embodiment of the invention.
Fig. 3 B is the top view according to the single pixel of one embodiment of the invention.
Fig. 4 be pixel among Fig. 3 B when testing, the synoptic diagram of the voltage of first pixel electrode and second pixel electrode.
Fig. 5 is the synoptic diagram according to the LCD of one embodiment of the invention.
[main element label declaration]
100: active component array base board
110: substrate
120: sweep trace
130: data line
140: the common lines pattern
142: the first common lines patterns
144: the second common lines patterns
150: pixel
152: active member
154: pixel electrode
156: capacitance electrode
158: the capacitive coupling line
E1: first capacitance electrode
E2: second capacitance electrode
E3: the 3rd capacitance electrode
P1: first pixel electrode
P2: second pixel electrode
T1: the first film transistor
T2: second thin film transistor (TFT)
200: LCD
210: the subtend substrate
220: liquid crystal layer
230: control circuit board
Embodiment
Fig. 1 is the top view according to the active component array base board of one embodiment of the invention.Please refer to Fig. 1, the active component array base board 100 of present embodiment comprises substrate 110, multi-strip scanning line 120, many data lines 130, a plurality of common lines pattern 140 independent of each other and a plurality of pixels 150.Wherein, sweep trace 120, data line 130 all are disposed on the substrate 110 with shared line pattern 140, and pixel 150 then is that arrayed is on substrate 110.As shown in Figure 1, each pixel 150 electrically connects with corresponding scanning line 120 and data line 130, and common lines pattern 140 is distributed in the below of each pixel 150.In addition, each pixel 150 comprises a plurality of active members 152 and a plurality of pixel electrode 154.Each pixel electrode 154 electrically connects by different active member 152 and corresponding scanning line 120 and data line 130 respectively, and each pixel electrode 154 is different with the capacitance coupling effect between the different common lines pattern 140.It should be noted that, when the capacitance coupling effect between each pixel electrode 154 and the different common lines pattern 140 not simultaneously, the unusual short circuit phenomenon that pixel electrode in the same pixel 150 is 154 just can be detected in the array test stage, and the detailed mechanism Fig. 3 that will arrange in pairs or groups describes.
In the present embodiment, substrate 110 for example is glass substrate, plastic base, or other hard substrate (rigid substrate) or soft substrate plate (flexible substrate).Generally speaking, the bearing of trend of sweep trace 120 for example is vertical with the bearing of trend of data line 130, certainly, along with the shape of pixel 150 is different with arrangement mode, as stripe-arrangement (strip arrangement), rounded projections arranged (delta arrangement), honeycomb arrangement (honeycomb arrangement) etc., the present invention can adopt the sweep trace 120 and data line 130 of different kenels.
In the present invention, the quantity of common lines pattern 140, active member 152 and pixel electrode 154 can be more than 2 or 2.In following embodiment, mainly be to be that example describes with 140,2 active members 152 of 2 common lines patterns and 2 pixel electrodes 154, so it is not in order to limit the present invention.
As shown in Figure 1, the common lines pattern 140 of present embodiment comprises the first common lines pattern 142 and the second common lines pattern 144, and the first common lines pattern 142 and the second common lines pattern 144 all are distributed in each pixel 150 below.In detail, because the first common lines pattern 142 and the second common lines pattern 144 on the active component array base board 100 are line pattern independent of each other (trace pattern), so the present invention can be coupled to different voltage levels respectively with the second common lines pattern 144 with the first common lines pattern 142, so that the pixel on the active component array base board 100 150 is tested.In addition, the active member 152 of present embodiment comprises the first film transistor T 1 and the second thin film transistor (TFT) T2, and pixel electrode 154 comprises first pixel electrode P1 that electrically connects with the first film transistor T 1 and the second pixel electrode P2 that electrically connects with the second thin film transistor (TFT) T2.In addition, the pixel electrode 154 of present embodiment (i.e. the first pixel electrode P1 and the second pixel electrode P2) can have zigzag (tooth-like) edge, as shown in Figure 1.
In order to improve aforesaid colour cast problem, present embodiment is designed to W respectively with the channel width/length ratio of the first film transistor T 1 and the second thin film transistor (TFT) T2
1/ L
1And W
2/ L
2, and the channel width/length ratio that makes the first film transistor T 1 and second thin film transistor (TFT) T2 difference (even W to some extent
1/ L
1≠ W
2/ L
2).In a preferred embodiment, for the channel width/length ratio that makes the first film transistor T 1 and the second thin film transistor (TFT) T2 has enough difference, we can make the channel width/length ratio of the first film transistor T 1 and the second thin film transistor (TFT) T2 satisfy (W usually
1/ L
1)/(W
2/ L
2The condition of) 〉=2.
In the present embodiment, each pixel 150 can further comprise a plurality of capacitance electrodes 156 that are disposed between common lines pattern 140 and the pixel electrode 154, wherein capacitance electrode 156 and corresponding pixel electrode 154 electric connections, and pixel electrode 154 forms a plurality of reservior capacitors by capacitance electrode 156 and 140 couplings of shared line pattern.As shown in Figure 1, capacitance electrode 156 is metal-insulator-metal (Metal-Insulator-Metal, framework MIM) with the reservior capacitor that shared line pattern 140 is constituted.Yet.It should be noted that the reservior capacitor in the pixel 150 of the present invention also can adopt metal-insulator-indium tin oxide (Metal-Insulator-ITO, framework MII); In other words, disclosed capacitance electrode 156 is selectivity member (optional element) in the present embodiment.
In the present embodiment, each pixel 150 also can further comprise capacitive coupling line 158, and wherein the capacitive coupling line 158 and the first pixel electrode P1 electrically connect, and is positioned at second pixel electrode P2 below.As shown in Figure 1, because the capacitive coupling line 158 and the first pixel electrode P1 electrically connect, and the voltage of capacitive coupling line 158 is different with the voltage of the second pixel electrode P2, so capacitive coupling line 158 can influence the voltage of the second pixel electrode P2 by capacitance coupling effect.In detail, during the first film transistor T 1 and second thin film transistor (TFT) T2 unlatching, the voltage of the second pixel electrode P2 can be subjected to the influence of the second thin film transistor (TFT) T2 and capacitive coupling line 158 simultaneously, and in the first film transistor T 1 and the second thin film transistor (TFT) T2 closed period, the voltage of the second pixel electrode P2 still can be subjected to the influence of capacitive coupling line 158.As described in the content of Taiwan number of patent application 94116051, its content is incorporated the application's reference into relevant for the relation between the capacitive coupling line 158 and the second pixel electrode P2.
Fig. 2 A and Fig. 2 B are the synoptic diagram of the voltage of share voltage and pixel electrode.Generally speaking, in the array test process, the array test board can be sent pulse width (pulse width) than the doubly above grid impulse (gate pulse) of actual panel operation long number, can be detected to guarantee most defective.In the case, the charging result of two pixel electrodes in the single pixel will be more similar, and therefore the unusual short circuit between two pixel electrodes can't be detected in the process of array test (array test) usually.Yet, utilization has the display panels that the thin-film transistor array base-plate of defective manufactures many fleck defects (bright dot defect) just can occur, this phenomenon will cause puzzlement in the manufacturing and the increase on the cost, and the grade of the display panels that manufactures simultaneously (grade) also can descend.Please refer to Fig. 2 A and Fig. 2 B, owing to existing array test board is difficult for judging small voltage differences, so the present invention controls the voltage that the voltage level that is coupled to the common lines pattern changes pixel electrode.When the voltage level that is coupled to the common lines pattern maintained same voltage level, the voltage of pixel electrode can not be subjected to the influence of common lines pattern and change (shown in Fig. 2 A).Otherwise when the voltage level that is coupled to the common lines pattern up was offset (swing up) to high-voltage level, the voltage of pixel electrode can be subjected to the influence of common lines pattern and rise (shown in Fig. 2 B).By Fig. 2 B as can be known, the voltage of pixel electrode can change along with the voltage of common lines pattern and rise or descend.
Fig. 3 A is the circuit diagram according to the single pixel of one embodiment of the invention, and Fig. 3 B is the top view according to the single pixel of one embodiment of the invention.Please be simultaneously with reference to Fig. 3 A and Fig. 3 B, the capacitance electrode 156 of present embodiment comprises at least one first capacitance electrode E1 and at least one second capacitance electrode E2.Wherein, the first capacitance electrode E1 is between the first common lines pattern 142 and the first pixel electrode P1, and by contact hole CH1 and first pixel electrode P1 electric connection.The second capacitance electrode E2 is between the second common lines pattern 144 and the first pixel electrode P1, and by contact hole CH2 and first pixel electrode P1 electric connection.In addition, the capacitance of the reservior capacitor that the first capacitance electrode E1 and the first common lines pattern 142 are constituted is C1, and the capacitance of the reservior capacitor that the second capacitance electrode E2 and the second common lines pattern 144 are constituted is C2, and C2＞C1.
Hold above-mentionedly, the capacitance of the reservior capacitor that the second pixel electrode P2 and the second common lines pattern 144 are constituted is C3.In addition, the capacitance electrode 156 of present embodiment can further comprise the 3rd capacitance electrode E3 between the first common lines pattern 142 and the second pixel electrode P2, this the 3rd capacitance electrode E3 and the second pixel electrode P2 electrically connect by contact hole CH3, and the capacitance of the reservior capacitor that the 3rd capacitance electrode E3 and the first common lines pattern 142 are constituted is C4, and C4＞C3.
Fig. 4 be pixel among Fig. 3 B when testing, the synoptic diagram of the voltage of first pixel electrode and second pixel electrode.Please refer to Fig. 3 B and Fig. 4, in order to increase by the voltage differences of the first pixel electrode P1 and the second pixel electrode P2, the present invention provides different voltage level or waveforms respectively with each common lines pattern, to increase the voltage difference (being illustrated as Fig. 4) between each pixel electrode.Particularly, present embodiment can be earlier transmits grid impulse by sweep trace, opening the first film transistor T 1 and the second thin film transistor (TFT) T2, and the first pixel electrode P1 and the second pixel electrode P2 is charged.After the first pixel electrode P1 and second pixel electrode P2 charging is finished, the first film transistor T 1 and the second thin film transistor (TFT) T2 just close immediately, at this moment, the voltage that the present embodiment may command is coupled to the first common lines pattern 142 up is offset (swing up) to first voltage, and the voltage that control is coupled to the second common lines pattern 144 down is offset (swing down) to second voltage that is lower than aforementioned first voltage.The common lines pattern is being coupled to different voltage level (first voltage and second voltage) respectively afterwards, measure the voltage difference between each pixel electrode, and judge the phenomenon whether unusual short circuit is arranged between each pixel electrode that is electrically insulated each other according to measured voltage difference.
In the present embodiment, the first common lines pattern 142 is to be coupled to first voltage, and the second common lines pattern 144 then is to be coupled to second voltage that is lower than first voltage.Wherein, employed share voltage when first voltage for example is the display panel normal running, second voltage then is to be lower than share voltage.Certainly, the present invention also can use first voltage that is lower than or is higher than share voltage, and when first voltage was higher than share voltage, second voltage can be higher than, be equal to or less than share voltage.
Fig. 3 B and Fig. 4 are to be that example describes with 2 common lines patterns (142,144), two pixel electrodes (P1, P2), and right the present invention does not limit to the quantity of common lines pattern and pixel electrode in the single pixel.For instance, the quantity of common lines pattern and pixel electrode can also be 3, and in the case, the common lines pattern for example is second voltage and the tertiary voltage that is lower than second voltage that is coupled to first voltage respectively, is lower than first voltage.In one embodiment of this invention, first voltage for example is share voltage.In another embodiment of the present invention, first voltage can be lower than or be higher than share voltage.When first voltage was higher than share voltage, second voltage can be higher than, be equal to or less than share voltage, and tertiary voltage can be higher than, be equal to or less than share voltage.
Fig. 5 is the synoptic diagram according to the LCD of one embodiment of the invention.Please refer to Fig. 5, the LCD 200 of present embodiment comprises aforesaid active component array base board 100, subtend substrate 210 (for example being colored optical filtering substrates), liquid crystal layer 220 and control circuit board 230.Wherein, subtend substrate 210 is disposed at active component array base board 100 tops, liquid crystal layer 220 is disposed between active component array base board 100 and the subtend substrate 210, and control circuit board 230 then electrically connects with active component array base board 100 and subtend substrate 220.It should be noted that common lines pattern 140 independent of each other on the active component array base board 100 (sharing the existing line pattern 142 and the second common lines pattern 144 as first) is the conducting each other by control circuit board 230, and be coupled to share voltage.
Because the present invention adopts a plurality of common lines patterns independent of each other, therefore the defective in active component array base board of the present invention and the LCD can be detected when the active component array base board manufacturing is finished effectively, and then improve and make yield, attenuating processing procedure cost, and promote the grade of display panels.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (21)
1. active component array base board comprises:
Substrate;
Multi-strip scanning line, many data lines and a plurality of common lines pattern independent of each other are disposed on this substrate;
A plurality of pixels, arrayed are on this substrate, and wherein each pixel and corresponding scanning line and data line electrically connect, and those common lines pattern distribution are in each pixel below, and each pixel comprises:
A plurality of active members; And
By different active members and corresponding scanning line and data line electric connection, wherein each pixel electrode is different with the capacitance coupling effect between each common lines pattern respectively for a plurality of pixel electrodes, each pixel electrode.
2. active component array base board according to claim 1, wherein those common lines patterns comprise:
The first common lines pattern; And
The second common lines pattern, wherein this first common lines pattern and this second common lines pattern distribution are in each pixel electrode below.
3. active component array base board according to claim 2, wherein those active members comprise the first film transistor and second thin film transistor (TFT), and those pixel electrodes comprise first pixel electrode that electrically connects with this first film transistor and second pixel electrode that electrically connects with this second thin film transistor (TFT).
4. active component array base board according to claim 3, wherein the transistorized channel width/length of this first film ratio is W
1/ L
1, and the channel width/length ratio of this second thin film transistor (TFT) is W
2/ L
2, and W
1/ L
1≠ W
2/ L
2
5. active component array base board according to claim 4, wherein (W
1/ L
1)/(W
2/ L
2) 〉=2.
6. active component array base board according to claim 3, each pixel also comprises a plurality of capacitance electrodes, be disposed between those common lines patterns and those pixel electrodes, wherein those capacitance electrodes and corresponding pixel electrode electrically connect, and those pixel electrodes are coupled with those common lines patterns by those capacitance electrodes and form a plurality of reservior capacitors.
7. active component array base board according to claim 6, wherein those capacitance electrodes comprise:
First capacitance electrode between this first common lines pattern and this first pixel electrode, and electrically connects with this first pixel electrode; And
Second capacitance electrode, between this second common lines pattern and this first pixel electrode, and electrically connect with this first pixel electrode, wherein the capacitance of the reservior capacitor that constituted of this first capacitance electrode and this first common lines pattern is C1, and the capacitance of the reservior capacitor that this second capacitance electrode and this second common lines pattern are constituted is C2, and C2＞C1.
8. active component array base board according to claim 7, wherein the capacitance of the reservior capacitor that constituted of this second pixel electrode and this second common lines pattern is C3, wherein those capacitance electrodes also comprise the 3rd capacitance electrode, between this first common lines pattern and this second pixel electrode, and electrically connect with this second pixel electrode, and the capacitance of the reservior capacitor that the 3rd capacitance electrode and this first common lines pattern are constituted is C4, and C4＞C3.
9. active component array base board according to claim 6, wherein each pixel also comprises the capacitive coupling line, wherein this capacitive coupling line and this first pixel electrode electrically connect, and are positioned at this second pixel electrode below.
10. active component array base board according to claim 1, wherein those pixel electrodes have jagged edge.
11. a method of testing is suitable for testing the active component array base board of claim 1, this method of testing comprises the following steps:
Provide different voltage level or waveform to each common lines pattern, to increase the voltage difference between each pixel electrode in each pixel; And
Producing short circuit according to this voltage difference judges.
12. method of testing according to claim 11, when the quantity of those common lines patterns was 2, those common lines patterns were coupled to first voltage and second voltage that is lower than this first voltage respectively.
13. method of testing according to claim 12, wherein this first voltage is higher than share voltage, and this second voltage is higher than, is equal to or less than this share voltage.
14. method of testing according to claim 13, wherein this share voltage is between-50V and 50V.
15. method of testing according to claim 12, wherein the voltage difference of this first voltage and this second voltage is between 0V and 100V.
16. method of testing according to claim 11, when the quantity of those common lines patterns was 3, those common lines patterns were coupled to first voltage respectively, are lower than second voltage and the tertiary voltage that is lower than this second voltage of this first voltage.
17. method of testing according to claim 16, wherein this first voltage is higher than share voltage, and this second voltage is higher than, is equal to or less than this share voltage, and this tertiary voltage is higher than, is equal to or less than this share voltage.
18. method of testing according to claim 16, wherein the voltage difference of this first voltage and this second voltage is between 0V and 100V.
19. method of testing according to claim 11 also comprises those pixel electrodes are finished charging, it is to carry out after those pixel electrodes being finished charging that different voltage level to the step of each common lines pattern wherein is provided.
20. a LCD comprises:
Active component array base board according to claim 1;
The subtend substrate is disposed at this active component array base board top;
Liquid crystal layer is disposed between this active component array base board and this subtend substrate; And
Control circuit board electrically connects with this active component array base board and this subtend substrate, and wherein those common lines patterns are by this control circuit board conducting, and are coupled to share voltage.
21. LCD according to claim 20, wherein this subtend substrate comprises colored optical filtering substrates.
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| CN109426014B (en) * | 2017-08-29 | 2020-11-06 | 京东方科技集团股份有限公司 | Array substrate preparation method |
| CN108363246A (en) * | 2018-02-26 | 2018-08-03 | 惠科股份有限公司 | Display panel and curved surface display device |
| CN108917570B (en) * | 2018-07-26 | 2020-05-26 | 京东方科技集团股份有限公司 | Detection probe, registration precision detection device and detection method thereof |
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| CN1573341A (en) * | 2003-05-21 | 2005-02-02 | 国际商业机器公司 | Inspection device and inspection method for active matrix panel, and manufacturing method for active matrix organic light emitting diode panel |
| CN1637561A (en) * | 2003-12-30 | 2005-07-13 | Lg.菲利浦Lcd株式会社 | In-plane switching mode liquid crystal display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101509967B (en) * | 2009-03-10 | 2011-06-15 | 华映光电股份有限公司 | Detecting line for detecting coupling effect of multiple switch assembly and detecting method thereof |
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| CN1920652A (en) | 2007-02-28 |
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