CN100403451C

CN100403451C - Nonvolatile semiconductor storage manufactured for changing erase unit

Info

Publication number: CN100403451C
Application number: CNB2003101015665A
Authority: CN
Inventors: 二箇谷知士; 早坂隆; 小仓卓
Original assignee: Renesas Technology Corp
Current assignee: Renesas Electronics Corp
Priority date: 2003-01-27
Filing date: 2003-10-08
Publication date: 2008-07-16
Anticipated expiration: 2023-10-08
Also published as: CN1518002A; TWI227896B; TW200414211A; JP4229712B2; KR20040068851A; KR100520596B1; US6760259B1; JP2004227736A

Abstract

Particular blocks (B000-B007) are a boot block and parameter block having a storage capacity smaller than that of a general block. In the case where a boot block is not required, a signal BOOTE is set at an L level. In the case where a signal BLKSEL is at an H level in an erasure mode, a control unit (2) selects four blocks aligned in a horizontal direction at the same time. The control unit (2) also selects two blocks simultaneously in the vertical direction. As a result, the particular eight blocks (B000-B007) are selected. The boot block and parameter block can be erased collectively as one block having a capacity similar to that of a general block. Therefore, a flash memory corresponding to the case of including a boot block and not including a boot block can be implemented simultaneously with one chip. Thus, the designing and fabrication process can be simplified.

Description

The Nonvolatile semiconductor memory device that changes erase unit and make

Technical field

The present invention relates to Nonvolatile semiconductor memory device, particularly variable erase unit storage block structured flash memory.

Background technology

On function, but the Nonvolatile semiconductor memory device that flash memory is the electronically written of erasing type in batch to be wiped.Because the flash memory cost is low and have an electric erase feature, in portable electronics etc., very big demand is arranged, its research and development are in vogue in recent years.Flash memory for example is provided with transistor floating gate, that can change threshold voltage (hereinafter referred to as memory transistor) and is used as the storage unit use.

Figure 26 is the diagrammatic sketch of the array structure of traditional flash memory.

Among Figure 26, simple in order to make explanation, just integral body describes for the situation of the storage array of 8M position.Storage array 500 contains: storage block B000～B007 that each is made of the storage unit that is equivalent to 4k word (64k position), storage block B008～B022 that each is made of the storage unit that is equivalent to 32k word (512k position), and storage block B100.Storage block B000～B022 respectively is the storage block that becomes the base unit of erase operation in flash memory.

In flash memory, need the zone of 4k word usually, therefore, storage array 500 contains storage block B000～B007 that memory space is lacked than common data storage area.The zone of such 4k word for example can be described as bootstrap block or parameter block.

The zone that CPU read of the system of flash memory when being system start-up after energized, is installed bootstrap block.And parameter block is frequently to rewrite the zone that the high data of possibility temporarily write.On the other hand, the storage block of 32k word memory space is used as the zone of storage data or program usually.In flash memory, the storage block of different size must be set by purposes like this.

In addition, storage block B100 is the zone that is equivalent to storage block B000～B007 on address assignment, is to be set as obsolete zone.Even do not use, for the successional needs that keep the signal on the storage array, storage block B100 also has the structure same with each structure of storage block B008～B022.

The selection of storage block, block selection signal BAVS0, BAVS1, the BAVM0～BAVM3 of the lengthwise position by selecting storage block and select the block selection signal BAH0～BAH3 of the lateral attitude of storage block to carry out.If storage block position and horizontal storage block position are activated simultaneously longitudinally, the storage block that then is positioned on this intersection point is just selected.For example, when selecting storage block B008, select signal BAVM0 and BAH1 to be activated, remaining selection signal is by deactivation.

Figure 27 is the block scheme that traditional piece of the selection signal of expression generation storage block is selected decoder architecture.

With reference to Figure 26, Figure 27, piece selects demoder 502 to adopt the address bit A12～A18 of the address signal of being supplied with by the outside to produce block selection signal BAVS0, BAVS1, BAVM0～BAVM3, BAH0～BAH3.Piece selects demoder 502 to contain: accept the four-input terminal NOR circuit 562 that signal BOP is selected in address bit A15, A16, A17, A18 and output, according to address bit A14, A17, A18 and the selection signal BAVS0 of selection signal BOP output lengthwise position, vertical block selection circuit 564 of BAVS1, BAVM0～BAVM3, and the horizontal block selection circuit 566 of exporting the selection signal BAH0～BAH3 of lateral attitude according to address bit A12, A13, A15, A16 and selection signal BOP.

Vertically block selection circuit 564 contains: according to selecting signal BOP to be activated, to address bit A14 decode and with signal BAVS0, BAVS1 output address decoder part 582, and when selecting signal BOP to be non-activated state, working, and out-of-work address decoder part 584 when selecting signal BOP to be activated.Address decoder part 584 is decoded to address bit A17, A18 when activating and with signal BAVM0～BAVM3 output.

Laterally block selection circuit 566 contains: when selecting signal BOP to be activated, with address bit A12, A13 serves as to select address bit SA0, SA1 output, and when selecting signal BOP to be non-activated state, with address bit A15, A16 is the address selection part 610 of selecting address bit SA0, SA1 output, and to select address bit SA0, SA1 decodes and with the address decoder part 612 of signal BAH0～BAH3 output.

In the storage array of 8M position shown in Figure 26, when to adopt 1 word be 16 structure, selecting the address bit of 32k word storage block was A15, A16, A17, A18.And selecting the address bit of 4k word storage block is A12, A13, A14.Here in Shuo Ming the conventional case, describe with regard to the situation of the structure of four storage blocks of lateral arrangement shown in Figure 26.

At first, select activation/non-activation of the signal BOP in 4k block by 562 decisions of NOR circuit.

When input is equivalent to the address of storage block B008～B022, signal BOP is by deactivation, and address decoder part 582 is signal BAVS0, BAVS1 deactivation, and address decoder part 584 activates any one among the selection signal BAVM0～BAVM3 of vertical storage block according to address bit A17, A18.

At this moment, because address selection part 610 serves as to select address bit SA0, SA1 output with address bit A15, A16, address decoder part 612 couples of address bit A15, A16 decode, and activate any one that select among signal BAH0～BAH3.

On the other hand, when address bit A15～A18 all is the L level, select signal BOP to be activated.This expression have with Figure 26 in be made as the input of the corresponding address of obsolete storage block B100.At this moment, select the corresponding region among storage block B000～B007 and do not select storage block B100.Specifically, when signal BOP was in activated state, address decoder part 584 was by deactivation, and signal BAVM0～BAVM3 is by deactivation.Decoded by address decoder part 582 address bit A14 then, the either party among signal BAVS0, the BAVS1 is activated.

And, when signal BOP was in activated state, address selection part 610 served as to select address bit SA0, SA1 output with address bit A12, A13, therefore, address decoder part 612 is decoded address bit A12, A13, and makes any one activation among signal BAH0～BAH3.

All the time, the storage block of selecting demoder 502 to be determined by piece is cut apart with address assignment and is fixed usually.In other words, the zone of 8M position size be divided into usually 8 4k word storage blocks and 15 32k word storage block B008～B022 totally 23 storage blocks used.

As described above, because the storage block B000～B022 of 23 uses is arranged in the storage array 500 of Figure 26,, must indicate 23 times erase operation by chip exterior in order to wipe the storage array of whole 8M position.

And among Figure 26, the storage block of 8 4k words is the most the next side that storage block B000～B007 is assigned to the address.This is called the bottom-boot type.But,, need the storage block of 4k word to be distributed in the flash memory of top leading type of the upper side of address sometimes according to the system that is used.In conventional art, the storer that changes to the top leading type for the storer with the bottom-boot type uses, and in the address input buffer device, carries out the anti-phase operation of specific address bit.

Figure 28 is the circuit diagram of traditional address input buffer device 516 structures of expression.

With reference to Figure 28, have in the address input buffer device 516: the signal TOP that is activated when using according to the storer that is switched to the top leading type, with positive/anti-phase address negative circuit of switching respectively 520,522,524 of address bit A15, A16, A17.

Be provided with in the address negative circuit 520: accept the address bit ext.A15 that supplies with by the outside and in addition anti-phase phase inverter 526, acknowledge(ment) signal TOP and in addition anti-phase phase inverter 528, accept the output of phase inverter 526 and the NAND circuit 530 of signal TOP, accept the NAND circuit 532 of the output of address bit ext.A15 and phase inverter 528, and accept the output of NAND circuit 530,532 and the NAND circuit 534 that address bit A15 is exported.

The difference of address negative circuit 522 is: input address position ext.A16 and OPADD position A16, but its inner structure is identical with address negative circuit 520, no longer repeat specification.The difference of address negative circuit 524 is: input address position ext.A17 and OPADD position A17, but its inner structure is identical with address negative circuit 520, no longer repeat specification.

Figure 29 is the diagrammatic sketch of the array structure of another kind of conventional flash memory.

With reference to Figure 29, storage block B000～B015 is each storage block that is made of the storage unit that is equivalent to 32k word (512k position).In storage array 700, be not equivalent to the storage block of the storage unit formation of 4k word, all be to constitute 8M position district by 16 storage blocks that the storage unit that is equivalent to the 32k word constitutes.In the storage array 500 of Figure 26, to wiping the erase operation that 8M position district needs 23 times, but in storage array 700, finish by 16 erase operations wiping 8M position district.

In addition, about the prior art document of memory block erasing, Japanese Patent Application Laid-Open 2002-133877 communique is for example arranged.

In conventional art, storage block is cut apart with the address assignment to each storage block often fixing.As a result, for example, as illustrating among Figure 26, in the product of the flash memory of 8M position, have in the product of specification of storage block of 4k word, have 8 4k word storage blocks and 15 32k word storage blocks totally 23 storage blocks.

On the other hand, as illustrating among Figure 29, in the product of the flash memory of the storage block that is not provided with the 4k word, constitute the 8M position by 16 32k word storage blocks.In other words, need to design and make diverse product according to whether the 4k word being arranged.

And, along with the expansion of the capacity of flash memory, developed not only upper side or the most the next side, but the chip of the bootstrap block of 4k word storage block all arranged in the most the next side in address and upper side in address assignment.Such chip is called the dual boot cake core.When two dual boot cake cores of combination use as bigger storage spaces, at the middle body of address space the tiny storage block of 4k word is arranged, there is the problem that goes up inconvenience of using.

Summary of the invention

The objective of the invention is to: be divided into a plurality of erase block memories, and wherein the less storage block of memory space for example is provided with in the flash memory of bootstrap block, realize the flash memory of 4k word storage block simultaneously and do not have the flash memory of 4k word storage block with a chip, and simplify its design and make.

The summary speech, the present invention is a kind of Nonvolatile semiconductor memory device, wherein is provided with: become the first basic storage block of the unit of wiping in batch, a plurality of second basic storage block, and wipe control circuit.The first basic storage block, wherein a plurality of memory cell matrix shapes are arranged, and have first memory space of the unit that formation wipes in batch.On a part that has less than the first basic storage block of second memory space of first memory space, do not constitute the unit of wiping in batch.The a plurality of second basic storage block is separated setting in addition with the first basic storage block.In each storage block of a plurality of second basic storage block, a plurality of memory cell matrix shapes are arranged.The a plurality of second basic storage block has second memory space separately.The summation of the memory space of a plurality of second basic storage block is identical with first capacity.Wipe control circuit and switch first operation and second operation, just wipe first operation of a storage block in a plurality of second basic storage block and wipe second of a plurality of second basic storage block in batches according to erasing instruction and operate according to erasing instruction according to switching signal.

Be provided with in the Nonvolatile semiconductor memory device of another form of the present invention: become the first basic storage block of erase unit in batch, a plurality of second basic storage block, and wipe control circuit.The first basic storage block, wherein a plurality of memory cell matrix shapes are arranged, and have to constitute first memory space of erase unit in batch.On a part that has less than the first basic storage block of second memory space of first memory space, do not constitute the unit of wiping in batch.The a plurality of second basic storage block is separated setting in addition with the first basic storage block.In each storage block of a plurality of second basic storage block, a plurality of memory cell matrix shapes are arranged.The a plurality of second basic storage block has second memory space separately.The summation of the memory space of a plurality of second basic storage block is identical with first capacity.Wipe control circuit and switch first operation and second operation, just wipe first operation of a storage block in a plurality of second basic storage block and wipe second of the first basic storage block according to erasing instruction and operate according to erasing instruction according to switching signal.

Therefore, according to the present invention, supply method by the change switching signal just can be realized multiple Nonvolatile semiconductor memory device, as with storage block as erase unit separately and concentrate the Nonvolatile semiconductor memory device of less storage block as an erase unit, thereby can reduce the development cost and the manufacturing management expense of many kinds.

For above-mentioned and other purpose, feature, form and advantage of the present invention, below will provide clear elaboration about detailed description of the present invention by what accompanying drawing was understood.

Description of drawings

Fig. 1 is the simple block diagram of structure of the Nonvolatile memory device of the expression embodiment of the invention 1.

Fig. 2 is the cut-open view in order to the memory transistor MT of rectangular arrangement on each storage block of explanation storage array 26.

Fig. 3 is the circuit diagram of the structure of the switching signal generation circuit 10 in the presentation graphs 1.

Fig. 4 is the diagrammatic sketch of explanation to the welding selection scheme of the switching signal generation circuit of Fig. 3.

Fig. 5 is the diagrammatic sketch of the relation between the set condition of explanation signal #NOBOOT, #BOOT and the signal BOOTE that switches usefulness.

Fig. 6 is the block scheme in order to the structure of the preposition demoder of key diagram 1.

Fig. 7 is the circuit diagram in order to the structure of the vertical block selection circuit in the key diagram 6.

Fig. 8 is the circuit diagram of the structure of the horizontal block selection circuit in the presentation graphs 6.

Fig. 9 is the process flow diagram of the operating process during in order to the memory block erasing of the internal controller in the key diagram 1.

Figure 10 is the circuit diagram in order to first variation that switching signal generation circuit illustrated in fig. 3 is described.

Figure 11 is the setting of explanation switching signal generation circuit shown in Figure 10 and the diagrammatic sketch of output.

Figure 12 is the circuit diagram of second variation of expression switching signal generation circuit.

Figure 13 is the diagrammatic sketch in order to the relation between the signal BOOTE of the state of explanation fuse element and control switching.

Figure 14 is the circuit diagram of the 3rd variation of expression switching signal generation circuit.

Figure 15 is the diagrammatic sketch in the relation between preset threshold voltage and the signal BOOTE on the memory transistor of the switching signal generation circuit of Figure 14.

Figure 16 is the block scheme in order to the Nonvolatile semiconductor memory device structure of the variation of explanation embodiment 1.

Figure 17 is the process flow diagram in order to the erase operation of the internal controller among explanation Figure 16.

Figure 18 is the block scheme of structure of the preposition demoder 18B of expression embodiment 2.

Figure 19 is the circuit diagram of the structure of the vertical block selection circuit among expression Figure 18.

Figure 20 is the circuit diagram of the structure of the horizontal block selection circuit among expression Figure 18.

Figure 21 is the diagrammatic sketch that is suitable for dual boot type storage array of the present invention, that in the bottom and the both sides, top of address area 4k word storage block is set all in order to illustrate.

The diagrammatic sketch of the structure of the dual boot when Figure 22 is explanation realization combination two chips.

The diagrammatic sketch of the structure of the bottom-boot when Figure 23 is explanation realization combination two chips.

The diagrammatic sketch of the structure of the top guiding when Figure 24 is explanation realization combination two chips.

The diagrammatic sketch of the structure of the no leading type when Figure 25 is explanation realization combination two chips.

Figure 28 is the circuit diagram of the structure of the traditional address input buffer device 516 of expression.

Embodiment

Below, with reference to accompanying drawing embodiments of the invention are elaborated.In addition, prosign is represented identical or suitable part among the figure.

Embodiment 1

Fig. 1 is the simple block diagram of the Nonvolatile memory device structure of the expression embodiment of the invention 1.

With reference to Fig. 1, Nonvolatile semiconductor memory device 1 comprises: inputoutput data impact damper 22, and the control section 2 of the control that writes, reads, wipes, OK/and column decoder 20, Y door 24, and storage array 26.

Inputoutput data impact damper 22 is being write fashionable outside acknowledge(ment) signal DQ0～DQ15 from chip, when reading to the external output signal DQ0～DQ15 of chip.

Control section 2 comprises: Cheng Xusheji ﹠amp; Checking circuit 4, sensor amplifier 6, internal controller 8, address buffer 16, preposition demoder 18, and switching signal generation circuit 10.Internal controller 8 is accepted the control signals such as signal CE, WE, OE, RP, WP from the outside, the indication that identification is supplied with by the outside and to address buffer 16, preposition demoder 18 and program design; Checking circuit 4 is controlled.And internal controller 8 activates the laggard horizontal reset of certain hour to the power-on-reset signal POR of switching signal generation circuit 10 outputs and removes when power supply is inserted chip.

Switching signal generation circuit 10 is according to predetermined setting output signal BOOTE.Address buffer 16 is accepted the address bit ext.A0～ext.A18 by the address signal of outside supply respectively, to preposition demoder 18 OPADD position A0～A18.Preposition demoder 18 according to by control signal such as internal controller 8 signal supplied BLKSEL and the switching operated by switching signal generation circuit 10 signal supplied BOOTE, and changes the decoded result of address bit A0～A18.Preposition demoder 18 is to row/column decoder 20 output decoder results.

Storage array 26 contains: the storage block B008～B022, the B100 that have the storage block B000～B007 of the memory space of 4k word separately and have the memory space of 32k word separately.But storage block B100 is the zone that usually is not used, but for convenience in the manufacturing of storage array and the continuity that keeps pattern, is made as the structure same with storage block B008～B022.

Storage block B000～B007 is memory space bootstrap block and the parameter block littler than common storage block.When not needing bootstrap block, signal BOOTE is made as the L level by welding selection etc.When signal BLKSEL is the H level when wiping, when carrying out four transversely arranged storage blocks, control section 2 selects.And, selected when this moment, control section 2 carried out longitudinally two storage blocks.The result carries out the selection of 8 storage block B000～B007 etc.Bootstrap block and parameter block can be used as a storage block that has with the same capacity of generic storage piece and wipe in batch.

Fig. 2 is the cut-open view of memory transistor MT of rectangular arrangement on each storage block of explanation storage array 26.

With reference to Fig. 2, memory transistor MT comprises: the impurity range that forms on substrate S UB is source S and drain D, the floating gate F that the top in the zone between source S and drain D forms, and the control grid G of the top of floating gate F formation.

Can satisfy predetermined condition by the voltage VWELL that makes the voltage VG, the voltage VS that supplies with source electrode that supply with the control grid, supplies with the voltage VD of drain electrode and supply with the substrate part and change the quantity of electric charge to the floating gate F of memory transistor MT charging, thereby, the threshold voltage variation of memory transistor MT, therefore, memory transistor MT can store the information that the value by threshold voltage provides.

With reference to Fig. 3, switching signal generation circuit 10 comprises: the resistance 32 that connects between pad 56 that is supplied to signal #NOBOOT and node N2, the resistance 34 that between pad 58 that is supplied to signal #BOOT and node N1, connects, the electric capacity 36 that between the node of node N1 and supply power current potential VCC, connects, the electric capacity 42 that between node N2 and ground connection node, connects, connect input end on the node N2 and on node N1, connecting the phase inverter 38 of output terminal, connect input end on the node N1 and on node N2, connecting the phase inverter 40 of output terminal, on node N2, connect the phase inverter 44 of input end, and accept the output of phase inverter 44 and the phase inverter 46 of anti-phase and output signal BOOTE.

Fig. 4 is the diagrammatic sketch of the welding of the switching signal generation circuit of Fig. 3 being selected in order to explanation.

Fig. 5 is the diagrammatic sketch in order to the relation between the signal BOOTE of the set condition of explanation signal #NOBOOT, #BOOT and switching usefulness.

With reference to Fig. 4, Fig. 5, when the pad 56 of supplying with signal #NOBOOT was set to the L level, the lead-in wire 52 that will be supplied to earthing potential with lead 54 in a plurality of lead-in wires around the chip 50 linked to each other with pad 56.At this moment, pad 58 is not connected with any lead-in wire, perhaps is connected with the lead-in wire that is supplied to power supply potential with another lead.When so setting, be set to the L level in order to the signal BOOTE that switches.

When signal BOOTE was set at the L level, the storage block B000 of Fig. 1～B007 can wipe with once indicating in batch as a storage block with 32k word memory space.In the occasion that does not need bootstrap block, in order to shorten the erasing time, select welding like this, carry out the production of Nonvolatile semiconductor memory device.

On the other hand, not to connect, but will go between 52 when being connected that signal #BOOT is set to the L level with pad 58 with lead 55 with lead 54.Can adopt other lead to be connected at this occasion pad 56, also can be not-connected status with the lead-in wire of supply power current potential.When setting like this, be set to the H level in order to the signal BOOTE that switches.

When signal BOOTE is set at the H level, need to be equivalent to the occasion of bootstrap block, storage block B000～B007 uses as basic erase unit separately.

With reference to Fig. 6, preposition demoder 18 comprises: accept address bit A15, A16, A17, the four-input terminal NOR circuit 62 of A18 and output signal BOP, as control signal acknowledge(ment) signal BOOTE, BLKSEL and BOP also will be according to address bit A14, A17, A18 carries out the signal BAVS0 of the selection of storage block position longitudinally, BAVS1, vertical block selection circuit 64 of BAVM0～BAVM3 output, as control signal acknowledge(ment) signal BOOTE, BLKSEL and BOP also will be in order to according to address bit A12, A13, A15, A 16 carries out the horizontal block selection circuit 66 of the signal BAH0～BAH3 output of the selection of horizontal storage block position, accept the preposition decoding circuit 68 of address bit A6～A15 and the output preposition decoded signal PDROW relevant with the row selection, and the preposition decoding circuit 70 of exporting the preposition decoded signal PDCOL relevant with column selection based on address bit A0～A5.

Based on signal BAVS0, BAVS1, BAVM0～BAVM3 and signal BAH0～BAH3, preposition decoded signal PDROW, row decoder 72 is gone selection.And based on signal BAH0～BAH3 and preposition decoded signal PDCOL, column decoder 74 carries out column selection.

As control signal signal supplied BOOTE is by the signal of switching signal generation circuit 10 generations of Fig. 1, is set to the H level when needs 4k word bootstrap block.And signal BLKSEL is the output signal of the internal controller 8 of Fig. 1, the signal of selection operation when being a plurality of storage block of control.

Fig. 7 is the circuit diagram in order to the structure of vertical block selection circuit of key diagram 6.

With reference to Fig. 7, vertically block selection circuit 64 comprises: according to the address decoder part 82 of address bit A14 output signal BAVS0, BAVS1 with according to the address decoder part 84 of address bit A17, A18 output signal BAVM0～BAVM3.

Address decoder part 82 comprises: at signal BLKSEL is the H level, and when signal BOOTE is the L level, the signal of output H level and export the gate circuit 86 of the signal of L level in other cases, at signal BOOTE is the H level, and when address bit A14 is the L level, the signal of output H level and export the gate circuit 88 of the signal of L level and the AND circuit 90 of acknowledge(ment) signal BOOTE and address bit A14 in other cases.

Address decoder part 82 also comprises: the OR circuit 92 of accepting the output of

gate circuit

86,88, accept the OR circuit 94 of the output of the output of gate circuit 86 and AND circuit 90, accept the output of OR circuit 92 and the AND circuit 96 of signal BOP and output signal BAVS0, and accept the output of OR circuit 94 and the AND circuit 98 of signal BOP and output signal BAVS1.

Address decoder part 84 comprises: the NOR circuit 102 of three input ends of acknowledge(ment) signal BOP and address bit A17, A18 and output signal BAVM0, the address bit A17 that is activated when signal BOP is the L level is the gate circuit 104 that H level and address bit A18 activate signal BAVM1 when being the L level, at address bit A17 is the gate circuit 106 that L level and address bit A18 activate signal BAVM2 when being the H level, and the AND circuit 108 of accepting address bit A17, A18 and output signal BAVM3.

Why not to gate circuit 106 and AND circuit 108 input signal BOP, be that the NOR circuit 62 of Fig. 6 is set to the L level with BOP, need not input because address bit A18 is when being the H level.

In addition, when signal BOOTE was the H level, the operation of vertical block selection circuit 64 and traditional vertical block selection circuit were identical.At signal BOOTE is L level and signal BLKSEL when being the L level, and vertically the operation of block selection circuit 64 is also identical with traditional vertical block selection circuit.

At signal BOOTE is L level and signal BLKSEL when being the H level, still be the H level no matter address bit A14 is in the L level, and signal BAVS0, BAVS1 become the H level simultaneously, selection when carrying out longitudinally two storage blocks.

With reference to Fig. 8, laterally block selection circuit 66 comprises: alternatively position, location SA0, SA1 select still the address selection part 110 selected of position, location SA0, SA1 alternatively with address bit A15, A16 with address bit A12, A13 according to signal BOP decision, select the address decoder part 112 of the decoding of address bit SA0, SA1, and the output of decision address decoder part 112 output 114 whether effectively.

Address selection part 110 comprises: acknowledge(ment) signal BOP and in addition anti-phase phase inverter 116, accept the NAND circuit 118 of address bit A12 and signal BOP, accept the NAND circuit 120 of the output of address bit A15 and phase inverter 116, and the NAND circuit 122 of accepting the output of NAND circuit 118,120 and will selecting address bit SA0 to export.

Address selection part 110 also comprises: the NAND circuit 124 of accepting address bit A13 and signal BOP, accept the NAND circuit 126 of the output of address bit A16 and phase inverter 116, the NAND circuit 128 of accepting the output of NAND circuit 124,126 and will selecting address bit SA1 to export.

Address decoder part 112 comprises: detect the decode gates circuit 130 of selecting address bit SA0, SA1 to be the situation of L level, detecting and selecting address bit SA0 is that H level and selection address bit SA1 are the decode gates circuit 132 of the situation of L level, detecting and selecting address bit SA0 is L level and to select address bit SA1 be the decode gates circuit 134 of the situation of H level, and detects and select address bit SA0, SA1 to be the decode gates circuit 136 of the situation of H level simultaneously.

Output 114 comprises: detectable signal BLKSEL, BOP is that H level and signal BOOTE are the gate circuit 138 of the situation of L level simultaneously, accept output and the output of decoding gate circuit 130 and the OR circuit 140 that signal BAH0 is exported of gate circuit 138, accept output and the output of decoding gate circuit 132 and the OR circuit 142 that signal BAH1 is exported of gate circuit 138, accept output and the output of decoding gate circuit 134 and the OR circuit 144 that signal BAH2 is exported of gate circuit 138, and output and the output of decoding gate circuit 136 and the OR circuit 146 that signal BAH3 is exported of accepting gate circuit 138.

When signal BOOTE was the H level, the operation of horizontal block selection circuit 66 shown in Figure 8 and traditional horizontal block selection circuit were identical.When signal BOOTE is L level and signal BLKSEL when being the L level, laterally the operation of block selection circuit 66 is also identical with traditional horizontal block selection circuit.

At signal BOOTE is L level and signal BLKSEL when being the H level, no matter address bit A12, A13 are L level or H level, signal BAH0, BAH1, BAH2, BAH3 become the H level simultaneously, select when carrying out four transversely arranged storage blocks.At this moment, in vertical block selection circuit of Fig. 7, no matter address bit A14 is L level or H level, signal BAVS0, BAVS1 become the H level simultaneously, select when carrying out longitudinally two storage blocks, therefore, 8 storage blocks such as many storage blocks of result B000～B007 are selected.

With reference to Fig. 9, just in the flash memory of the embodiment of the invention 1 erase operation as the storage block unit of feature of the present invention is described.

In batch mode carry out the feature that memory block erasing is a flash memory.But, in the erase operation process, storage unit for whole storage block applies pulse in batches, be meant that the storage block among the step S2 writes in batch, the storage block of carrying out in step S4 is applying of erasing pulse 1 in batch, the storage block of carrying out in step S5 is soft in batch to be write, and the storage block of carrying out in step S7 applying of erasing pulse 2 in batch.In addition, so-called storage block is soft in batch to be write, and is meant than what carry out in step S2 to write shorter more weak the writing in batch that maybe suppresses the pulse voltage that applies lower of pulse application time.

Among the present invention, during four steps such as execution in step S2, S4, S5, S7, the storage block B000～B007 of 8 4k words can be selected simultaneously with vertical block selection circuit shown in Figure 7 64 and horizontal block selection circuit 66 shown in Figure 8.In these four steps, 8 4k word storage blocks can be handled as 1 main memory block (32k word storage block).

During the operating process of key diagram 9, during from outside input erasing instruction and corresponding address, in step S1, begin erase operation in order.In step S2, indicate: to becoming writing in batch of the storage block of wiping object.Internal controller 8 is set to the H level with signal BLKSEL when execution in step S2.Thereby select when carrying out a plurality of storage block, therefore, be set at the occasion of not using the 4k word, the storage block B000 of Fig. 1～B007 is selected simultaneously and applied in batches and write pulse.

Sort signal BLKSEL only supplies with in batches on the storage unit of erase block memory in the step of pulse and just is set to the H level.In other words, when other step S4 outside the execution in step S2, S5, S7, be set at the H level, other occasion is set at the L level.

Then enter step S3 execution and wipe verification 1.Whether the threshold voltage of wiping verification 1 and be the memory transistor of the storage block of confirming appointment becomes the operation corresponding to the threshold voltage of predetermined erase status.When not reaching certain erase status, to wipe verification failure (Fail) and enter step S4, storage block erasing pulse in batch is applied to and wipes on the object storage piece.Applying when finishing of erasing pulse among the step S4 enters step S3 execution once more and wipes verification 1.

In step S3, wipe verification 1 and enter step S5 for by (Pass) time, and carry out that storage block is soft in batch to be write.Enter step S6 execution then and wipe verification 2.When wiping verification 2 imperfect tense, enter step S7 to selecting storage block to supply with storage block erasing pulse 2 in batch.Enter step S6 then, carry out once more and wipe verification 2.

As in step S6, wiping verification 2, then in step S8, carry out the mistake that detected erase status and wipe verification for passing through.What is called is crossed to wipe and is meant: owing to applying of erasing pulse, the threshold voltage of memory transistor surpasses the variation of preset range.

Wiped when detecting, and crossed when wiping the verification failure, in step S9, carried out wiping recovery operation.The check of carrying out the lower limit of threshold voltage vt h then in step S10 is verification, when being failure as if this result, returns step S9.If among the step S10 check results for by the time, in step S8, carried out wiping verification once more.In step S8, if this result for by the time, enter the EO of step S11 memory block erasing.

The variation of switching signal generation circuit

With reference to Figure 10, switching signal generation circuit 10A comprises: the resistance 156 that connects between pad 152 that is supplied to signal #BOOT and node N3, accept power-on-reset signal POR and carry out anti-phase phase inverter 154, connection and its grid are accepted the P type channel MOS transistor 158 of the output of phase inverter 154 between power supply node and node N3, and the electric capacity 160 that connects between power supply node and node N3.

Switching signal generation circuit 10A also comprises: input end is connected the phase inverter 164 that node N3 and output terminal are connected node N4, the P type channel MOS transistor 162 that connection and its grid are connected with node N4 between power supply node and node N3, the electric capacity 166 that between node N4 and ground connection node, connects, input end is connected the phase inverter 168 of node N4, and accepts the output of phase inverter 168 and the phase inverter 170 of the anti-phase BOOTE of output signal then in addition.

With reference to Figure 11, when being chosen on the lead-in wire that is supplied to earthing potential connection pads 152 by wire bonds, signal #BOOT is set at the L level, and correspondingly signal BOOTE is set at the H level.

On the other hand, when pad 152 being connected to the lead-in wire of accepting power supply potential with lead, or be in open circuit not with the state that is connected of lead-in wire under, signal BOOTE is set at the L level.Also can so change switching signal generation circuit 10.

With reference to Figure 12, switching signal generation circuit 10B comprises: accept power-on-reset signal POR and in addition anti-phase phase inverter 172, between power supply node and node N5, connect, its grid accepts the P type channel MOS transistor 174 of the output of phase inverter 172, the fuse element 176 that between node N5 and node N6, connects, can cut off by laser beam, and between node N6 and ground connection node, connect, its grid accepts the N type channel MOS transistor 178 of the output of phase inverter 172.

Switching signal generation circuit 10B also comprises: input end is connected the phase inverter 182 that node N5 and output terminal are connected node N7, the P type channel MOS transistor 174 that between power supply node and node N5, connects, its grid is connected with node N7, accept the output of phase inverter 172 and in addition anti-phase phase inverter 184, accept the NOR circuit 186 of the output of the output of phase inverter 182 and phase inverter 184, accept the output of NOR circuit 186 and in addition anti-phase phase inverter 188, and accept the output of phase inverter 188 and the phase inverter 190 of the anti-phase BOOTE of output signal then.

With reference to Figure 12, Figure 13, when fuse element 176 was cut off by laser beam, node N5 kept the H level and node N7 becomes the L level.Then, after power-on-reset was disengaged, the output of phase inverter 184 also became the L level.Signal BOOTE in order to switching controls is set to the H level like this.

On the other hand, when fuse element 176 was in conducting state, if power-on-reset is disengaged, then node N5 was set at the L level, and its result node N7 is set at the H level.The output of NOR circuit 186 becomes the L level like this, therefore, is set at the L level in order to the signal BOOTE that switches.

When having bad storage unit in the such semiconductor storage of Nonvolatile semiconductor memory device, often be provided with the operation of cutting off fuse element for replacing with redundant storage unit.Therefore, in this cut-out operation,, then need not to use special device also can change the setting of switching signal if cut off the fuse element of switching signal generation circuit.

With reference to Figure 14, switching signal generation circuit 10C comprises: accept power-on-reset signal POR and in addition anti-phase phase inverter 192, between power supply node and node N8, connect, its grid is accepted the P type channel MOS transistor 196 of the output of phase inverter 192, the switch 198 that node N8 and the power supply potential HVCC higher than common power current potential are connected with node N9 selectively, the memory transistor 200 that between node N9 and node N10, connects, the switch 202 that between node N10 and ground connection node, connects, and in order to the switch 194 of the control grid of control store transistor 200.

Memory transistor 200 has the structure identical with the memory transistor that storage array comprised of Nonvolatile semiconductor memory device of the present invention.Therefore, need not to increase new operation, can memory transistor 200 be located at the inside of switching signal generation circuit 10C by the change layout.Switch 198,194,202, in predetermined test pattern according to erasing instruction or programmed instruction, the control grid of Control Node N9, node N10 and memory transistor 200 and being provided with.In this predetermined test pattern, set the maintenance content of the floating gate of memory transistor 200.

After the memory contents of setting memory transistor 200, switch 194 is with the control grid of the output supply memory transistor 200 of phase inverter 192, and switch 198 connected node N8 and node N9, and switch 202 is connected to the ground connection node with node N10.

Switching signal generation circuit 10C also comprises: input end is connected the phase inverter 206 that node N8 and output terminal are connected node N10, the P type channel MOS transistor 204 that between power supply node and node N8, connects, its grid is connected with node N10, accept the output of phase inverter 192 and in addition anti-phase phase inverter 208, accept the NOR circuit 210 of the output of the output of phase inverter 206 and phase inverter 208, accept the output of NOR circuit 210 and in addition anti-phase phase inverter 212, and accept the output of phase inverter 212 and the phase inverter 214 of the anti-phase BOOTE of output signal then.

With reference to Figure 14, Figure 15, when the threshold voltage vt h of memory transistor 200 was higher than predetermined voltage, even the output of phase inverter 192 is activated, memory transistor 200 also became nonconducting state.Therefore, become with Figure 12 in the state same state of fuse element 176 when being cut off, and therewith correspondingly signal BOOTE be set to the H level.

On the other hand, when the threshold voltage vt h of memory transistor 200 is lower than predetermined value, if the output of phase inverter 192 becomes the H level, then memory transistor 200 conductings, node N9 is connected with node N10.Therefore, same state when becoming fuse element 176 conductings in the circuit with Figure 12, signal BOOTE is set to the L level.

Like this, owing to adopted the technological process of making nonvolatile memory cell among the present invention, even be setting signal BOOTE, and the same memory transistor of use and nonvolatile memory cell also need not increase manufacturing process, and signal well can switch.

The variation of embodiment 1

In above embodiment, just the structure of selecting to wipe a plurality of storage blocks simultaneously with indication once by the storage block in the preposition demoder 18 at Fig. 1 when applying a plurality of simultaneous fixed pulse is illustrated, but in internal controller, carry out wiping of a plurality of storage blocks successively according to indication once, can carry out operation same when the outside is seen from the outside.

Figure 16 is the block scheme in order to the structure of the Nonvolatile semiconductor memory device of the variation of explanation embodiment 1.

With reference to Figure 16, Nonvolatile semiconductor memory device 221 is replaced the control section 2 in the structure of Nonvolatile semiconductor memory device 1 illustrated in fig. 1 by control section 2A.Control section 2A is provided with internal controller 8A and preposition demoder 18A, replaces internal controller 8 and preposition demoder 18 in the structure of control section 2 of Fig. 1 respectively.The structure of the Nonvolatile semiconductor memory device 221 of other parts is identical with Nonvolatile semiconductor memory device 1 shown in Figure 1, therefore not repeat specification.

Preposition demoder 18A carry out with Figure 27 in traditional same operation of storage block selection operation of illustrating.

With reference to Figure 17, internal controller 8A from the outside by control signal accept predetermined storage block wipe indication the time, in step S21, begin erase operation.

In step S22, indication writes in batch to becoming the storage block of wiping object.Then, enter step S23 execution and wipe verification 1.Whether the threshold voltage of wiping verification 1 and be the memory transistor of the storage block of confirming appointment becomes the operation corresponding to the threshold voltage of predetermined erase status.When not reaching certain erase status, to wipe the verification failure and enter step S24, storage block erasing pulse in batch is applied to and wipes on the object storage piece.As if the end that applies of the erasing pulse among the step S24, enter step S23 execution once more and wipe verification 1.

In step S23, wipe verification 1 for by the time, enter step S25 and carry out that storage block is soft in batch to be write.Enter step S26 execution then and wipe verification 2.Do not finish the occasion of wiping verification 2, entering step S27, to selecting storage block to supply with storage block erasing pulse 2 in batch.Entering step S26 then carries out once more and wipes verification 2.

In step S26, wipe verification 2 for by the time, in step S28, detected the mistake of erase status and wiped verification.

Detected and wiped, and promptly crossed and wipe when being verified as failure, in step S29, carried out wiping recovery operation.Then, the check of carrying out the lower limit of threshold voltage vt h in step S30 is verification, if this result then returns step S29 for failure.

In step S30 if check results for passing through, then in step S28, carried out wiping verification once more.In step S28 if the result is for by then entering step S31.

In step S31, the signal BOOTE that part produces takes place by switching signal in check.If signal BOOTE is the H level, then meaning needs bootstrap block, therefore, only wipes the storage block of initial appointment and enters step S34 and finish erase operation.

On the other hand, if signal BOOTE is the L level, then meaning does not need bootstrap block, and therefore, the storage block B000 of 4k word～B007 becomes the object of wiping in batch.Therefore, enter step S32, and judge that whether the storage block of wiping end this moment is the final storage block that becomes in the storage block of the object of wiping in batch.

When being not final storage block, enter step S33, wipe object and change to next storage block.When the storage block of for example just having wiped is storage block B000, wipes object and change to next storage block B001.And then enter step S22 and carry out wiping in batch of the storage block become object.

In step S32,, promptly when the storage block that storage block B000 wipes successively and finish to wipe this moment is B007, enter step S34 if detect storage block when being final storage block.And, enter step S34 too and finish erase operation when if this moment, the storage block of wiping was not the storage block of 4k word but storage block B008～B022.

Even do not select when not carrying out a plurality of storage block like this, can in controller, pack into yet and a plurality of storage blocks be carried out the sequential of wiping of block-by-block according to once wiping indication.

Embodiment 2

Among the embodiment 1, the nonvolatile memory that the occasion of the storage block B000～B007 of the 4k word of individually wiping Fig. 1 and the occasion of wiping is in batches switched with regard to can be enough predetermined setting is described.At this moment for the continuity of storage array storage block B100 need be set, but it is the zone that often is not used.Need not the occasion of 4k word storage block, can constitute preposition demoder, select obsolete traditionally storage block B100 to replace storage block B000～B007.

Figure 18 is the block scheme of the structure of the preposition demoder 18B among the expression embodiment 2.

With reference to Figure 18, preposition demoder 18B is in the structure of preposition demoder 18 illustrated in fig. 6, with BOP circuit 62B taking place and replaced NOR circuit 62, replaced vertical block selection circuit 64 with vertical block selection circuit 64B, has replaced horizontal block selection circuit 66 with horizontal block selection circuit 66B.The structure of the preposition demoder 18B of other parts is identical with preposition demoder illustrated in fig. 6 18, therefore not repeat specification.

Circuit 62B takes place and comprises in BOP: accept the four-input terminal NOR circuit 222 of address bit A15, A16, A17, A18, and accept the output of NOR circuit 222 and the AND circuit 223 of signal BOOTE and output signal BOP.

In embodiment 1, sort signal BOP is when importing corresponding to the address of obsolete storage block B100, the operation of preposition demoder is switched to the signal of the operation of selecting storage block B000～B007.In structure shown in Figure 180, when signal BOOTE is the L level, signal BOP often by deactivation to the L level, storage block B000～B007 can be not selected, and replace the storage block B100 that selects the 32k word.Therefore, by the outside give with wipe that the storage array that illustrates among indication and Figure 30 700 is the same to be finished with 16 times.

With reference to Figure 19, vertically block selection circuit 64B contains address decoder part 82A, replaces the address decoder part 82 in the structure of vertical block selection circuit 64 illustrated in fig. 7.The structure of vertical block selection circuit 64B of other parts is identical with vertical block selection circuit illustrated in fig. 7 64, therefore not repeat specification.

Address decoder part 82A contains: the gate circuit 224 of address bit A14 is anti-phase and output signal BAVS0 when signal BOP is activated as the H level, and the AND circuit 226 of acknowledge(ment) signal BOP and address bit A14 and output signal BAVS1.

At signal BOP by deactivation during to the L level, signal BAVS0, the BAVS1 that selects vertical storage block simultaneously by deactivation to the L level, storage block B000～B007 becomes non-selected state.On the other hand, when signal BOP was activated to the H level, according to address bit A14, any one party was activated to the H level among signal BAVS0, the BAVS1, can select any among storage block B000～B007.

With reference to Figure 20, laterally block selection circuit 66B contains address selection part 110 and address decoder part 112.Because address selection part 110 is illustrated in Fig. 8 with the structure of address decoder part 112, so not repeat specification.In addition, different with Fig. 8 is in horizontal block selection circuit 66B, by decode gates circuit 130,132,134,136 difference output signal BAH0, BAH1, BAH2, the BAH3 of address decoder part 112.

The signal BOOTE of Figure 18 is the signal that determines whether to have the 4k block identical with embodiment 1.In embodiment 2, also can adopt switching

signal generation circuit

10,10A, 10B, 10C to produce this signal as explanation among the embodiment 1.Take place by by the direct control signal BOP of signal BOOTE, can when signal BOP is the H level, select storage block B000～B007 among the circuit 62B at the BOP of Figure 18, and when signal BOP is the L level, select storage block B100.Thus, can realize having the flash memory of 4k word storage block and the flash memory that does not have 4k word storage block simultaneously with a kind of storer.

In the embodiment of above explanation, 8 4k blocks are the little sides (bottom side) in the address only, but they also can carry out during a big side (top side) in the address sample with blocked operation.And, the storage block in 8 4k blocks also can all be set in bottom and both sides, top.

Application examples

Figure 21 is the diagrammatic sketch that adopts the so-called dual boot type storage array that 4k word storage block all is set in the bottom and the both sides, top of address area of the present invention in order to explanation.

With reference to Figure 21, storage array 300 comprises: corresponding to the storage block B000～B007 of bottom-boot, and corresponding to the storage block B008～B021 of main memory block, and corresponding to the storage block B022～B029 of top guiding.

Why requiring top guiding and bottom-boot, is because in initial which zone of access there is dual mode in the difference because of cpu type at the CPU that system adorned that uses Nonvolatile semiconductor memory device.

If the system that uses is during corresponding to bottom-boot, storage block B000～B007 is made as the structure that can individually wipe, and can indicate the structure of erase block memory B022～B029 in batch as wiping of explanation among the embodiment 1 with one, perhaps can switch, replace the selection of storage block B022～B029 to select storage block B200.

When if the system that uses guides corresponding to the top, storage block B022～B029 is made as the structure that can individually wipe, can be as explanation among the embodiment 1, wipe with one and to indicate the structure of erase block memory B000～B007 in batch, perhaps can switch, replace the selection of storage block B000～B007 to select storage block B100.

But as on the storage array of dual boot, adopting storage block choice structure of the present invention, then no matter system is the occasion of the occasion of bottom-boot or top guiding or does not have leading type and all produce a kind of chip in advance, can be as required to come corresponding various structures by the change of the memory contents of the cut-out of the change of wire-bonded or fuse or the nonvolatile memory cell be scheduled to.

Make up the occasion that two such nonvolatile memorys corresponding to dual boot use, in the conventional art, because there is the tiny storage block of so-called 4k word in the middle body in the address, there is awkward problem, be used in combination but nonvolatile memory of the present invention is switched to top leading type, bottom-boot type, no leading type, thereby even also can realize various types of nonvolatile memorys in the occasion of two chip structures.

With reference to Figure 22, storer 302 is realized by combination storage array 304 and storage array 306.Storage array 304 guides by the 300 corresponding ends of storage array that make dual boot type illustrated in fig. 21 and realizes, and storage array 306 is by making storage array 300 corresponding top guiding for using.Therefore, In the view of the user, the storage block of the tiny 4k word on the middle body of address is non-existent, thereby uses easily.

The diagrammatic sketch of the structure of the realization bottom-boot when Figure 23 is explanation combination two chips.

With reference to Figure 23, storer 308 is realized by combination storage array 310 and storage array 312.Storage array 310 is realized by the storage array 300 corresponding bottom-boots that make dual boot type illustrated in fig. 21, and storage array 312 uses by making storage array 300 corresponding no leading types.This occasion, In the view of the user, on the middle body or top of address, the storage block of tiny 4k word is non-existent, thereby uses easily.

The diagrammatic sketch of the structure of the realization top guiding when Figure 24 is explanation combination two chips.

With reference to Figure 24, storer 314 is realized by combination storage array 316 and storage array 318.Storage array 316 is realized by the storage array 300 corresponding no leading types that make dual boot type illustrated in fig. 21, and storage array 318 uses by storage array 300 corresponding tops are guided.This occasion, In the view of the user, middle body or bottom in the address, the storage block of tiny 4k word is non-existent, thereby uses easily.

Realization when Figure 25 is explanation combination two chips does not have the diagrammatic sketch of the structure of leading type.

With reference to Figure 25, storer 320 is realized by combination storage array 322 and storage array 324.Storage array 322,324 is realized by the storage array 300 corresponding no leading types that make dual boot type illustrated in fig. 21.This occasion, In the view of the user, on the top of address, middle body, bottom, the storage block of tiny 4k word is non-existent, thereby uses easily.

More than the present invention has been done detailed description, but this only is an illustration, does not limit the present invention, is understood that the spirit and scope of the present invention are stipulated by appending claims.

Claims

1. Nonvolatile semiconductor memory device wherein is provided with:

A plurality of memory cell matrix shapes are arranged the first basic storage block that forms, and it has first memory space that becomes the unit of wiping in batch;

With the described first basic storage block separate be provided with in addition, each have a plurality of memory cell matrix shapes and arrange a plurality of second basic storage block that forms, they have second memory space littler than described first memory space separately, and the summation of memory space is identical with described first memory space; And

Wipe control circuit, it is wiped first operation of a storage block in the described a plurality of second basic storage block according to the switching signal switching according to erasing instruction and wipes second operation of the described second basic storage block according to described erasing instruction in batches.

2. Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:

At least one storage block in the described a plurality of second basic storage block is the bootstrap block of reading when the startup of the system that uses described Nonvolatile semiconductor memory device.

3. Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:

At least one storage block in the described a plurality of second basic storage block is the storage block that writes than the high data of data that write the described first basic storage block in order to will rewrite possibility.

4. Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:

Also be provided with the lead-in wire of supplying with predetermined fixed potential, and in order to wipe the pad that control circuit switches the polarity of described switching signal with respect to described;

The described control circuit of wiping contains when engaging described lead-in wire and described pad, described switching signal is set in the switching signal generation circuit of first polarity.

5. Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:

The described control circuit of wiping contains the switching signal generation circuit of exporting described switching signal;

Described switching signal generation circuit contains, in order to determine the fuse element of described switching signal.

6. Nonvolatile semiconductor memory device as claimed in claim 5 is characterized in that:

Described fuse element is to connect the fuse element that decides described switching signal according to having or not.

7. Nonvolatile semiconductor memory device as claimed in claim 5 is characterized in that:

Described fuse element has the identical structure of nonvolatile memory cell that is comprised with described first, second basic storage block.

8. Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:

The described control circuit of wiping in the occasion of carrying out described second operation, when in batches a plurality of nonvolatile memory cells being supplied with pulse, is concentrated and is selected the described a plurality of second basic storage block.

9. Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:

The described control circuit of wiping in the occasion of carrying out described second operation, is selected the described a plurality of second basic storage block successively, the basic storage block of having selected wipe end after, begin the erase operation of next basic storage block.

10. Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:

The described a plurality of second basic storage block and the described first basic storage block are dispensed on predetermined address area;

The described a plurality of second basic storage block is configured in the upper side in described predetermined address area.

11. Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:

The described a plurality of second basic storage block is configured in the most the next side in described predetermined address area.

12. Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:

Also comprise have separately the memory space littler than the described first basic storage block, constitute a plurality of the 3rd basic storage block of erase unit in batch;

The described a plurality of the 3rd basic storage block, the described a plurality of second basic storage block and the described first basic storage block are dispensed on predetermined address area,

Any one party in the described a plurality of second basic storage block and the described a plurality of the 3rd basic storage block is configured in the upper side in the described predetermined address area, and the opposing party is configured in the most the next side in the described predetermined address area.

13. a Nonvolatile semiconductor memory device wherein is provided with:

A plurality of memory cell matrix shapes are arranged the first basic storage block that forms, and it has and constitutes first memory space of erase unit in batch;

Wipe control circuit, it is wiped first operation of a storage block in the described a plurality of second basic storage block according to the switching signal switching according to erasing instruction and wipes second operation of the described first basic storage block according to described erasing instruction.

14. Nonvolatile semiconductor memory device as claimed in claim 13 is characterized in that:

Also comprise the lead-in wire of supplying with predetermined fixed potential, and in order to wipe the pad that control circuit switches the polarity of described switching signal with respect to described;

15. Nonvolatile semiconductor memory device as claimed in claim 13 is characterized in that: