CN100399665C - Voltage source electrostatic discharge protective circuit - Google Patents
Voltage source electrostatic discharge protective circuit Download PDFInfo
- Publication number
- CN100399665C CN100399665C CNB200310102218XA CN200310102218A CN100399665C CN 100399665 C CN100399665 C CN 100399665C CN B200310102218X A CNB200310102218X A CN B200310102218XA CN 200310102218 A CN200310102218 A CN 200310102218A CN 100399665 C CN100399665 C CN 100399665C
- Authority
- CN
- China
- Prior art keywords
- district
- implanting ions
- ions zone
- zone
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000001681 protective effect Effects 0.000 title abstract 2
- 150000002500 ions Chemical class 0.000 claims description 95
- 230000004224 protection Effects 0.000 claims description 40
- 230000003068 static effect Effects 0.000 claims description 30
- 238000002955 isolation Methods 0.000 claims description 22
- 238000005421 electrostatic potential Methods 0.000 claims 2
- 238000001514 detection method Methods 0.000 abstract 3
- 210000001503 joint Anatomy 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010009 beating Methods 0.000 description 3
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 1
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 1
- 230000001149 cognitive effect Effects 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention discloses an electrostatic discharge protective circuit for mixed voltage sources, which comprises a first double-carrier transistor group, a second double-carrier transistor group, a first detection circuit and a second detection circuit, wherein each of the double-carrier transistor groups is formed by the butt joint of two NPN double-carrier transistors, the NPN double-carrier transistors in the first and the second double-carrier transistor groups positioned between mixed voltage sources are controlled to be switched on or off by the first and the second detection circuits also positioned between the mixed voltage sources to block the mixed voltage sources and eliminate heavy current generated by electrostatic discharge between the mixed voltage sources.
Description
Technical field
The present invention relates to a kind of ESD protection circuit, a kind of ESD protection circuit of voltage source is particularly arranged.
Background technology
ESD protection circuit often appears at IC interior; because the relation of its big voltage of static discharge; therefore; must have ESD protection circuit in the lsi internal circuit, lsi internal circuit be caused damage to avoid static discharge (Electro Static Discharge).
Yet; differentiation along with demand; bring into use different voltage sources between the internal circuit of integrated circuit; also therefore; ESD protection circuit is except being arranged in the lsi internal circuit between signal I/O end weld pad; more necessary being arranged in the integrated circuit between different voltage sources, and the present invention proposes at this.
Please refer to Fig. 1, Fig. 1 is the ESD protection circuit schematic diagram of known voltage source.In Fig. 1, comprise internal circuit 110 and internal circuit 120 in the integrated circuit 100.Wherein, internal circuit 110 and internal circuit 120 are to use different voltage source V DD1 and voltage source V DD2 respectively, and the signal 121 of internal circuit 110 can input in the internal circuit 120 via reverser 123,125.
And the anti-system of the static discharge between two internal circuits, 110,120 its voltage source V DD1, VDD2 is then used the electrostatic discharge clamp 130,140 that is distributed in around the internal circuit 110,120 and the ESD protection circuit 150,160 of voltage.
Lift an example explanation, when producing static discharge between voltage source V DD1 and earth terminal VSS2, the formed big electric current of potential difference can flow to earth terminal VSS2 by voltage source V DD1 between voltage source V DD1 and earth terminal VSS2, or flows to voltage source V DD1 by earth terminal VSS2.And importing internal circuit 110,120 for fear of the big electric current between voltage source V DD1 and earth terminal VSS2, this clamp circuit 130,140 can form short circuit.Therefore, the big electric current I that is produced in voltage source V DD1
1Can shunt the diode 151,153, the clamp circuit 130 that in ESD protection circuit 150, are connected in series along path P 1 and flow into earth terminal VSS2, and flow into earth terminal VSS2 along the substrate resistance of path P 2 in clamp circuit 140, ESD protection circuit 160.
Simultaneously, clamp circuit 130,140 is in big electric current I
1After flowing through, potential difference brought between potential difference between also that voltage source V DD1 is corresponding with it earth terminal VSS1 and voltage source V DD2 and its corresponding earth terminal VSS2 is (when referring to two internal circuits, 110,120 operate as normal, between the voltage source V DD1 earth terminal VSS1 corresponding with it and the potential difference between voltage source V DD2 and its corresponding earth terminal VSS2) under normal circumstances.In like manner; when producing static discharge between voltage source V DD2 and earth terminal VSS1; the formed big electric current of potential difference still can import earth terminal VSS1 by voltage source V DD2 by ESD protection circuit 150,160 and electrostatic discharge clamp 130,140 between voltage source V DD2 and earth terminal VSS1.And clamp circuit 130,140 is after big electric current flows through, potential difference brought between potential difference between the earth terminal VSS1 that voltage source V DD1 is corresponding with it and voltage source V DD2 and its corresponding earth terminal VSS2 under normal circumstances, so the big electric current that is produced during static discharge between internal circuit 110,120 liang of voltage source V DD1, VDD2 can be got rid of smoothly, unlikely flowing in the internal circuit 110,120, and 110,120 voltage levels that use respectively of internal circuit are still kept normally.
In addition; when this ESD protection circuit 150 of 110,120 of 100 liang of internal circuits of integrated circuit not only must produce static discharge between voltage source V DD1, VDD2 and earth terminal VSS1, VSS2; effectively the big electric current that static discharge produced is effectively got rid of; more necessary when between voltage source V DD1, VDD2 and earth terminal VSS1, VSS2, not producing static discharge (when referring to two internal circuits, 110,120 operate as normal); effectively isolated two voltage source V DD1, VDD2 are so that two internal circuits 110,120 can stably use its voltage source V DD1, VDD2 separately.Therefore, this ESD protection circuit 150 is more necessary has certain starting voltage (threshold voltage) with effectively isolated two voltage source V DD1, VDD2.
That is to say that two serial connection diodes 151,153 must could effectively completely cut off two voltage source V DD1, VDD2 greater than the pressure reduction between voltage source V DD1 and voltage source V DD2 in the cross-pressure that is produced along partially the time in the ESD protection circuit 150.With voltage source V DD1 is that 1.8V, voltage source V DD2 are 3.3 to be example, and serial connection diode 151,153 cross-pressures that produced just must be greater than 1.5V along partially the time.
In addition, when big more as if the voltage difference between voltage source V DD1 and voltage source V DD2, then in the ESD protection circuit 150, the number of diode serial connection also must improve relatively, with effective obstruct voltage source V DD1 and voltage source V DD2.
Please refer to Fig. 2, Fig. 2 is to use the schematic diagram of the another kind of known ESD protection circuit of mixed-voltage source integrated circuit.In Fig. 2, the voltage difference when between voltage source V DD3, VDD4 is bigger, and then the serial connection of the diode in the ESD protection circuit 230,240 number becomes more.
Between different voltage sources, the diode in the ESD protection circuit is all with PMOS transistor or nmos pass transistor (end illustrates) equivalence and forms in integrated circuit.The shortcoming that diode produced of known ESD protection circuit.For instance:
1. diode has higher leakage current and lower breakdown voltage, can not effectively block two voltage sources independently.
2. the ability of diode drive current is not fine, can not rapidly the electric current that static discharge produced be got rid of rapidly.
3. the parasitic capacitance that produced between two independent current sources of diode is bigger, is coupled to the signal between two internal circuits easily.
Summary of the invention
Main purpose of the present invention provides a kind of ESD protection circuit of voltage source; have lower leakage current, higher breakdown voltage; and has higher current driving ability; and between AC-battery power source, have lower parasitic capacitance, and the big electric current that static discharge produced between voltage source can be got rid of rapidly.
The ESD protection circuit of voltage source of the present invention comprises: the first bipolar transistor group, the second bipolar transistor group, first testing circuit and second testing circuit.Wherein, the first bipolar transistor group is made up of first bipolar transistor and second bipolar transistor.And wherein, the emitter of the collector electrode of first bipolar transistor and second bipolar transistor couples one first power supply in first node.The collector electrode that the emitter of first bipolar transistor couples with second bipolar transistor then couples a second source in Section Point.
The second bipolar transistor group then is made up of the 3rd bipolar transistor and the 4th bipolar transistor.And wherein, the emitter of the collector electrode of the 3rd bipolar transistor and the 4th bipolar transistor couples one first earth terminal in the 3rd node.The collector electrode of the emitter of the 3rd bipolar transistor and the 4th bipolar transistor couples one second earth terminal in the 4th node.
As for first testing circuit, it has first link, second link and trigger end, and wherein, first link of first testing circuit couples first node, second link of first testing circuit couples the 3rd node, and the trigger end of first testing circuit couples the base stage of the base stage of first bipolar transistor and the 3rd bipolar transistor in the 5th node.
And second testing circuit, it has first link, second link and trigger end equally, first link of second testing circuit couples Section Point, second link of first testing circuit couples the 4th node, and the trigger end of second testing circuit couples the base stage of the base stage of second bipolar transistor and the 4th bipolar transistor in the 6th node.
In order feature of the present invention, purpose and function to be had further cognitive and to understand, the present invention is described in detail with instantiation below in conjunction with accompanying drawing.
Description of drawings
Fig. 1 is to use the known ESD protection circuit schematic diagram of the integrated circuit of voltage source;
Fig. 2 is to use the schematic diagram of the another kind of known ESD protection circuit of voltage source integrated circuit;
Fig. 3 is the schematic diagram of ESD protection circuit of the voltage source of preferred embodiment of the present invention;
Fig. 4 A is the schematic diagram of the first transistor group 310 structures of preferred embodiment of the present invention;
Fig. 4 B is the top view of Fig. 4 A the first transistor group 310 structures.
Fig. 5 is that the present invention uses the NPN bipolar transistor to be connected in series the comparison diagram that diode is led electric current off with known use; And
Fig. 6 is the comparison sheet of the parasitic capacitance that forms between NPN bipolar transistor and diode and two voltage sources.
Description of reference numerals: 100,300 integrated circuits; 110,120,210,220,301,302 internal circuits; 121 signals; 123,125,333,343 reversers; 130,140,330,340 electrostatic discharge clamps; 150,160,230,240 ESD protection circuits; 151,153,155 diodes; VDD1, VDD2, VDD3, VDD4 voltage source; VSS1, VSS2, VSS3, VSS4 earth terminal; 310,320 transistor groups; 335,345 testing circuits; 311,312,321,322NPN bipolar transistor; 331,341 resistance; 332,342 electric capacity; 334,344NMOS transistor; I
1, I
2Electric current; The 430P district; 477,437P district; 431,471 deep layer N districts; 435,439,475,479N district; 441,445,449,461,465,469N+ implanting ions zone; 443,447,463,467P+ implanting ions zone; 451,452,453,454 isolation structures.
Embodiment
See also Fig. 3, Fig. 3 is the ESD protection circuit schematic diagram of the voltage source of preferred embodiment of the present invention.In Fig. 3, the electrostatic discharge clamp 330,340 of integrated circuit 300 protections two internal circuits 301,302 and the ESD protection circuit 310,320 of protecting this voltage source.Wherein, this electrostatic discharge clamp 330 comprises an electrostatic discharge circuit 334 and one first testing circuit 335; This electrostatic discharge clamp 340 comprises an electrostatic discharge circuit 344 and one second testing circuit 345.The ESD protection circuit of this voltage source comprises the first transistor group 310, transistor seconds group 320, first testing circuit 335 and second testing circuit 345.
Wherein, the first transistor group 310 is made of two NPN bipolar transistors 311,312, and transistor seconds group 320 is made of two NPN bipolar transistors 321,322.And first testing circuit 335 mainly is made of resistance 331, electric capacity 332 and reverser 333, and second testing circuit 345 is made of resistance 341, electric capacity 342 and reverser 343.
Under normal circumstances, when two internal circuits 301,302 liang of voltage source V DD1, when there is no the static discharge generation between VDD2, resistance 331, electric capacity 332 and reverser 333 inputs couple jointly, its voltage can be subjected to electric capacity 332 equivalences approximately identical with voltage source V DD1 (being assumed to be 1.8 volts) for the influence magnitude of voltage that opens circuit maintains, therefore the voltage of high level will transfer low level and output (node 1 to via reverser 333, the output of this first testing circuit 335) to the gate of nmos pass transistor 334, and nmos pass transistor 334 gates are owing to accept the relation of low level voltage, nmos pass transistor 334 not conductings (OFF).
In like manner, resistance 341, electric capacity 342 and reverser 343 inputs couple jointly, its magnitude of voltage VDD2 identical (being assumed to be 3.3 volts) to the gate of nmos pass transistor 344, makes nmos pass transistor 344 not conductings through reverser 343 outputs (node 2, the i.e. output of this second testing circuit 345).
And simultaneously, the output of this first testing circuit 335 (node 1) couples bipolar transistor 311 base stages in the first transistor group 310 and bipolar transistor 321 base stages in the transistor seconds group 320, also makes this bipolar transistor 311 and bipolar transistor 321 not conductings because of the low level of node 1.
And the output of this second testing circuit 345 (node 2) couples bipolar transistor 312 base stages in the first transistor group 310 and bipolar transistor 322 base stages in the transistor seconds group 320, makes this bipolar transistor 312 and bipolar transistor 322 not conductings because of the low level of node 2.
The NPN contact structure of two bipolar transistors 311,312 between two voltage source V DD1, VDD2 will make this two bipolar transistor 311,312 have the characteristic of low-leakage current and high breakdown voltage.
Under normal circumstances, so the first bipolar transistor group 310 and the 320 neither conductings of the second bipolar transistor group are effectively isolated two voltage source V DD1, VDD2.
Under the static discharge situation of two voltage sources, promptly flow to earth terminal VSS2, or flow to voltage source V DD1, or flow to earth terminal VSS1, or flow to voltage source V DD2 by earth terminal VSS1 by voltage source V DD2 by earth terminal VSS2 by voltage source V DD1.
When static discharge is a positive big pulse when beating to earth terminal VSS2 by voltage source V DD1, the formed big electric current I of static discharge
1To flow to earth terminal VSS2 by voltage source V DD1.And simultaneously, electric capacity 342 in the electric capacity 332 in first testing circuit 335 and second testing circuit 345 forms short circuit, and couple the relation of earth terminal VSS1, VSS2 respectively because of electric capacity 332,334 1 ends, its voltage is drawn to reduce to low level voltage (being the accurate position of ground connection voltage), and be output as high levle voltage via reverser 333,343 respectively, promptly the voltage of node 1,2 is high levle voltage.The output of this testing circuit 335 (node 1) will trigger the bipolar transistor 321 in bipolar transistor 311 and the transistor seconds group 320 in the first transistor group 310.The output of this testing circuit 345 (node 2) will trigger the bipolar transistor 322 in bipolar transistor 312 and the transistor seconds group 320 in the first transistor group 310.
At static discharge is a positive big pulse when beating to earth terminal VSS2 by voltage source V DD1, the formed big electric current I of static discharge
1Shunting, and 1 flow to earth terminal VSS2 along the path respectively through bipolar transistor 311, nmos pass transistor 344, and 2 flow to earth terminal VSS2 through nmos pass transistor 334, bipolar transistor 321 along the path.
In like manner, when static discharge is that a positive big pulse is when beating to earth terminal VSS1 by voltage source V DD2, the formed big electric current of static discharge can and flow to earth terminal VSS1 through bipolar transistor 312, nmos pass transistor 334 respectively by voltage source V DD2 shunting, and flows to earth terminal VSS1 through nmos pass transistor 344, bipolar transistor 322.
In addition, between voltage source V DD1, VDD2, use NPN bipolar transistor 311,312,321,322 to have higher current driving ability, just lead the ability of electric current that static discharge forms off as the ESD protection circuit assembly.Please refer to Fig. 5, Fig. 5 is that the present invention uses the NPN bipolar transistor to be connected in series the comparison diagram that diode is led electric current off with known use.
In Fig. 5, be all 2 μ m * 2 μ m layout dimension, and under the identical base stage or gate voltage, when static discharge produced, single NPN bipolar transistor can the quickest generation electric current, and single diode takes second place, two serial connection diodes are the poorest.And the electric current that single NPN bipolar transistor is produced is the quickest tending towards stability also, and two serial connection diodes take second place, and single diode is the poorest.So the NPN bipolar transistor has preferable ability of leading static discharge off really.
In preferred embodiment of the present invention, the first transistor group 310 also can use the structure of CMOS three-field system journey to finish with the practical structures of transistor seconds group 320.Structure with the first transistor group 310 is an example, please refer to Fig. 4 A, and Fig. 4 A is the schematic diagram of the first transistor group 310 structures of preferred embodiment of the present invention.In Fig. 4 A, bipolar transistor 311 its structures in Fig. 3 the first transistor group 310 are: be embedded with deep layer N district 431 in the P district 430, and P district 430 end faces extend downward deep layer N district 431 end faces and also are embedded with N district 435, P district 437 and N district 439.Then N+ implanting ions zone 441, P+ implanting ions zone 443, N+ implanting ions zone 445, P+ implanting ions zone 447 and N+ implanting ions zone 449 near N district 435, P district 437 and N district 439 end faces.And N+ implanting ions zone 441, P+ implanting ions zone 443, N+ implanting ions zone 445, P+ implanting ions zone 447 and N+ implanting ions zone 449 parts are for using the isolation structure 451-454 that is partly imbedded by P district 430 top face to separate in twos.
Therefore, N+ implanting ions zone 445 is the collector electrode of bipolar transistor 311 and couples Fig. 3 voltage source V DD1, P+ implanting ions zone 443,447 is the base stage of bipolar transistor 311 and couples Fig. 3 node 1, and N+ implanting ions zone 441,449 is the emitter of bipolar transistor 311 and couple Fig. 3 voltage source V DD2.
When the formed electric current I of Fig. 3 static discharge
1When flowing to emitter by bipolar transistor 311 collector electrodes, electric current I
1Can 431 flow into N districts 435 through deep layer N district by P district 437, and by P district 437 through deep layer N district 431 inflow N districts 439.
Similarly, N+ implanting ions zone 465 is the collector electrode of Fig. 3 bipolar transistor 312 and couples Fig. 3 voltage source V DD2, P+ implanting ions zone 463,467 is the base stage of bipolar transistor 312 and couples Fig. 3 node 2, and N+ implanting ions zone 461,469 is the emitter of bipolar transistor 312 and couple Fig. 3 voltage source V DD1.And when the formed electric current I of Fig. 3 static discharge
2When flowing to emitter by bipolar transistor 312 collector electrodes, electric current I
2Can 471 flow into N districts 475 through deep layer N district by P district 477, and by P district 477 through deep layer N district 471 inflow N districts 479.
In addition, in preferred embodiment of the present invention, the formed circulus of three-field system journey also helps static discharge current I
1, I
2Lead off.Please refer to Fig. 4 B, Fig. 4 B is the top view of Fig. 4 A transistor 310 structures.In Fig. 4 B, the isolation structure 452,453 of Fig. 4 A forms a ring-type and is centered around around the N+ implanting ions zone 445.In the same manner, P+ implanting ions zone 443,447 be centered around isolation structure 452,453 ring-types that form around.Isolation structure 451,454 also forms ring-type and is centered around around the P+ implanting ions zone 445.N+ implanting ions zone 441,449 is same form ring-types and be centered around isolation structure 451,453 ring-types that form around.431 peripheries, deep layer N district also will be centered around N+ implanting ions zone 445 circuluses that form around.
Because the first transistor group 310 is the cause of circulus, first bipolar transistor 311 can flow I with static discharge
1, I
2Be radial by its base stage, collector electrode and emitter and lead off, therefore, it has the effect of well leading static discharge current off.
And under this three-field system journey structure, NPN bipolar transistor 311 or 312 formed parasitic capacitance between two voltage sources is also come for a short time than known diode.Please refer to Fig. 6, Fig. 6 is the comparison sheet of the parasitic capacitance that forms between NPN bipolar transistor and diode and two voltage sources.In Fig. 6, connecing the electric capacity that face produced with main P district 437 that produces the parasitic capacitance part and deep layer N district 431 in NPN bipolar transistor 331 structures is 6.80E-04 (F/m
2), connecing the electric capacity that face produces with the main N+ implanting ions zone that produces the parasitic capacitance part in the diode N+/PW structure and P district is 1.00E-03 (F/m
2), and with diode P+/NW structure in to connect the electric capacity that face produces be 1.12E-03 (F/m the main P+ implanting ions zone that produces the parasitic capacitance part and N district
2).
The unit parasitic capacitance that the NPN bipolar transistor is produced between two voltage sources is compared with the unit parasitic capacitance that diode is produced between two power supplys, and the unit parasitic capacitance that the NPN bipolar transistor is produced between two voltage sources is little many.
Comprehensively above-mentioned; ESD protection circuit between voltage source of the present invention will have lower leakage current, higher breakdown voltage; and has higher current driving ability; and lower parasitic capacitance; and effectively block outside the AC-battery power source; and the big electric current that static discharge produced between the mixed-voltage source can be got rid of rapidly, and the signal between the corresponding internal circuit in the AC-battery power source source that is not easy to be coupled.
The above only is preferred embodiment of the present invention, when can not with limit the scope of the invention.Promptly the equalization of doing according to claim of the present invention generally changes and modifies and will not lose main idea of the present invention place, does not also break away from the spirit and scope of the present invention, and the former capital should be considered as further enforcement of the present invention.
Claims (9)
1. the ESD protection circuit of a voltage source; in order to protect the static discharge of a potential circuit; this potential circuit comprises one first internal circuit, one second internal circuit, one first end points, one second end points, one the 3rd end points and one the 4th end points; described first end points, one second end points, one the 3rd end points and one the 4th end points receive one first operating voltage, one second operating voltage, one the 3rd operating voltage and one the 4th operating voltage respectively, and this device comprises:
One the first transistor group is coupled between this first end points and the 3rd end points;
One transistor seconds group is coupled between this second end points and the 4th end points;
One first testing circuit is electrically connected between this first end points and this second end points, is used for detecting between this first end points and this second end points whether electrostatic potential is arranged, and produces one first triggering signal;
One first electrostatic discharge circuit is electrically connected between this first end points and this second end points;
One second testing circuit is electrically connected between the 3rd end points and the 4th end points, is used for detecting between the 3rd end points and the 4th end points whether electrostatic potential is arranged, and produces one second triggering signal; And
One second electrostatic discharge circuit is electrically connected between the 3rd end points and the 4th end points;
Wherein,, make this first and second transistor group and this first electrostatic discharge circuit conducting, use allowing electrostatic induced current pass through according to this first triggering signal;
Wherein, make this first and second transistor group and this second electrostatic discharge circuit conducting, use allowing electrostatic induced current pass through according to this second triggering signal.
2. the ESD protection circuit of voltage source as claimed in claim 1, it is characterized in that: this first transistor group includes one first bipolar transistor and one second bipolar transistor.
3. the ESD protection circuit of voltage source as claimed in claim 2 is characterized in that: this first and this second bipolar transistor be the NPN bipolar transistor.
4. the ESD protection circuit of voltage source as claimed in claim 1, it is characterized in that: this transistor seconds group includes one the 3rd bipolar transistor and one the 4th bipolar transistor.
5. the ESD protection circuit of voltage source as claimed in claim 4, it is characterized in that: the 3rd and the 4th bipolar transistor is the NPN bipolar transistor.
6. the ESD protection circuit of voltage source as claimed in claim 1, it is characterized in that: this first testing circuit comprises:
One resistance;
One electric capacity is connected in series with this resistance; And
One reverser has an input and an output, and this input couples the tie point of this resistance and this electric capacity, and this output is in order to export this first triggering signal.
7. the ESD protection circuit of voltage source as claimed in claim 1 is characterized in that: this first or this second electrostatic discharge circuit be a nmos pass transistor.
8. the ESD protection circuit of voltage source as claimed in claim 2, it is characterized in that: the structure of this first bipolar transistor comprises:
One the one P district;
One first deep layer N district is embedded in bottom, a P district;
One the one N district is positioned at a P district, extends to this first deep layer N district end face in the side direction of a N district by a P district end face, and wherein, a N district also includes:
One the one N+ implanting ions zone is positioned at a N district, and a N+ implanting ions zone is in close proximity to the end face in a N district, and a N+ implanting ions zone couples second operating voltage;
One the 2nd N district is positioned at a P district, and the 2nd N district extends inwardly to this first deep layer N district end face by a P district end face with respect to the opposite side in a N district, wherein,
The 2nd N district also comprises one the 2nd N+ implanting ions zone, is positioned at the 2nd N district, and the 2nd N+ implanting ions zone is in close proximity to the end face in the 2nd N district, and the 2nd N+ implanting ions zone couples second operating voltage;
One the 2nd P district is positioned at a P district and adjacent a N district and the 2nd N district is arranged, and the 2nd P district extends inwardly to this first deep layer N district end face by a P district end face, and wherein, the 2nd P district also includes:
One the one P+ implanting ions zone is positioned at the 2nd P district, and a P+ implanting ions zone is in close proximity to the end face in the 2nd P district and a side in a close N+ implanting ions zone, and a P+ implanting ions zone couples this first triggering signal;
One the 2nd P+ implanting ions zone is positioned at the 2nd P district, and the 2nd P+ implanting ions zone is in close proximity to the end face in the 2nd P district and a side in close the 2nd N+ implanting ions zone, and the 2nd P+ implanting ions zone couples this first triggering signal;
One the 3rd N+ implanting ions zone, in the 2nd P district and between P+ implanting ions zone and the 2nd P+ implanting ions zone, the 3rd N+ implanting ions zone is in close proximity to the end face in the 2nd P district, and the 3rd N+ implanting ions zone couples first operating voltage;
One first isolation structure, part is positioned at a P district, and this first isolation structure is in close proximity to a N+ implanting ions zone and a P+ implanting ions zone, in order to isolate a N+ implanting ions zone and a P+ implanting ions zone;
One second isolation structure, part is positioned at a P district, and this second isolation structure is in close proximity to P+ implanting ions zone and the 3rd N+ implanting ions zone, in order to isolate P+ implanting ions zone and the 3rd N+ implanting ions zone;
One the 3rd isolation structure, part is positioned at a P district, and the 3rd isolation structure is in close proximity to the 3rd N+ implanting ions zone and the 2nd P+ implanting ions zone, in order to isolate the 3rd N+ implanting ions zone and the 2nd P+ implanting ions zone; And
One the 4th isolation structure, part is positioned at a P district, and the 4th isolation structure is in close proximity to the 2nd P+ implanting ions zone and the 2nd N+ implanting ions zone, in order to isolate the 2nd P+ implanting ions zone and the 2nd N+ implanting ions zone.
9. the ESD protection circuit of voltage source as claimed in claim 8, it is characterized in that: the structure of this first bipolar transistor comprises:
One second deep layer N district is embedded in bottom, a P district;
One the 3rd N district is positioned at a P district, extends to this second deep layer N district end face in the side direction of the 3rd N district by a P district end face, and wherein, the 3rd N district also comprises:
One the 4th N+ implanting ions zone is positioned at the 3rd N district, and the 4th P+ implanting ions zone is in close proximity to the end face in the 3rd N district, and the 4th N+ implanting ions zone couples first operating voltage;
One the 4th N district is positioned at a P district, and the 4th N district extends inwardly to this second deep layer N district end face by a P district end face with respect to the opposite side in the 3rd N district, and wherein, the 4th N district also comprises:
One the 5th N+ implanting ions zone is positioned at the 4th N district, and the 5th N+ implanting ions zone is in close proximity to the end face in the 4th N district, and the 5th N+ implanting ions zone couples first operating voltage;
One the 3rd P district is positioned at a P district and adjacent the 3rd N district and the 4th N district is arranged, and the 3rd P district extends inwardly to this second deep layer N district end face by a P district end face, and wherein, the 3rd P district also comprises:
One the 3rd P+ implanting ions zone is positioned at the 3rd P district, and the 3rd P+ implanting ions zone is in close proximity to the end face in the 3rd P district and a side in close the 4th N+ implanting ions zone, and the 3rd P+ implanting ions zone couples this second triggering signal;
One the 4th P+ implanting ions zone is positioned at the 3rd P district, and the 4th P+ implanting ions zone is in close proximity to the end face in the 2nd P district and a side in close the 5th N+ implanting ions zone, and the 4th P+ implanting ions zone couples this second triggering signal;
One the 6th N+ implanting ions zone, in the 3rd P district and between the 3rd P+ implanting ions zone and the 4th P+ implanting ions zone, the 6th N+ implanting ions zone is in close proximity to the end face in the 2nd P district, and the 6th N+ implanting ions zone couples second operating voltage;
One the 5th isolation structure, part is positioned at a P district, and the 5th isolation structure is in close proximity to the 4th N+ implanting ions zone and the 3rd P+ implanting ions zone, in order to isolate the 4th N+ implanting ions zone and the 3rd P+ implanting ions zone;
One the 6th isolation structure, part is positioned at a P district, and the 6th isolation structure is in close proximity to the 3rd P+ implanting ions zone and the 6th N+ implanting ions zone, in order to isolate the 3rd P+ implanting ions zone and the 6th N+ implanting ions zone;
One the 7th isolation structure, part is positioned at a P district, and the 7th isolation structure is in close proximity to the 6th N+ implanting ions zone and the 4th P+ implanting ions zone, in order to isolate the 6th N+ implanting ions zone and the 4th P+ implanting ions zone; And
One the 8th isolation structure, part is positioned at a P district, and the 8th isolation structure is in close proximity to the 4th P+ implanting ions zone and the 5th N+ implanting ions zone, in order to isolate the 4th P+ implanting ions zone and the 5th N+ implanting ions zone.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200310102218XA CN100399665C (en) | 2003-10-27 | 2003-10-27 | Voltage source electrostatic discharge protective circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200310102218XA CN100399665C (en) | 2003-10-27 | 2003-10-27 | Voltage source electrostatic discharge protective circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1612434A CN1612434A (en) | 2005-05-04 |
| CN100399665C true CN100399665C (en) | 2008-07-02 |
Family
ID=34756328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200310102218XA Expired - Lifetime CN100399665C (en) | 2003-10-27 | 2003-10-27 | Voltage source electrostatic discharge protective circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100399665C (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201026159A (en) * | 2008-12-26 | 2010-07-01 | Vanguard Int Semiconduct Corp | Electrostatic discharge protection circuit and integrated circuit utilizing the same |
| CN102012719B (en) * | 2009-09-07 | 2012-07-04 | 联想(北京)有限公司 | Notebook computer |
| CN106899011B (en) * | 2015-12-18 | 2019-01-18 | 中芯国际集成电路制造（天津）有限公司 | Electrostatic discharge protective circuit |
| TWI604676B (en) | 2016-10-05 | 2017-11-01 | 瑞昱半導體股份有限公司 | Cross-domain esd protection circuit |
| TWI604677B (en) | 2016-10-05 | 2017-11-01 | 瑞昱半導體股份有限公司 | Cross-domain esd protection circuit |
| CN107947138B (en) * | 2016-10-13 | 2019-07-23 | 瑞昱半导体股份有限公司 | ESD protection circuit across power domain |
| CN107947139B (en) * | 2016-10-13 | 2019-07-23 | 瑞昱半导体股份有限公司 | ESD protection circuit across power domain |
| WO2021232212A1 (en) * | 2020-05-19 | 2021-11-25 | 华为技术有限公司 | Electrostatic discharge protection circuit and integrated circuit having electrostatic discharge protection circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1145143A (en) * | 1994-03-28 | 1997-03-12 | 英特尔公司 | Electrostatic discharge protection circuits using biased and terminated PNP transistor chains |
| US6011681A (en) * | 1998-08-26 | 2000-01-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Whole-chip ESD protection for CMOS ICs using bi-directional SCRs |
| CN1314019A (en) * | 1998-06-17 | 2001-09-19 | 英特尔公司 | Power supply clamp for esd protection |
-
2003
- 2003-10-27 CN CNB200310102218XA patent/CN100399665C/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1145143A (en) * | 1994-03-28 | 1997-03-12 | 英特尔公司 | Electrostatic discharge protection circuits using biased and terminated PNP transistor chains |
| CN1314019A (en) * | 1998-06-17 | 2001-09-19 | 英特尔公司 | Power supply clamp for esd protection |
| US6011681A (en) * | 1998-08-26 | 2000-01-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Whole-chip ESD protection for CMOS ICs using bi-directional SCRs |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1612434A (en) | 2005-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108701693B (en) | Embedded PMOS-triggered silicon controlled rectifier for electrostatic discharge protection | |
| US7087938B2 (en) | ESD protective circuit with collector-current-controlled triggering for a monolithically integrated circuit | |
| US6144542A (en) | ESD bus lines in CMOS IC's for whole-chip ESD protection | |
| US10147717B2 (en) | Electrostatic discharge protection circuit | |
| US6765771B2 (en) | SCR devices with deep-N-well structure for on-chip ESD protection circuits | |
| EP2057682B1 (en) | N-channel esd clamp with improved performance | |
| US6465848B2 (en) | Low-voltage-triggered electrostatic discharge protection device and relevant circuitry | |
| US8194369B2 (en) | Semiconductor integrated circuit | |
| KR100849069B1 (en) | Electro static discharge device | |
| CN103001206B (en) | Electrostatic discharge (ESD) power clamp for clamping high-voltage power supply in mixed-voltage chip by means of low-voltage transistor | |
| US7394631B2 (en) | Electrostatic protection circuit | |
| US8315024B2 (en) | Electrostatic discharge protection circuit, integrated circuit and method of protecting circuitry from an electrostatic discharge voltage | |
| US20120307408A1 (en) | Semiconductor device with a plurality of power supply systems | |
| US20080278872A1 (en) | Electrostatic Discharge Protection Circuit | |
| US8934204B2 (en) | Protection circuit for semiconductor integrated circuit and driving method therefor | |
| KR20130012565A (en) | Semiconductor integrated circuit | |
| JP3885172B2 (en) | Electrostatic discharge protection circuit | |
| US9054517B1 (en) | Smart diagnosis and protection circuits for ASIC wiring fault conditions | |
| KR20050122166A (en) | Separated power esd protection circuit and integrated circuit thereof | |
| US5675469A (en) | Integrated circuit with electrostatic discharge (ESD) protection and ESD protection circuit | |
| EP3340298A1 (en) | Electrostatic discharge (esd) protection for use with an internal floating esd rail | |
| US20090086392A1 (en) | Power-rail esd protection circuit without lock-on failure | |
| US8169758B2 (en) | Path sharing high-voltage ESD protection using distributed low-voltage clamps | |
| CN100399665C (en) | Voltage source electrostatic discharge protective circuit | |
| US9154122B2 (en) | Latch up detection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20080702 |