CN100397791C

CN100397791C - ASIC realizing method for transmission system overhead processing chip side clock domain switching circuit

Info

Publication number: CN100397791C
Application number: CNB03140071XA
Authority: CN
Inventors: 何志阔
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2003-08-06
Filing date: 2003-08-06
Publication date: 2008-06-25
Anticipated expiration: 2023-08-06
Also published as: CN1581705A

Abstract

The present invention relates to an implementation method for the clock domain switching circuit of overhead processing chip receiving line side of a transmission system. A plurality of clock domains which are input by the receiving line side and have different frequencies and phases are switched to reference clock domains which are input by a local system. The input clock frequency of the clock domain switching circuit of the present invention can be N times as high as the frequency of the reference clock provided by the local system, and can be also 1/4 of the frequency of the local input system clock; after being processed by the clock domain switching circuit, all the clock domains are switched to a single system clock domain.

Description

The ASIC implementation method of transmission system overhead processing chip side clock zone change-over circuit

Technical field:

The present invention relates to the implementation method of the clock zone change-over circuit of communication transmission system overhead processing chip.

Background technology:

In the overhead processing chip of transmission system, enter from the receiving lines side after the processing of serial high speed circulation oversampling clock data recovery unit of chip, according to user's demand, all can produce channelized frequencies usually, the asynchronous clock that phase place has nothing in common with each other.In traditional processing method, the conversion between these clocks and the local system clock need could realize in pointer regeneration usually.Such processing method makes the chip designer face too many asynchronous design, has not only increased design difficulty, faces the coverage rate that asynchronous circuit reduces Time-Series analysis too much simultaneously when static timing analysis is carried out in the circuit design rear end equally.

The objective of the invention is to: the ASIC implementation method that a kind of transmission system overhead processing chips wire trackside clock zone change-over circuit is provided.

Summary of the invention:

The present invention is achieved in that

A, at first M CLK_IA clock zone with the line side of input clock territory change-over circuit carries out frequency division by the 4*X frequency dividing circuit;

B, M the CLK_IA clock zone frequency division that circuit is imported are M the CLK_IC that frequency is a system reference clock frequency 1/4;

The clock zone CLK_IB that N frequency of c, receiving lines input is system reference clock frequency 1/4; The CLK_IA of line side input has been converted to CLK_IC later on through 4*X frequency dividing circuit frequency division; The clock zone of input this moment promptly becomes M+N the clock zone that frequency is a system reference clock frequency 1/4 of line side input; The conversion that this moment, the clock zone converting unit was carried out is exactly the conversion between the reference clock territory importing of line side M+N CLK_IC clock zone and system; After the processing through the clock zone change-over circuit, the data rate of the CLK_IC clock zone of input still is 1/4 of a system reference clock rate, just the clock of handling is by M+N the frequency in line side, and the asynchronous clock CLK_IC that phase place has nothing in common with each other has converted a system clock of local input to; The clock of the interior processing of circuit of chip this moment is by M+N frequency, and the line side clock that phase place has nothing in common with each other is reduced to a system reference clock.

A plurality of asynchronous clock domains that circuit of the present invention directly just produces the clock and data recovery unit at receiving lines are undertaken synchronously by a reference clock of system's input, handle by the reference clock that the circuit in the later chip of clock zone conversion can both the employing system be imported.Reduce the asynchronous design circuit of chip internal greatly, reduced the difficulty of chip design; Simultaneously also make chip when carrying out the rear end static timing analysis, can carry out the analysis of static timing, improve the coverage rate of chip static timing analysis abundant circuit.Guarantee the correctness of chip sequential function better.

Description of drawings:

Accompanying drawing 1 is the transfer principle figure of receiving lines clock zone of the present invention to the system reference clock zone;

Accompanying drawing 2 is conversion unit circuit schematic diagrams of receiving lines side clock zone of the present invention and reference clock;

Accompanying drawing 3 is clock zone change-over circuit input/output signal sequential charts of the present invention.

Execution mode:

Chips of the present invention will receive the system reference clock of a local input, M the frequency reference clock X line clock doubly that just uses system reference clock of this local input that the line side is recovered out, perhaps N frequency is system reference clock 1/4 the line clock territory is transformed on system reference clock zone of importing this this locality.

As shown in Figure 1: M the frequency that circuit receiving lines side of the present invention is sent into is data and the clock (the temporary called after CLK_IA of this group clock) on the X clock zone doubly of reference clock (the temporary called after CLK_REF of clock), and data and clock (this organizes the temporary called after CLK_IB of clock) on N frequency clock zone that is system reference clock 1/4.At first M CLK_IA clock zone with the line side of input clock territory change-over circuit carries out frequency division by the 4*X frequency dividing circuit, frequency division is the clock (called after CLK_IC temporarily) that M frequency is system reference clock frequency 1/4, and this function can be finished by the frequency dividing circuit of a simple 4*X.With M CLK_IA clock zone frequency division of circuit input is after M frequency is the CLK_IC of system reference clock frequency 1/4, for the clock zone translation circuit, the clock zone (temporary called after CLK_IC) that it is system reference clock frequency 1/4 that the clock zone of input promptly becomes M+N frequency of line side input.

The conversion that this moment, the clock zone converting unit was carried out is exactly the conversion between the reference clock territory CLK_REF importing of line side M+N CLK_IC clock zone and system.After the processing through the clock zone change-over circuit, the data rate of M+N CLK_IC clock zone of input still is 1/4 of a system reference clock rate, just the clock of handling is by M+N the frequency in line side, and the asynchronous clock CLK_IC that phase place has nothing in common with each other has converted a system reference clock of local input to.The clock of the interior processing of circuit of chip this moment is by M+N frequency, and the line side clock that phase place has nothing in common with each other is reduced to a system reference clock.

M+N CLK_IC clock zone for the line side input, the principle of M+N clock zone change-over circuit that converts them to the system reference clock zone is identical, so the present invention only describes the conversion unit circuit from some CLK_IC clock zones of receiving lines side to the system reference clock zone.The circuit theory diagrams of its conversion are as shown in Figure 2:

Among Fig. 2, CLK_IC_* represents that the line side recovers to come out after the clock and data recovery unit frequency is the receiving lines side clock of system reference clock CLK_REF clock 1/4; DATA_IN_* represents and line side input clock CLK_IC_* data in synchronization; CLK_REF represents the system reference clock of local input; CLK_IC_*_ENA represents that the line clock territory is transformed into the later line clock enable signal of system reference clock zone; DATA_OUT_* represents through the output of the data after the clock zone conversion, this moment data frequency still the frequency with line side clock CLK_IC_* is identical, still, the data of this moment have been transformed on the clock zone of system reference.

1. trigger represents that the line side data and the clock CLK_IC_* that import are synchronous;

2. and 3. trigger is represented to use the local system reference clock of importing that the clock CLK_IC_* of circuit input is carried out double sampling;

4. trigger is represented with generation line side clock enable signal behind the clock CLK_IC_* rising edge of system reference clock sampling line side, and it is synchronized on the system reference clock.

The trigger that has an Enable Pin 5. represent by the line side clock enable signal that produces behind the clock CLK_IC_* of system reference clock sampling line side with the data transaction of line side input to the clock zone of system reference clock.

After the clock zone change-over circuit, in chip, the M+N circuit-switched data that is synchronized with CLK_IC_* separately of line side input is handled and all will be adopted a system reference clock of local input to handle.Because receiving lines side at transmission system overhead processing chip, there is shake to a certain degree in the line side clock that chip receives, therefore the CLK_IC_* clock in line side and system reference clock are not strict quadruple relations, may exist shake to reach the possibility of a reference clock cycle under the worst situation.After guaranteeing that clock zone converts, the using system reference clock can not leak the data of adopting the line side input to changing through clock zone when later data are handled, the continuous sampling that the CLK_IC_* that the present invention imports the line side by the system reference clock carries out rising edge has produced a line clock enable signal CLK_IN_*_ENA later on, system clock all will carry out when this clock enable signal is effective the processing of circuit input data in the chip, the M+N circuit-switched data that so just can guarantee the line side input can not lost when the using system reference clock is handled, as shown in Figure 3.

As can be seen from Figure 3, even very severe at the line side clock jitter, shake reaches the one-period of the reference clock of a local system input, and the data of line side input are not through losing after the clock zone conversion yet.In handling through the subsequent conditioning circuit after the clock zone conversion, M+N road clock enable signal CLK_IC_*_ENA will occur in pairs with the M+N circuit-switched data that conversion back using system reference clock is handled, that is to say, in the processing of subsequent conditioning circuit, the processing of data DATA_OUT_* is only just carried out under the effective situation of CLK_IC_*_ENA.

Claims

1. the application-specific IC ASIC implementation method of a transmission system overhead processing chip clock zone change-over circuit is characterized in that:

A, M the frequency of at first circuit receiving lines side being sent into are that local system reference clock x line side clock zone and N frequency sending into of circuit receiving lines side doubly is local system reference clock 1/4 the line side clock zone carries out frequency division by the 4*x frequency dividing circuit, are the clock and the data of system reference clock frequency 1/4 with its frequency division;

B, the system reference clock that uses this locality to import are its double sampling of line side clock of 1/4 to M+N frequency; Produce a line clock enable signal that is synchronized with the system reference clock;

The line clock enable signal and the data of C, output simultaneously and system reference clock synchronization, these two groups of signals always occur in pairs in subsequent process circuit; The frequency of line side input is that local system reference clock x line side clock zone doubly has been converted to the clock zone that frequency is a system reference clock 1/4 later on through 4*x frequency dividing circuit frequency division; Together with N the clock zone that frequency is a system reference clock 1/4 that the line side is sent into, the conversion that the clock zone change-over circuit carries out be exactly line side M ten a N frequency be conversion between the reference clock territory of the clock zone of system reference clock 1/4 and system's input; After the processing through the clock zone change-over circuit, the frequency of input is that the data rate of the clock zone of system reference clock 1/4 still is 1/4 system reference clock frequency, and just the clock of the handling clock zone that has been system reference clock 1/4 by each asynchronous clock frequency inequality of M+N phase place in line side has converted a system clock of local input to; The line side clock that the clock of the interior processing of circuit of chip this moment is had nothing in common with each other by M+N phase place is reduced to a system reference clock.