CN100397675C - Improved unit structure for reducing phase transition memory writing current, and method thereof - Google Patents
Improved unit structure for reducing phase transition memory writing current, and method thereof Download PDFInfo
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- CN100397675C CN100397675C CNB2004100177474A CN200410017747A CN100397675C CN 100397675 C CN100397675 C CN 100397675C CN B2004100177474 A CNB2004100177474 A CN B2004100177474A CN 200410017747 A CN200410017747 A CN 200410017747A CN 100397675 C CN100397675 C CN 100397675C
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- 230000007704 transition Effects 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000010438 heat treatment Methods 0.000 claims abstract description 26
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000005498 polishing Methods 0.000 claims abstract description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 3
- -1 sulfur series compound Chemical class 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 10
- 238000003860 storage Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 230000001413 cellular effect Effects 0.000 claims description 7
- 238000010276 construction Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000007772 electrode material Substances 0.000 claims description 3
- 239000012782 phase change material Substances 0.000 claims description 2
- 230000008859 change Effects 0.000 abstract description 4
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 150000003464 sulfur compounds Chemical class 0.000 abstract 2
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical class [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 abstract 1
- 238000002844 melting Methods 0.000 abstract 1
- 230000008018 melting Effects 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001786 chalcogen compounds Chemical class 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
The present invention relates to an improved unit structure and an implement method for lowering the working current of a phase change memory, which belongs to the technical field of microelectronics. The present invention is characterized in that a transition layer of which the thickness is 10 to 50 nm is added between a heating electrode and sulfur compounds, wherein the resistivity of the transition layer is higher than that of the heating electrode, the melting point is higher than that of the sulphur compounds, and the transition layer can be made of Pt, Ti, TiN, etc. The structural implement is achieved by depositing bottom electrodes in the form of sputtering, depositing an additional dielectric layer, etching small holes by way of exposure, depositing the heating electrode and the transition layer in sequence, depositing a dielectric layer on the transition layer, etching large holes in which the sulfur compounds are deposited, and depositing top electrodes after the process of chemico-mechanical polishing. Through the structural implement and the application, the calorific efficiency is high due to the high resistivity of the transition layer, and the temperature required can be achieved by using small current.
Description
Technical field
A kind ofly reduce the cellular construction of phase transition storage (PRAM) write current and improve one's methods, belong to the manufacturing process of the nano material in the microelectronics.
Background technology
Phase-change random access memory (PRAM) has been compared remarkable advantages with present dynamic random access memory (DRAM), flash memory (FLASH): its volume is little, and driving voltage is low, and power consumption is little, and read or write speed is very fast, and is non-volatile.PRAM is not only non-volatility memorizer, and might make multistage storage, and be useful for ultralow temperature and hot environment, anti-irradiation, anti-vibration, therefore not only will be widely applied to daily portable type electronic product, and huge potential application be arranged in fields such as Aero-Space.Especially, its high speed, the non-volatile deficiency that has just in time remedied FLASH and ferroelectric memory (FeRAM) in portable type electronic product.American I ntel company just once foretold that PRAM will replace FLASH, DARM and static random access memory (SRAM), and PRAM chip very F.F. is gone into market.International semiconductor federation is predicted as PRAM equally and can realizes one of business-like memory at first in the ROADMAP of its calendar year 2001.
Facing a subject matter yet study phase-change random access memory at present, is exactly how further to reduce its operating current, particularly wherein requires bigger write current.Because phase transition storage will and metal-oxide-semiconductor field effect t (MOSFET) device integrated, operating current is provided by the MOSFET pipe.Yet the electric current by the MOSFET pipe is limited, and to reduce electric current be particular importance for the power consumption that reduces entire device.At this, industrial quarters has proposed various solution.Wherein a kind of method reduces heating electrode exactly and thereby the chalcogenide compound contact area increases current density.As Spacer PatterningTechnology (l.ang-KyuChoi, su-Jae King, the IEEE transaction on electrondevicse of Samsung (Samsung) in proposition in 2003 and use, VOL.49, N0.3,4362.H.Horri, J.H.Yi, J.H.Park, YH Ha, LG.Baek, S.O.Park, YN.Hwang, Symposium on VLSI Tech Digest of TechPapers, 2003), EDGE CONTACT method (3.YHHa, J.H.Y, J.H.Park, S.H.Joo, S.O.Park, U-InChung, J.T.Moon, Symposium on VLSITech Digest of Tech Papers, 2003)
Summary of the invention
The object of the invention is to propose a kind ofly to reduce the cellular construction of phase transition storage write current and improve one's methods.It is to set about from the improvement of PRAM structure, reaches the operating current that reduces PRAM from another angle.
Structural improved being characterised in that of the PRAM that the present invention proposes is the transition zone that increases a high resistivity between heating electrode and sulfur series compound phase-change material, and the resistivity of transition zone is greater than heating electrode resistivity, and fusing point is higher than chalcogenide compound.Its thickness in conjunction with the method for the contact area that reduces heating electrode and chalcogenide compound, thereby reaches the increase current density between 10-SOnm, reduce the purpose of operating current.
The heating electrode that current PRAM uses mainly is to use the tungsten material.The resistivity of W has only 5.65X10-gS}m, and the resistivity of metals such as Pt and Ti reaches 10.6 and 42.0X10-aSZm respectively.And some nitride (as TiN) resistivity is all than all more a lot of than W, and their fusing point is higher than the fusing point of chalcogenide compound again, can select their materials as transition zone.As for not exclusively doing heating electrode with them, be based on and reduce power consumption, be beneficial to the consideration of each side such as heat radiation.And the present invention and above-mentioned Spacer Patterning Technology, EDGE CONTACT method etc. is not conflicted, and can use in the lump, thereby reaches better effect.
The step of the structural improved specific implementation of PRAM that the present invention proposes is as follows:
(1) on substrate, with the method deposition hearth electrode material of magnetron sputtering, thickness 50-150nm, sputter is that base vacuum is 4 * 10
-6Torr, the sputter vacuum is 0.10Pa;
(2) deposition one deck silicon nitride medium layer on the hearth electrode of step (1) deposition, thickness is 100-150nm, by the exposure lithographic technique, etches aperture in the dielectric layer centre then, the aperture is 0.15-0.5um;
(3) deposit heating electrode and transition zone of heating successively, heating electrode thickness is 70-120nm, and transition region thickness is 20-50nm, chemico-mechanical polishing then;
(4) deposit one deck medium silicon nitride layer more thereon, the exposure etching, the aperture is at 0.7-1.0um, magnetron sputtering chalcogenide compound GeTeSb in the hole, and then chemico-mechanical polishing (CMP).
(5) deposit top electrode at last, thickness is 80-150nm, promptly finishes simple unit PRAM preparation of devices.
Concrete steps are seen Fig. 1.
Description of drawings
Fig. 1 is a cell phase change memory preparation process schematic diagram
(a) be magnetron sputtering deposition W electrode on silicon oxide substrate
(b) be deposited silicon nitride, and exposure etching aperture
(c) be deposition heating electrode W and transition zone of heating Ti
(d) be deposited silicon nitride, and the exposure etched hole, magnetron sputtering GeTeSb in the hole
(e) be deposition top electrode W, make the unit PRAM of architecture advances.
1 is substrate among the figure;
2 is hearth electrode W;
3 is dielectric layer Si
3N
4
4 is heating electrode W;
5 are transition zone of heating Ti;
6 is chalcogen compound GeTeSb;
7 is dielectric layer Si
3N
4
8 is top electrode W
Embodiment
Embodiment 1: below by the manufacturing process that elaborates cell phase change memory in conjunction with the accompanying drawings, further helping the understanding of the present invention, but the present invention is confined to embodiment absolutely not.Its simple unit component preparation process is as follows:
(1), do substrate with oxidized silicon chip, the method with magnetron sputtering on it at room temperature deposits hearth electrode material W, and thickness is about 100nm, and the power during sputter is 300W, and base vacuum is 4 * 10
-6Torr, the sputter vacuum is 0.10Pa; (Fig. 1, a)
(2), deposit one deck silicon nitride medium layer thereon, thickness is 100nm, carves aperture by steps such as exposure etchings then, and the aperture is at 0.25um; (Fig. 1, b)
(3), deposit heating electrode W thereon successively, transition zone Ti, W thickness are 100nm, the thick 30nm of Ti, and chemico-mechanical polishing then (CMP), attention can not be ground too much, prevent that the Ti layer from all having polished; (Fig. 1, c)
(4), deposit one deck dielectric layer silicon nitride again, the exposure etching, aperture 1.0um, magnetron sputtering GeTeSb in the hole, power 100W, base vacuum are 3 * 10
-6Torr, the sputter vacuum is 0.08Pa.And then chemico-mechanical polishing; (Fig. 1, d)
(5), deposition top electrode W, thickness is about 100nm.Promptly finish simple cell phase change memory preparation (Fig. 1, e).Draw lead, just can measure its various performances.
Can find out obviously that by present embodiment add a transition zone Ti in the modified model PRAM structure provided by the invention between heating electrode layer W and chalcogenide compound GeTeSb, its thickness is less than 50nm.And combine closely between this transition zone Ti and heating electrode layer and the chalcogenide compound layer.
Claims (4)
1. one kind reduces phase transition storage write current cellular construction, adds one deck buffer layer material between heating electrode and sulfur series compound phase-change material structure, and the resistivity that it is characterized in that transition zone is greater than heating electrode, and fusing point is higher than chalcogenide compound; Heating electrode is W, and the material of transition zone is a kind of in Pt, Ti or the TiN material, combines closely between transition zone and heating electrode layer and the chalcogenide compound layer.
2. by the described phase transition storage write current cellular construction that reduces of claim 1, the thickness that it is characterized in that transition zone is 10nm-50nm.
3. improve the method that reduces phase transition storage write current cellular construction as claimed in claim 1 or 2, it is characterized in that its concrete steps are:
(1) on substrate, with the method deposition hearth electrode material of magnetron sputtering, thickness 50-150nm sputter is that base vacuum is 4 * 10
-6Torr, the sputter vacuum is 0.10Pa;
(2) deposition one deck silicon nitride medium layer on the hearth electrode of step (1) deposition, thickness is 100-150nm, by the exposure lithographic technique, etches aperture in the dielectric layer centre then, the aperture is 0.15-0.5 μ m;
(3) deposit heating electrode and transition zone of heating successively, heating electrode thickness is 70-120nm, and transition region thickness is 20-50nm, chemico-mechanical polishing then;
(4) deposit one deck medium silicon nitride layer more thereon, the exposure etching, the aperture is at 0.7-1.0um, magnetron sputtering chalcogenide compound GeTeSb in the hole, and then chemico-mechanical polishing;
(5) deposit top electrode at last, thickness is 80-150nm, promptly finishes simple unit PRAM preparation of devices.
4. by described a kind of the improving one's methods of phase transition storage operating current cellular construction that reduce of claim 3, it is characterized in that the material of described hearth electrode and top electrode is W.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100177474A CN100397675C (en) | 2004-04-16 | 2004-04-16 | Improved unit structure for reducing phase transition memory writing current, and method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100177474A CN100397675C (en) | 2004-04-16 | 2004-04-16 | Improved unit structure for reducing phase transition memory writing current, and method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN1564337A CN1564337A (en) | 2005-01-12 |
| CN100397675C true CN100397675C (en) | 2008-06-25 |
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| CNB2004100177474A Expired - Fee Related CN100397675C (en) | 2004-04-16 | 2004-04-16 | Improved unit structure for reducing phase transition memory writing current, and method thereof |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI291745B (en) | 2005-11-30 | 2007-12-21 | Ind Tech Res Inst | Lateral phase change memory with spacer electrodes and method of manufacturing the same |
| CN100553005C (en) * | 2007-08-01 | 2009-10-21 | 中国科学院上海微***与信息技术研究所 | Reduce the zone of heating of phase transformation memory device unit power consumption and the manufacture method of device |
| CN100565955C (en) * | 2008-01-22 | 2009-12-02 | 中国科学院上海微***与信息技术研究所 | The transition zone that is used for phase transition storage |
| CN101335327B (en) * | 2008-08-05 | 2010-06-16 | 中国科学院上海微***与信息技术研究所 | Method for controlling phase-change material or phase-change memory unit volume change and corresponding construction |
| CN103606624B (en) * | 2013-11-15 | 2017-12-05 | 上海新储集成电路有限公司 | A kind of phase transition storage with heterogeneous side wall construction heating electrode and preparation method thereof |
| CN109839296A (en) * | 2017-11-28 | 2019-06-04 | 中国科学院上海微***与信息技术研究所 | A kind of preparation method of the transmission electron microscope sample for electrical testing in situ |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020074658A1 (en) * | 2000-12-20 | 2002-06-20 | Chien Chiang | High-resistivity metal in a phase-change memory cell |
| US20040037179A1 (en) * | 2002-08-23 | 2004-02-26 | Se-Ho Lee | Phase-changeable devices having an insulating buffer layer and methods of fabricating the same |
| US20040067608A1 (en) * | 2000-12-14 | 2004-04-08 | Charles Dennison | Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040067608A1 (en) * | 2000-12-14 | 2004-04-08 | Charles Dennison | Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby |
| US20020074658A1 (en) * | 2000-12-20 | 2002-06-20 | Chien Chiang | High-resistivity metal in a phase-change memory cell |
| US20040037179A1 (en) * | 2002-08-23 | 2004-02-26 | Se-Ho Lee | Phase-changeable devices having an insulating buffer layer and methods of fabricating the same |
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