CN100397587C - Silicon gate etching process capable of avoiding microtrench phenomenon - Google Patents
Silicon gate etching process capable of avoiding microtrench phenomenon Download PDFInfo
- Publication number
- CN100397587C CN100397587C CNB2005101262996A CN200510126299A CN100397587C CN 100397587 C CN100397587 C CN 100397587C CN B2005101262996 A CNB2005101262996 A CN B2005101262996A CN 200510126299 A CN200510126299 A CN 200510126299A CN 100397587 C CN100397587 C CN 100397587C
- Authority
- CN
- China
- Prior art keywords
- etching
- etching process
- base point
- little groove
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
The present invention provides a silicon gate etching process capable of avoiding a microtrench phenomenon, which comprises a through step, a main etching step, a base point etching step and an over etching step. The process effectively avoids the microtrench phenomenon without changing hardware design by adding the base point etching process after the main etching step of the silicon gate etching process and guaranteeing the verticality of an etching sectional plane, and thereby, the requirement of the advanced gate etching process is satisfied. The method is simple and practical and not only avoids variable increased by system hardware design, guarantees the process stability but also avoids the system upgrade and saves a pile of expenses.
Description
Technical field
The present invention relates to a kind of gate etching process, specifically, relate to a kind of Si-gate etching technics that can avoid little groove phenomenon.
Background technology
The Si-gate etching technics is the important step that realizes semiconductor manufacturing feature size, and along with the development of semiconductor technology, the lines of grid etching are more and more narrow, and grid oxide layer thickness is more and more thinner, and the difficulty of gate etching process also constantly raises thereupon.The etching section of Si-gate is meant the sidewall shape of the figure that is etched.In the etching process, good section control is very important, and qualified handicraft product requires the section of vertical smooth.Because the influence of various factors, general technology can not reach desirable etching section, occurs phenomenons such as undercutting, little raceway groove, sidewalls flex easily.
Existing etching technics is divided into mainly and runs through that (the main quarter (cross and carve (OE, Overetch) three key steps of etching by ME, Mainetch) etching for BT, Breakthrough) etching.Wherein main etching is the main body etch step, and its concrete technology is as follows: going up RF power is 250-450W, and following RF power is 30-100W, and chamber pressure is 5-30mT, and total gas flow rate is 65-280sccm, wherein Cl
2Be 10-50sccm, HBr is 50-200sccm, O
2Gas or He/O
2Gaseous mixture 5-30sccm (the two volume ratio is 7: 3).
Adopt in this process to contain one step of Cl gas and finish, strong by the etching power of Cl free radical, the fast characteristics of reaction speed mainly are anisotropic etchings, form steep etching section easily.But when spending quarter, the chamber pressure that adopts is higher, collision is more in the plasma sheath, compare with main etching and to be more prone to isotropic etching, under the high-density plasma environment, etch rate at etching lines bottom corners place will be easy to form little groove phenomenon thus faster than the etch rate of other positions, causes the inefficacy of device.
Summary of the invention
(1) technical problem that will solve
Purpose of the present invention aims to provide a kind of Si-gate etching technics that can avoid occurring little groove phenomenon.
(2) technical scheme
For achieving the above object, the present inventor provides a kind of new gate etching process, increases a base point etching step after the main etching step, and the concrete process conditions of this step are:
Upper electrode power is 250-450W; Lower electrode power is 20-80W; Chamber pressure is 15-45mT; Process gas is Cl
2, HBr, He and O
2Mist, total gas flow rate is 125-320sccm, wherein the ratio of each gas is not particularly limited, but is preferably Cl
220-40sccm, HBr 100-250sccm, He 3.5-21sccm, O
21.5-9sccm.
Preferred processing condition is: upper electrode power is 300-350W; Lower electrode power is 30-50W; Chamber pressure is 20-40mT; The process gas total flow is 185-255sccm, and wherein the ratio of each gas is not particularly limited, but is preferably: Cl
225-35sccm, HBr 150-200sccm, He7-14sccm, O
23-6sccm.
Most preferred process conditions are: upper electrode power is 325W; Lower electrode power is 40W; Chamber pressure is 30mT; The process gas total flow is 220sccm, wherein Cl
2Be 30sccm, HBr is 175sccm, He 10.5sccm, O
24.5sccm.
In Si-gate etching technics base point etching step of the present invention, by increasing Cl
2: the ratio of HBr, the augmenting response chamber pressure reduces the bias voltage radio-frequency power, helps isotropic etching, thereby forms the base point etching phenomenon at etching lines bottom corners place.For in over etching step subsequently, it is steep to obtain section, obtains the base angle of near vertical, and the height of base point etching should be 1/4th to 1/2nd of etching lines height, and angle is the 40-60 degree.Preferred base point etching produces at 1/3rd places of lines height, and the angle of base point etching is 50 degree simultaneously.
In the main etching step, can take the laser interference end-point method (IEP) of end point determination to determine main end of carving, that is the original position of base point etching, that is, 1/4th to 1/2nd places of etching lines height certainly, also can estimate by etch rate.Equally also use IEP to determine the end of base point etching.
Technology of the present invention run through etching and over etching is same as the prior art.Promptly for running through etching, last RF power is 200-400W, and following RF power is 30-100W, and chamber pressure is 5-15mT, and process gas is C
2F
6, its flow is 30-100sccm.For over etching, last RF power is 250-450W, and following RF power is 30-100W, and chamber pressure is 50-90mT, and total gas flow rate is 155-530sccm, and wherein HBr is 50-250sccm, and He is 100-250sccm, He/O
2Gaseous mixture (the two volume ratio is 7: 3) 5-30sccm.
This technology is applicable to all grid etching apparatuss.
(3) beneficial effect
This technology can only by increase the base point etching step after Si-gate etching technics main etching step, effectively have been avoided the appearance of little groove phenomenon under the prerequisite that does not change hardware designs, satisfy the needs of advanced gate etching process.This method is simple, has not only avoided the parameter that The Hardware Design increased, has guaranteed the stability of technology; Can also avoid system upgrade, save the writing spending.
Description of drawings
Fig. 1 is a silicon chip cross section micrograph after the existing gate etching process over etching step
Fig. 2,4,6 is silicon chip cross section micrograph after the gate etching process base point etching step of the present invention
Fig. 3,5,7 is silicon chip cross section micrograph after the grid etching over etching step of the present invention
Device therefor is the S-4700 awkward silence at a meeting scanning electron microscopy that Hitachi, Ltd produces, and multiplication factor is 150,000 times.
Embodiment
Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiment only to be used to the present invention is described and be not used in and limit the scope of the invention.
Embodiment 1
Use silicon etching equipment to be the commercial machine of northern microelectronics 200mm.
The pattern piece silicon chip structure that is adopted is: silicon chip/silicon dioxide (10-100 dust)/polysilicon (1300-2000 dust)/silicon dioxide (100-150 dust)/silicon oxynitride (200-300 dust).It is on silicon dioxide/silicon oxynitride double-decker that the etching figure is transferred to hard mask by photoresistance.Has 80-260nm live width figure on the pattern piece.
In the etching technics, at first import silicon chip into etching reaction chamber, fixing by electrostatic chuck absorption, chamber temp is controlled to be 60 ℃, silicon temperature control system design temperature is 60 ℃, blow system pressure and be set at 8T for improving the He gas back of the body that temperature homogeneity adds, after the auxiliary process conditional stability, carry out etching technics.
BT goes on foot etching: the primary thin layer of silicon dioxide (autoxidation forms in the air, and thickness is generally at the 5-20 dust) of removing polysilicon surface.Concrete process conditions are as follows: chamber pressure 7mT, last RF power 300W, following RF power 80W, process gas C
2F
6Flow 50sccm.Process time 5s.
Main etching: etching is removed most unwanted silicon materials, forms the silicon gate structure main body, is the main part of etching technics, and the critical size control ability of this step has significant effects to final etching result.Concrete process conditions are as follows: chamber pressure 15mT, and last RF power 350W, following RF power 50W, process gas is Cl
230sccm, HBr 170sccm, O
2The mist of 10sccm, process time control detects control by end-point detecting system.
Over etching: it is perfect to be used for that the Si-gate shape at main etching place is done further finishing.Concrete process conditions are as follows: chamber pressure 80mT, and last RF power 250W, following RF power 50W, process gas are 180sccm HBr, 100sccm He, 8sccm O
2The mist of forming, process time 50s.
After etching technics was finished, by the awkward silence at a meeting sem observation, the etching section had little groove phenomenon (see figure 1) as can be seen.
Embodiment 2
According to embodiment 1 described method, difference is that add the base point etching step behind main etching: chamber pressure is 30mT, and last RF power is 325W, and following RF power is 40W, and total gas flow rate is 220sccm; Cl wherein
2Be 30sccm, HBr is 175sccm, and He is 10.5, O
24.5sccm.Process time control detects control by end-point detecting system.
After running through etching, main etching and base point etching technology and finishing, by awkward silence at a meeting sem observation silicon chip cross section pattern, base point etching produces at 1/3rd places of etching lines height, the basic point (see figure 2) of 50 degree of having an appointment at etching lines bottom corners place as can be seen; Repeat this technology with new silicon chip in addition, after whole gate etching process is finished, the steep no little groove phenomenon (see figure 3) of etching section.
Embodiment 3
According to embodiment 2 described methods, difference is that the base point etching process is: going up RF power is 250W, and following RF power is 80W, and chamber pressure is 15mT, and total gas flow rate is 297sccm, wherein Cl
2Be 20sccm, HBr is 250sccm, and He is 21sccm, O
2Be 6sccm.
After running through etching, main etching and base point etching technology and finishing, base point etching produces at 1/4th places of etching lines height, the basic point (see figure 4)s of 40 degree of having an appointment at etching lines bottom corners place as can be seen; Repeat this technology with new silicon chip in addition, after whole gate etching process is finished, the steep no little groove phenomenon (see figure 5) of etching section.
Embodiment 4
According to embodiment 2 described methods, difference is that the base point etching process is: going up RF power is 450W, and following RF power is 80W, and chamber pressure is 45mT, and total gas flow rate is 125sccm, wherein Cl
2Be 25sccm, HBr is 90sccm, and He is 8.5sccm, O
2Be 1.5sccm.
After running through etching, main etching and base point etching technology and finishing, base point etching produces the basic point (see figure 6)s of 60 degree of having an appointment at etching lines bottom corners place as can be seen at 1/2nd places of etching lines height; Repeat this technology with new silicon chip in addition, after whole gate etching process is finished, the steep no little groove phenomenon (see figure 7) of etching section.
Claims (10)
1. the gate etching process that can avoid little groove phenomenon comprises and runs through etching, main etching and over etching, it is characterized in that increasing base point etching behind the described main etching, and the process conditions of described base point etching are: upper electrode power is 250-450W; Lower electrode power is 20-80W; Chamber pressure is 15-45mT; The base point etching process gas is Cl
2, HBr, He and O
2Mist, the process gas total flow is 125-320sccm.
2. the gate etching process that can avoid little groove phenomenon as claimed in claim 1, it is characterized in that described base point etching process conditions are: upper electrode power is 300-350W; Lower electrode power is 30-50W; Chamber pressure is 20-40mT.
3. the gate etching process that can avoid little groove phenomenon as claimed in claim 2, it is characterized in that described base point etching process conditions are: upper electrode power is 325W; Lower electrode power is 40W; Chamber pressure is 30mT.
4. the gate etching process that can avoid little groove phenomenon as claimed in claim 1 is characterized in that described process gas is: Cl
220-40sccm, HBr 100-250sccm, He 3.5-21sccm, O
21.5-9sccm.
5. the gate etching process that can avoid little groove phenomenon as claimed in claim 4 is characterized in that described process gas is: Cl
225-35sccm, HBr 150-200sccm, He7-14sccm, O
23-6sccm.
6. the gate etching process that can avoid little groove phenomenon as claimed in claim 5 is characterized in that wherein process gas Cl
2Be 30sccm, HBr is 175sccm, He 10.5sccm, O
24.5sccm.
7. the gate etching process that can avoid little groove phenomenon as claimed in claim 1 is characterized in that described process gas total flow is 185-255sccm.
8. the gate etching process that can avoid little groove phenomenon as claimed in claim 1 is characterized in that described process gas total flow is 220sccm.
9. as the arbitrary described gate etching process that can avoid little groove phenomenon of claim 1-8, it is characterized in that basic point produces at 1/4th to 1/2nd places of etching lines height in the described base point etching, the angle of the horizontal sextant angle of basic point bottom sectional is the 40-60 degree.
10. as the arbitrary described gate etching process that can avoid little groove phenomenon of claim 1-8, it is characterized in that base point etching produces at 1/3rd places of etching lines height, the angle of the horizontal sextant angle of basic point bottom sectional is 50 degree.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2005101262996A CN100397587C (en) | 2005-12-05 | 2005-12-05 | Silicon gate etching process capable of avoiding microtrench phenomenon |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2005101262996A CN100397587C (en) | 2005-12-05 | 2005-12-05 | Silicon gate etching process capable of avoiding microtrench phenomenon |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1851873A CN1851873A (en) | 2006-10-25 |
CN100397587C true CN100397587C (en) | 2008-06-25 |
Family
ID=37133347
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005101262996A Active CN100397587C (en) | 2005-12-05 | 2005-12-05 | Silicon gate etching process capable of avoiding microtrench phenomenon |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN100397587C (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102280374A (en) * | 2010-06-08 | 2011-12-14 | 中国科学院微电子研究所 | Manufacturing method of silicon gate structure of 50nm and below |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102263064A (en) * | 2010-05-28 | 2011-11-30 | 中芯国际集成电路制造(上海)有限公司 | Method for forming discrete grid storage device |
CN102437026B (en) * | 2011-11-29 | 2017-07-11 | 上海华虹宏力半导体制造有限公司 | Groove etching method and method, semi-conductor device manufacturing method |
CN113571414A (en) * | 2021-09-24 | 2021-10-29 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1555087A (en) * | 2003-12-27 | 2004-12-15 | 上海华虹(集团)有限公司 | Method for eliminating grid etching lateral notch |
CN1588627A (en) * | 2004-07-12 | 2005-03-02 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method for increasing deep submicron multiple crystalline silicon grating etching uniformity |
CN1604277A (en) * | 2004-11-04 | 2005-04-06 | 上海华虹(集团)有限公司 | Method for eliminating transverse concave groove with nitrogen |
CN1700426A (en) * | 2004-05-21 | 2005-11-23 | 中国科学院微电子研究所 | Method for etching 15-50 nanowire wide polycrystalline silicon gate |
-
2005
- 2005-12-05 CN CNB2005101262996A patent/CN100397587C/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1555087A (en) * | 2003-12-27 | 2004-12-15 | 上海华虹(集团)有限公司 | Method for eliminating grid etching lateral notch |
CN1700426A (en) * | 2004-05-21 | 2005-11-23 | 中国科学院微电子研究所 | Method for etching 15-50 nanowire wide polycrystalline silicon gate |
CN1588627A (en) * | 2004-07-12 | 2005-03-02 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method for increasing deep submicron multiple crystalline silicon grating etching uniformity |
CN1604277A (en) * | 2004-11-04 | 2005-04-06 | 上海华虹(集团)有限公司 | Method for eliminating transverse concave groove with nitrogen |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102280374A (en) * | 2010-06-08 | 2011-12-14 | 中国科学院微电子研究所 | Manufacturing method of silicon gate structure of 50nm and below |
CN102280374B (en) * | 2010-06-08 | 2013-05-01 | 中国科学院微电子研究所 | Manufacturing method of silicon gate structure of 50nm and below |
Also Published As
Publication number | Publication date |
---|---|
CN1851873A (en) | 2006-10-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102187437B (en) | Silicon etch with passivation using chemical vapor deposition | |
CN108321079A (en) | Semiconductor structure and forming method thereof | |
CN101148765B (en) | Silicon chip etching method | |
CN104124194B (en) | The forming method of groove | |
CN102259832A (en) | Preparation method of three-dimensional nano structure array | |
CN100397587C (en) | Silicon gate etching process capable of avoiding microtrench phenomenon | |
CN102259831A (en) | Three-dimensional nano structure array | |
CN105584986B (en) | A kind of silicon deep hole lithographic method | |
CN106783866B (en) | The manufacturing method of flush memory device | |
CN108206131A (en) | The forming method of semiconductor structure and semiconductor structure | |
CN104752198B (en) | Substrate lithographic method | |
Mahorowala et al. | Etching of polysilicon in inductively coupled Cl 2 and HBr discharges. I. Experimental characterization of polysilicon profiles | |
CN107611027A (en) | A kind of method for improving deep silicon etching sidewall roughness | |
CN102142377B (en) | Production method of silicon groove of power MOS (Metal Oxide Semiconductor) device | |
CN106960812B (en) | Inclined hole etching method | |
CN108573867A (en) | Silicon deep hole lithographic method | |
TWI784796B (en) | Etching method of silicon wafer | |
CN100397586C (en) | Polycrystalline silicon pulse etching process for improving anisotropy | |
CN102412139A (en) | Plasma etching method of amorphous carbon hard mask | |
CN105720002B (en) | Inclined hole lithographic method | |
CN103137564B (en) | Method for achieving expanding base region structure in bipolar-complementary metal oxide semiconductor (BiCMOS) device | |
CN105720003B (en) | Deep silicon hole lithographic method | |
CN107437556A (en) | GAA structures MOSFET forming method | |
CN100442452C (en) | Plasma etching method | |
CN108133888B (en) | Deep silicon etching method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP03 | Change of name, title or address |
Address after: No. 8, Wenchang Avenue, Beijing economic and Technological Development Zone, 100176 Patentee after: Beijing North China microelectronics equipment Co Ltd Address before: 100016 Jiuxianqiao East Road, Chaoyang District, Chaoyang District, Beijing Patentee before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing |
|
CP03 | Change of name, title or address |